共查询到20条相似文献,搜索用时 31 毫秒
1.
《Electron Devices, IEEE Transactions on》2006,53(8):1937-1939
The electrical characteristics of layered$hboxAl_2hboxO_3/hboxPr_2hboxO_3/hboxAl_2hboxO_3$ metal–insulator–metal (MIM) capacitors for RF device applications are presented for the first time. This advanced dielectric layer system 4-nm$hboxAl_2hboxO_3/hbox8-nm hboxPr_2hboxO_3/hbox4-nm hboxAl_2hboxO_3$ shows a high capacitance density of 5.7$hboxfF/muhboxm^2$ , a low leakage current density of$hbox5 times hbox10^-9 hboxA/hboxcm^2$ at 1 V, and an excellent dielectric loss behavior over the studied frequency range. 相似文献
2.
《Microwave and Wireless Components Letters, IEEE》2006,16(9):493-495
A very high density of 35$hboxfF/muhboxm^2$ is measured in a radio frequency (RF) metal-insulator-metal (MIM) capacitor using high-$kappa (kappa=hbox169)$ $hboxSrTiO_3$ fabricated by very large scale integration (VLSI) back-end integration. A very small capacitance reduction of 4.1% from 100kHz to 10GHz, low leakage current of 1$times hbox10^-7 hboxA/cm^2$ at 1V are simultaneously measured. The small voltage dependence of a capacitance$Delta C/C$ of 637ppm is also obtained at 2GHz, which ensures this MIM capacitor useful for high precision circuits operated at a RF regime. 相似文献
3.
The dielectric properties of the amorphous BaSm2Ti4O12 (BSmT) film with various thicknesses were investigated to evaluate its potential use as a metal-insulator-metal (MIM) capacitor. An amorphous 35-nm-thick BSmT film grown at 300 degC exhibited a high capacitance density of 9.9 fF/mum2 at 100 kHz and a low leakage current density of 1.790 nA/cm2 at 1 V. The quadratic and linear voltage coefficients of capacitance of the film were 599 ppm/V2 and -81 ppm/V at 100 kHz, respectively. The temperature coefficient of capacitance of the film was also low about 236 ppm/degC at 100 kHz. These results confirmed the suitability of the amorphous BSmT film as a high-performance MIM capacitor 相似文献
4.
《Electron Device Letters, IEEE》2008,29(7):684-687
5.
New Curvature-Compensation Technique for CMOS Bandgap Reference With Sub-1-V Operation 总被引:3,自引:0,他引:3
《Circuits and Systems II: Express Briefs, IEEE Transactions on》2006,53(8):667-671
A new sub-1-V curvature-compensated CMOS bandgap reference, which utilizes the temperature-dependent currents generated from the parasitic n-p-n and p-n-p bipolar junction transistor devices in the CMOS process, is presented. The new proposed sub-1-V curvature-compensated CMOS bandgap reference has been successfully verified in a standard 0.25-$muhboxm$ CMOS process. The experimental results have confirmed that, with the minimum supply voltage of 0.9 V, the output reference voltage at 536 mV has a temperature coefficient of 19.5$hboxppm/^circhboxC$ from 0$^circhboxC$ to 100$~^circhboxC$ . With a 0.9-V supply voltage, the measured power noise rejection ratio is$-hbox25.5~hboxdB$ at 10 kHz. 相似文献
6.
《Electron Device Letters, IEEE》2009,30(6):614-616
7.
《Electron Device Letters, IEEE》2009,30(5):460-462
8.
《Components and Packaging Technologies, IEEE Transactions on》2006,29(3):570-576
We fabricated a silicon microrefrigerator on a 500-$mu$ m-thick substrate with the standard integrated circuit (IC) fabrication process. The cooler achieves a maximum cooling of 1$^circ$ C below ambient at room temperature. Simulations show that the cooling power density for a$hbox40times hbox40 muhboxm^2$ device exceeds 500$hboxW/cm^2$ . The unique three-dimensional (3-D) geometry, current and heat spreading, different from conventional one-dimensional (1-D) thermoelectric device, contribute to this large cooling power density. A 3-D finite element electrothermal model is used to analyze non-ideal factors inside the device and predict its limits. The simulation results show that in the ideal situation, with low contact resistance, bulk silicon with 3-D geometry could cool$sim hbox20 , ^circhboxC$ with a cooling power density of 1000$hboxW/cm^2$ despite the low thermoelectric figure-of-merit (ZT) of the material. The large cooling power density is due to the geometry dependent heat and current spreading in the device. The non-uniformity of current and Joule heating inside the substrate also contributes to the maximum cooling of silicon microrefrigerator, exceeding 30% limit given in one–dimensional thermoelectric theory$DeltaT_max=hbox0.5hboxZT_c^2$ , where$T_c$ is the cold side temperature. These devices can be used to remove hot spots on a chip. 相似文献
9.
Kyoung Pyo Hong Kyung-Hoon Cho Young Hun Jeong Sahn Nahm Chong-Yun Kang Seok-Jin Yoon 《Electron Device Letters, IEEE》2008,29(4):334-337
A small crystalline phase was formed in the Bi1.5ZnNb1.5O7 (BZN) film grown at 300degC on TiN/SiO2/Si substrate using RF-magnetron sputtering. A 46-nm-thick BZN film exhibited a high capacitance density of 13.6 fF/mum2 at 100 kHz with a dielectric constant of 71, which did not change even in the gigahertz range (1-6 GHz). The quality factor was high, approximately 50, at 2.5 GHz. The leakage-current density was low, approximately 5.66 nA/cm2, at 2 V. The quadratic voltage and temperature coefficients of capacitance were approximately 631 ppm/V2 and 149 ppm/degC at 100 kHz, respectively. These results indicate that the BZN film grown on TiN substrate at 300degC can be a good candidate material for metal-insulator- metal capacitors. 相似文献
10.
《Solid-State Circuits, IEEE Journal of》2006,41(9):2077-2082
A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-$muhbox m$ CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07$hbox mm^2$ and has a peak-to-peak jitter of$pm $ 6.6 ps at 1.3 GHz. 相似文献
11.
Hayakawa T. Yamamoto S. Hayashi H. Sakurai T. Hijikata T. 《Quantum Electronics, IEEE Journal of》1981,17(11):2205-2210
The threshold-current variation with temperature has been measured for Ga1-x Alx As double-heterostructure (DH) lasers with AlAs mole fraction in the active layerx of 0.08 and 0.2, and with several heterojunction step heightsDeltax . The threshold-temperature coefficient Jth (350 K)/Jth (300 K), which generally increases with decreasingDeltax , is found to be larger forx = 0.2 than that forx = 0.08 at the same value ofDeltax , and also to be larger for the lasers with smaller effective electron diffusion length in theP cladding layer, in the case ofx = 0.2 . These characteristics are well explained by a model of carrier leakage due to unconfined carriers in the active layer. It is confirmed by a good fit of the experimental results with the calculated values that the electron leakage in theGamma conduction band of theP cladding layer dominates forx leq 0.1 , but the hole leakage in theN cladding layer increases withx and becomes comparable in magnitude with the electron leakage atx sim 0.2 . 相似文献
12.
《Solid-State Circuits, IEEE Journal of》2006,41(10):2215-2223
In this paper, a monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX), which is intended for use in 80 Gbit/s optical fiber links, is presented. The integrated circuit (IC) is manufactured using an in-house InP double heterostructure bipolar transistor (DHBT) technology, exhibiting cut-off frequency values of more than 220 GHz for both$f_T$ and$f_max $ . The CDR circuit in the topology of a phase-locked loop (PLL) is mainly composed of a half-rate linear phase detector including a 1:2 demultiplexer (DEMUX), a loop filter, and a voltage-controlled oscillator (VCO). Hence, the corresponding architecture of each of these components as well as the applied circuit design technique are extensively addressed. Concerning the performance achieved by the CDR/DEMUX IC, the recovered and demultiplexed 40 Gbit/s data from an 80 Gbit/s input signal feature clear eye opening with a signal swing as high as 600$hboxmV_ pp$ . The extracted 40 GHz clock signal shows a phase noise as low as$- hbox98~dBc/hboxHz$ at 100 kHz offset frequency. The corresponding rms jitter amounts to 0.37 ps while the peak-to-peak jitter is as low as 1.66 ps. At a single supply voltage of$-hbox4.8~V$ , the power consumption of the full CDR/DEMUX IC amounts to 1.65 W. To the authors' best knowledge, this work demonstrates the first CDR circuit at the achieved data rate, regardless of all the competing semiconductor technologies. 相似文献
13.
《Electron Device Letters, IEEE》2008,29(9):984-987
14.
《Electron Device Letters, IEEE》2006,27(9):778-780
A novel 80 nm gate length strained-Si n-channel transistor structure with lattice-mismatched source and drain (S/D) formed on thin-body silicon-on-insulator substrate is reported. The strained transistor features silicon–carbon$(hboxSi_1 - yhboxC_y)$ S/D regions, which are pseudomorphically grown by selective epitaxy. The incorporated carbon mole fraction$y$ is 0.01. The lattice mismatch between$hboxSi_0.99hboxC_0.01$ and Si results in lateral tensile strain and vertical compressive strain in the Si channel region, both contributing to substantial electron mobility enhancement. The implementation of the$hboxSi_0.99hboxC_0.01$ stressors provides a substantial drive current$I_ Dsat$ enhancement of 11% over a control transistor at a gate length of 80 nm and a width of$simhbox1.1 muhboxm$ , while the enhancement for the linear drive current$I_ Dlin$ is approximately two times larger. Pulse measurements were also performed to correct for self-heating effects. 相似文献
15.
《Electronics Packaging Manufacturing, IEEE Transactions on》2006,29(1):10-16
Sn–Cu near eutectic solder bump was fabricated by electroplating for flip-chip, and its electroplating and bump characteristics were studied. A Si-wafer was used as a substrate and the under bump metallization (UBM) comprised 400 nm of Al, 300 nm of Cu, 400 nm of Ni, and 20 nm of Au sequentially from bottom to the top of the metallization. The electrolyte for plating Sn–Cu solder consisted of$hbox Sn^+2$ (concentration of 30 g/L) and$hbox Cu^+2$ (0.3 g/L) solutions with methasulfonic acid and deionized water. The experimental results showed that the plating ratio of the Sn–Cu increased from 0.25 to 2.7$mu/hbox min$ with increasing current density from 1 to 8$hbox A/dm^2$ . In this range of current density, the plated Sn–Cu maintained its composition nearly constant level as Sn-(0.9$sim$ 1.4)wt% Cu. The solder bump of typical mushroom shape with 120-$muhbox m$ stem diameter and 75-$muhbox m$ height was formed by plating at 5$hbox A/dm^2$ for 2 h. The mushroom bump changed its shape to the hemispherical type of 140-$muhbox m$ diameter by air reflow on a hot plate at 260$^circhbox C$ . The homogeneity of element distribution in the solder bump was examined, and Sn content in the mushroom bump appears to be uneven changed to more uniform after the air reflow. The highest shear bond strength of the Sn–Cu hemispherical bump showed 113 gf by reflowing at 260$^circhbox C$ for 10 s. 相似文献
16.
Shi-Jin Ding Hang Hu Lim H.F. Kim S.J. Yu X.F. Chunxiang Zhu Li M.F. Byung Jin Cho Chan D.S.H. Rustagi S.C. Yu M.B. Chin A. Dim-Lee Kwong 《Electron Device Letters, IEEE》2003,24(12):730-732
For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications. 相似文献
17.
《Electron Device Letters, IEEE》2006,27(10):821-823
In this letter, we demonstrate that negative bias temperature instability of high-$k$ $(hboxHfO_2/hboxSiO_2)$ gate dielectric stacks can be greatly improved by incorporating fluorine and engineering its concentration depth profile with respect to$hboxHfO_2/hboxSiO_2$ interface. It was found that fluorine is easily incorporated in$hboxHfO_2/hboxSiO_2$ at low temperatures$(leq hbox400 ^circhboxC)$ by$hboxF_2$ anneal in the presence of UV radiation. Fluorine tends to segregate at the$hboxHfO_2/hboxSiO_2$ interface and, to a lesser extent, diffuses into the underlying$hboxSiO_2/hboxSi$ interface. The$hboxHfO_2/hboxSiO_2$ stacks with F addition show significantly reduced ($≪$ 50%) positive charge trapping and interface states generation compared to control samples without F. 相似文献
18.
《Solid-State Circuits, IEEE Journal of》2009,44(7):1990-2001
19.
《Electron Device Letters, IEEE》2006,27(10):793-795
Enhancement-mode$hboxSi_3hboxN_4/hboxAlGaN/GaN$ metal–insulator–semiconductor HFETs (MISHFETs) with a 1-$muhboxm$ gate footprint are demonstrated by combining$hboxCF_4$ plasma treatment technique and a two-step$hboxSi_3hboxN_4$ deposition process. The threshold voltage has been shifted from$-$ 4 [for depletion-mode HFET] to 2 V using the techniques. A 15-nm$hboxSi_3hboxN_4$ layer is inserted under the metal gate to provide additional isolation between the gate Schottky contact and AlGaN surface, which can lead to reduced gate leakage current and higher gate turn-on voltage. The two-step$hboxSi_3hboxN_4$ deposition process is developed to reduce the gate coupling capacitances in the source and drain access region, while assuring the plasma-treated gate region being fully covered by the gate electrode. The forward turn-on gate bias of the MISHFETs is as large as 7 V, at which a maximum current density of 420 mA/mm is obtained. The small-signal RF measurements show that the current gain cutoff frequency$(f_T)$ and power gain cutoff frequency$(f_max)$ are 13.3 and 23.3 GHz, respectively. 相似文献
20.
《Electron Device Letters, IEEE》2009,30(7):715-717