使用输出分组和电路可满足性的等价性验证算法

介绍了一种使用电路可满足性解算器的组合电路等价性验证算法．对包含多输出的复杂验证问题,首先对联接电路作输出分组,将等价性验证问题转化为包含若干个组的电路可满足性问题,继而使用电路解算器解决问题．同时,注意各个子问题间的有用隐含信息的共享,减小了SAT推理的搜索空间．实验结果表明,该算法是实用有效的．     

带黑盒组合电路的等价性验证

为了在早期阶段发现电路设计错误,需要对包含未知部分的实现电路和规范电路进行等价性验证.本文提出了一种"分而治之"的方法,把电路划分成若干子电路,使用四值逻辑模拟技术对电路未知部分进行量化,然后对子电路的合取范式进行可满足性验证.这种方法增强了算法的错误检测能力,通过在ISCAS'85基准电路和10个简单组合电路上得到的两组实验数据表明了此算法的有效性和可行性.     

利用SMT约束分解方法求解RTL可满足性问题

随着集成电路技术与工艺的不断发展,目前工业界所采用的形式验证工具已很难适应集成电路规模的飞速增长.为了对RTL电路的可满足性问题进行形式验证,提出基于超图划分的约束分解实现可满足性模理论(SMT)求解的分级验证方法.通过分析RTL电路的结构约束,对约束集合中的元素和相关变量进行约束建模,并构建带有合适权重的超图模型;利用超图划分的机制寻找带有最小割集的等量划分,实现约束分解,完成RTL电路的定界模型检验.实验结果表明,该方法能够减小处理问题的规模和求解过程中的搜索空间,提高验证效率.     

一种验证服务组合中消息语义匹配的方法

介绍一种服务组合模型中服务消息语义化匹配验证的方法.该方法先介绍基于服务行为模型的服务组合,并将其转换为形式化的有限状态自动机.利用有限状态自动机中服务行为可以转换为线性逻辑表达式描述的原理,使用线性逻辑的演绎方法对服务消息的匹配性可满足性进行验证.     

基于布尔可满足性的电路设计错误诊断算法

提出了一种组合电路设计错误诊断算法,该算法结合传统基于模拟的方法和可满足性问题求解技术,在不依赖于故障模型的条件下实现对电路逻辑错误的诊断定位．提出了基于布尔可满足性的增量式电路诊断方法,通过对可满足解依据电路结构信息筛选分级,提高了多错误诊断定位的分辨率和准确性;并提出多项启发式方法,避免了大量不必要的操作,使算法在时间和内存上保持有效性．实验结果表明,利用形式验证的技术来导向模拟的过程,抓住了高复杂度的多错误定位问题的特征,提高了电路错误诊断的效率．     

服务组合中基于线性逻辑的消息语义匹配

介绍一种自动服务组合模型服务消息语义化匹配验证的方法。该方法先从服务描述中提取服务消息模型和服务行为模型,后将服务行为模型转换为形式化的有限状态自动机。根据有限状态自动机中的服务接口可以转化为本体概念,服务行为可以转换为线性逻辑表达式描述,使用线性逻辑的演绎方法对服务消息的匹配性和可满足性进行验证。同时,对线性逻辑的演绎定理进行适当扩展以适应服务组合的需要。     

CSPack:采用CSP图匹配的新型装箱算法

现代FPGA芯片可编程单元的日益复杂化对装箱提出了更大挑战,为了使依赖硬件结构的装箱过程不断适应芯片结构变化的过程,提出一种基于CSP图匹配的装箱算法CSPack.用配置库来描述芯片可编程逻辑块的各种电路功能,根据配置库并利用CSP图匹配算法进行电路匹配,找出满足约束的子电路,并以指令的形式将子电路映射到可编程逻辑块内.该算法已经应用于复旦大学自主研发的FPGA芯片FDP2008软件流程的装箱模块中,且针对不同芯片系列只需修改描述芯片功能配置的文件就能实现装箱.实验结果表明,与T-VPack算法相比,CSPack算法在时序性能上提升了6.1%,同时可减少1.4%的芯片占用面积.     

SpaceWire译码电路在HOL4中的形式化验证

SpaceWire是在苛刻环境下的高速通信总线协议,译码电路是其接收端的关键电路,对该电路进行形式化验证具有重要的现实意义.形式化验证方法中的定理证明将需要分析的电路进行形式化建模,结合定理证明器,对模型的性质进行严格推理从而完成验证.本文运用定理证明的方法,在高阶逻辑证明工具HOL4中对SpaceWire总线的译码电路进行形式化验证.首先根据SpaceWire标准规范抽取相关性质,用高阶逻辑语言形式化描述;然后分析电路设计中的VHDL代码,依据代码实现的功能用相应的逻辑谓词建模;最后在HOL4中证明了译码电路设计的模型能满足所提取的性质.本文同时给出了形式化建模的方法和验证过程.     

基于线性规划的RTL可满足性求解和性质检验

采用线性规划作为基本工具开发一个RTL可满足性求解器,并将其应用于解决RTL性质检验问题．深入研究了使用线性规划约束对RTL电路元器件的建模方法,得到了一种对RTL电路建模的通用方法．通过将RTL性质转化为虚拟RTL电路,找到了一种验证RTL性质的方法．通过实验,并与采用zchaff布尔可满足性求解器的模型检验工具NuSMV进行比较,证明了基于RTL可满足性求解器的性质验证方法在内存和时间消耗上具有相当大的优势．     

RTL验证中的混合可满足性求解

RTL混合可满足性求解方法分为基于可满足性模理论(SMT)和基于电路结构搜索两大类.前者主要使用逻辑推理的方法,目前已在处理器验证中得到了广泛的应用,主要得益于SMT支持用于描述验证条件的基础理论;后者能够充分地利用电路中的约束信息,因而求解效率较高.介绍了每一大类中的典型研究及其所采用的重要策略,以及RTL可满足性求解方面的研究进展.     

数字电路门级并行逻辑模拟

对基于事件驱动的电路门级并行逻辑模拟算法和相应的电路划分算法进行了研究。在保守协议的基础上,模拟算法采用流水线技术避免了死锁;采用事件打包,消息队列和非阻塞通讯技术减少了消息传递开销。在聚集分解的基础上,电路划分算法对组合或时序电路都可进行非循环划分,保证流水线模拟不会出现死锁。在曙光集群上采用MPI实现了模拟算法,对ISCAS部分电路进行实验,获得了很好的加速比。最后提出采用预模拟方法的电路划分改进方案。     

Physical synthesis of quantum circuits using templates

Similar to traditional CMOS circuits, quantum circuit design flow is divided into two main processes: logic synthesis and physical design. Addressing the limitations imposed on optimization of the quantum circuit metrics because of no information sharing between logic synthesis and physical design processes, the concept of “physical synthesis” was introduced for quantum circuit flow, and a few techniques were proposed for it. Following that concept, in this paper a new approach for physical synthesis inspired by template matching idea in quantum logic synthesis is proposed to improve the latency of quantum circuits. Experiments show that by using template matching as a physical synthesis approach, the latency of quantum circuits can be improved by more than 23.55 % on average.     

Generalized disjunction decomposition for evolvable hardware.

Evolvable hardware (EHW) refers to self-reconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the "generalized disjunction decomposition" (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the (1 + lambda) evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided.     

LORES-2: A Logic Reorganization System

LORES-2 is a logic reorganization system which greatly contributes to the effective automation of logic design. LORES-2 uses a macro-expansion technique to help designers transform printed-circuit assembly logic composed of SSI and MSI circuits into master-slice LSI logic circuits. The number of gates of the most reorganized LSI circuit falls within ± 20 percent of the number of gates of the original circuit. When ROMS and/or PLAs are not-allowed on the target LSI circuit, those elements are converted into optimized, multilevel random logic using logic minimization, factoring and macro-expansion techniques.     

A new automated design and optimization method of CMOS logic circuits based on Modified Imperialistic Competitive Algorithm

This paper proposes a novel evolutionary approach based on modified Imperialist Competitive Algorithm for combinational logic circuits designing and optimization. The Imperialist Competitive Algorithm operates on real values and is not applicable to logic circuits optimization problems. So a modified version of ICA is proposed to overcome this shortcoming. Modification of the algorithm depends on random cell replacement between Imperialist and its colonies as assimilation policy. Also a multi-objective evaluation mechanism in the form of a weighted cost function is introduced to obtain optimized circuits in case of circuit area and propagation delay. To evaluate the effectiveness of this method some general benchmark circuits are used in which the circuits with fewer logic cells (minimized space) and lower propagation delay are obtained. The simulation results of our proposed method are compared with some conventional and heuristic methods. Simulation results show that our proposed method significantly improves the performance factor which represents both circuit area and propagation delay.     

EDOA: an efficient delay optimization approach for mixed-polarity Reed-Muller logic circuits under the unit delay model

Delay optimization has recently attracted significant attention. However, few studies have focused on the delay optimization of mixed-polarity Reed-Muller (MPRM) logic circuits. In this paper, we propose an efficient delay optimization approach (EDOA) for MPRM logic circuits under the unit delay model, which can derive an optimal MPRM logic circuit with minimum delay. First, the simplest MPRM expression with the fewest number of product terms is obtained using a novel Reed-Muller expression simplification approach (RMESA) considering don’t-care terms. Second, a minimum delay decomposition approach based on a Huffman tree construction algorithm is utilized on the simplestMPRM expression. Experimental results on MCNC benchmark circuits demonstrate that compared to the Berkeley SIS 1.2 and ABC, the EDOA can significantly reduce delay for most circuits. Furthermore, for a few circuits, while reducing delay, the EDOA incurs an area penalty.     

多阈值神经元电路设计及在多值逻辑中的应用

分析了多阈值神经元工作原理,并提出设计多阈值神经元电路的方法．首先,用两个MOS晶体管组成电压型突触电路,然后又提出一种基于BiCMOS工艺的判别转换开关电路,这种电路以压控电流作为阈值信号,并实现电压到电流的转换．在此基础上,结合限幅电压开关理论提出多阈值神经元阈值判别函数电路的开关级设计方法．最后,从开关级设计了实现三值逻辑中文字、与、或三种基本运算的多阈值神经元电路,用这三种基本运算的多阈值神经元电路可实现任意三值函数的多阈值神经网络．文章还对设计出的电路用PSPICE进行模拟,测量相关参数．模拟结果表明,该文设计的电路不仅实现了正确的逻辑功能,而且速度较快。     

Dual threshold voltage and sleep switch dual threshold voltage DOIND approach for leakage reduction in domino logic circuits

Subthreshold leakage current becomes the major component of total power dissipation as scaling down the feature size. In this paper, two new circuit techniques are proposed for reducing the subthreshold leakage power consumption in domino logic circuit. Dual threshold voltage DOIND (Domino logic with clock and input dependent transistors) and NMOS sleep switch dual threshold voltage DOIND circuits for low leakage domino logic circuits are presented. High threshold voltage transistors are utilized to reduce the leakage current and a sleep transistor is added to the dynamic node that strongly turnoff all the high threshold voltage transistor and significantly reduce the subthreshold leakage power. The proposed circuit techniques, dual threshold voltage DOIND logic and sleep switch dual threshold voltage DOIND logic reduces the leakage current by 71.46 and 74.86% respectively as compared to standard domino logic circuit. Simulation results also shows that both the circuits are less affected by supply and temperature variations. The proposed sleep switch dual threshold voltage DOIND exhibits 19.95% less power consumption with 24% die area overhead for the buffer circuit as compared to standard domino logic circuit. The proposed sleep switch dual threshold voltage DOIND logic has improved normalized figure of merit of 1.17 as compared to standard domino logic circuit.

     

A recursive method for synthesizing quantum/reversible quaternary parallel adder/subtractor with look-ahead carry

Multiple-valued quantum logic circuits are a promising choice for future quantum computing technology since they have several advantages over binary quantum logic circuits. Adder/subtractor is the major component of the ALU of a computer and is also used in quantum oracles. In this paper, we propose a recursive method of hand synthesis of reversible quaternary full-adder circuit using macro-level quaternary controlled gates built on the top of ion-trap realizable 1-qudit quantum gates and 2-qudit Muthukrishnan–Stroud quantum gates. Based on this quaternary full-adder circuit we propose a reversible circuit realizing quaternary parallel adder/subtractor with look-ahead carry. We also show the way of adapting the quaternary parallel adder/subtractor circuit to an encoded binary parallel adder/subtractor circuit by grouping two qubits together into quaternary qudit values.