A CMOS Imager with On-Chip Temporal Filtering for Motion Pre-Processing

Previous hardware implementations of the Reichardt motion detection model based on the fly visual system suffer from drawbacks such as large pixel area and fixed spatial frequency response. In this work, we introduce a two-stage implementation of the Reichardt model in order to overcome these issues. We perform the pixel-level temporal filtering required for motion processing along with photoreception on a single analog chip using continuous-time low-order filters. The rest of the computation—spatial filtering and correlation—is performed on a subsequent discrete-time digital processing stage. We designed and tested an integrated CMOS imager with integrated, pixel-level temporal filtering necessary for motion detection. This temporal filtering enhances transients and provides a delayed and non-delayed channel for each pixel in the array. By varying bias currents on the chip, we are able to control the time constant of continuous-time low pass filters that set the delay and hence the temporal response of the imager. By varying a reset switching frequency, we can control the high pass filter time constant which determines the time course of transient enhancement. Operation primarily in weak inversion results in a low-power sensor well suited for integration into a motion processing system. We have constructed a 16 × 16 temporal processing array in a 0.5 m CMOS process. Motion information is extracted by post processing the imager output in a discrete time domain, which validates the functionality of the temporal filters.     

A Smart-Scanning Analog VLSI Visual-Attention System

We have implemented a hardware model of selective visual attention within the neuromorphic, analog VLSI paradigm. The system includes a highly-parallel winner-take-all selection with excitatory and inhibitory influences. The selection specifies positions of attention based on an array of intensity levels, which comprise a primitive saliency map. The excitation and inhibition control the strategy for shifts of attention from one position to the next. The combination of these fundamental building blocks demonstrates emergent properties that can be observed in real time due to the parallel hardware implementation. The system behaves as a smart-scanning sensor array. The basic characteristics of the scanning pattern are controlled by setting a number of analog parameters. In this paper we describe the system, focusing on the role that inhibition plays in the redirection of attention. We show experimental results from one-dimensional implementations of the hardware model. Analysis that explains the expected behavior for the two-element mode of operation is presented. The theoretical predictions are compared to experimental results.     

一种运动自适应去隔行技术及其VLSI结构

提出一种有效的运动自适应去隔行算法.该算法通过对同极性的相邻场进行运动检测,把插值点所处的区域分为快速运动区域、慢速运动区域和静止区域,对不同的区域采用不同的插值算法.在边缘检测方面,采用改进型ELA算法克服了传统的ELA算法处理水平边缘方面的不足,使边缘得到有效保护.与运动补偿算法相比,该算法计算复杂度较低,易于VL...     

A Pulsed Communication/Computation Framework for Analog VLSI Perceptive Systems

This paper presents the principles, the main propertiesand some applications of a pulsed communication system adaptedto the needs of the analog VLSI implementation of perceptivesystems. The system takes advantage of the fact that activitiesin perception tasks are often sparsely distributed over a largenumber of elementary processing units (cells) and facilitatesaccess to the communication channel for the more active cells.The resulting architecture can be advantageously used to setup connections between distant cells on the same chip or point-to-pointconnections between cells on different chips when direct wiringis prohibitive. Cells communicate in an asynchronous fashionwhich conserves the fine time relationships of events. The systemalso lends itself to the simple circuit implementation of typicalbiologically inspired connectivity patterns such as projectionof the activity of one cell on a region (its projective field)of the next neural processing layer, which can be on a differentchip in an actual implementation, as is the case for one of theapplications presented: an oriented-edges enhancement system.     

一种全搜索块匹配运动估计VLSI结构

提出了一种新的两维全搜索运动估计VLSI结构。该结构基于两维脉动阵列,能够完全实现两维数据重用,减少了对外部存储器数据量的访问,具有100%的硬件效率和高吞吐率。该结构也可以很容易地应用于不同块尺寸、不同的搜索范围的全搜索块匹配运动估计,具有通用性。     

基于HEVC六边形运动估计算法的VLSI设计

运动估计是HEVC中计算量最大、耗时最多的模块。为了加速编码过程,设计了适用于HEVC运动估计的六边形搜索算法的VLSI架构。该架构支持HEVC标准中的尺寸可变块设计,并且充分考虑六边形模板的数据复用特点,在PE阵列中使用流水线的组织策略,有效降低了片上缓存的访问次数。采用SMIC 65 nm工艺综合该电路,最高工作频率可达100 MHz,电路规模101 k门,能够满足高清视频（1 920×1 080,60帧/秒）的实时编码要求。     

A Modular Multi-Chip Neuromorphic Architecture for Real-Time Visual Motion Processing

The extent of pixel-parallel focal plane image processing is limited by pixel area and imager fill factor. In this paper, we describe a novel multi-chip neuromorphic VLSI visual motion processing system which combines analog circuitry with an asynchronous digital interchip communications protocol to allow more complex pixel-parallel motion processing than is possible in the focal plane. This multi-chip system retains the primary advantages of focal plane neuromorphic image processors: low-power consumption, continuous-time operation, and small size. The two basic VLSI building blocks are a photosensitive sender chip which incorporates a 2D imager array and transmits the position of moving spatial edges, and a receiver chip which computes a 2D optical flow vector field from the edge information. The elementary two-chip motion processing system consisting of a single sender and receiver is first characterized. Subsequently, two three-chip motion processing systems are described. The first three-chip system uses two sender chips to compute the presence of motion only at a particular stereoscopic depth from the imagers. The second three-chip system uses two receivers to simultaneously compute a linear and polar topographic mapping of the image plane, resulting in information about image translation, rotation, and expansion. These three-chip systems demonstrate the modularity and flexibility of the multi-chip neuromorphic approach.     

基于望远镜搜索的块匹配运动估值的低功耗VLSI结构

在一种基于望远镜搜索的块匹配运动估值的 VL SI实现中 ,对用于加速搜索的传统心动阵列引擎进行了结构上的改进 ,从而能够显著地降低功耗 .方法是使用一种新的块匹配误差计算的提早跳出技术 ,并通过在阵列处理单元中屏蔽操作数来避免不必要的计算操作 .基于算法模拟结果的简单估计表明 :使用新结构搜索引擎的运动估值 ,功耗可降低到原来的 40 %左右 ,而仍然保持着相同的处理速度和相似的视频解码图质量 .     

基于纹理图像的MPEG-4运动补偿电路的VLSI设计

在采用外部存储和内部缓存的两级存储方案的基础上,提出了一种基于纹理图像的MPEG-4ASP@L5运动补偿电路的硬件结构,并完成了VLSI设计。针对运动向量的预测算法,在满足实时译码的前提下对电路的内部缓存LM2进行了优化。对于重叠块运动补偿算法,提出了一种有效的双循环替换缓存结构。采用TSMC0.25μm1P5MCMOS工艺,完成了运动补偿电路的VLSI实现,芯片内核面积为1.31mm×1.31mm,最高工作频率150MHz。系统仿真结果表明该电路可在120MHz的频率下对符合ASProfile标准的ITU-R601格式的纹理视频流进行实时运动补偿。     

稳健的预分析多直线全局运动估计方法

本文提出了RTSG图像预分析和多直线全局运动估计方法,该方法首先根据光流场方程得到RTSG图像,并对RTSG图像进行预分析以去除图像中的外点和确定全局运动模型,然后提取多个直线特征元,利用直线特征元估计局部运动参数,最后用局部运动参数和与之相关的权值进行全局运动估计。     

GRAdient Broadcast: A Robust Data Delivery Protocol for Large Scale Sensor Networks

Although data forwarding algorithms and protocols have been among the first set of issues explored in sensor networking, how to reliably deliver sensing data through a vast field of small, vulnerable sensors remains a research challenge. In this paper we present GRAdient Broadcast (GRAB), a new set of mechanisms and protocols which is designed specifically for robust data delivery in face of unreliable nodes and fallible wireless links. Similar to previous work [12,13], GRAB builds and maintains a cost field, providing each sensor the direction to forward sensing data. Different from all the previous approaches, however, GRAB forwards data along a band of interleaved mesh from each source to the receiver. GRAB controls the width of the band by the amount of credit carried in each data message, allowing the sender to adjust the robustness of data delivery. GRAB design harnesses the advantage of large scale and relies on the collective efforts of multiple nodes to deliver data, without dependency on any individual ones. We have evaluated the GRAB performance through both analysis and extensive simulation. Our analysis shows quantitatively the advantage of interleaved mesh over multiple parallel paths. Our simulation further confirms the analysis results and shows that GRAB can successfully deliver over 90% of packets with relatively low energy cost, even under the adverse conditions of 30% node failures compounded with 15% link message losses.Fan Ye received his B.E. in Automatic Control in 1996 and MS in Computer Science in 1999, both from Tsinghua University, Beijing, China. After that, he has been pursuing a Ph.D. degree at UCLA. His research interests are in network protocol design, with focus on data forwarding, power management and security in large scale sensor networks.Gary Zhong is currently pursuing M.S. degree in computer science at University of California, Los Angeles. He received his B.S. degree in computer science and engineering from University of California, Davis. His research interests include wireless networking, mobile computing, and large scale sensor networks.Songwu Lu received both his M.S. and Ph.D. from University of Illinois at Urbana-Champaign. He is currently an assistant professor at UCLA Computer Science. He received NSF CAREER award in 2001. His research interests include wireless networking, mobile computing, wireless security, and computer networks.Lixia Zhang received her Ph.D in computer science from the Massachusetts Institute of Technology. She was a member of the research staff at the Xerox Palo Alto Research Center before joining the faculty of UCLAs Computer Science Department in 1995. In the past she has served on the Internet Architecture Board, Co-Chair of IEEE Communication Society Internet Technical Committee, the editorial board for the IEEE/ACM Transactions on Networking, and technical program committees for many networking-related conferences including SIGCOMM and INFOCOM. Zhang is currently serving as the vice chair of ACM SIGCOMM.     

压电双晶梁MEMS传感器的稳健设计研究

微机电系统(MEMS)传感器结构参数的微小变差会影响其性能稳定。为提高MEMS传感器性能的稳健性,以压电双晶梁MEMS传感器为例,根据Smits模型,分析压电双晶梁的设计变量和噪声因素的随机性,建立基于随机模型的稳健设计数学模型;编制算法程序,确定MEMS传感器的最优设计解结果优于原设计方案。对比其稳健设计容差模型所得优化解,两者误差率为6.17%,验证了稳健设计结果的正确性。研究表明,即使设计变量存在变差,稳健设计仍能提高MEMS传感器的性能,并保证设计解的稳健性。     

模拟VLSI电路故障诊断的相关分析法

为了提高模拟VLSI电路的测试精度,提出了一种基于数字信号处理的模拟VLSI电路测试方法,将测试响应经余弦调制实现的数字滤波器组完成子带滤波,随后对各子带滤波序列进行能量计算和相关分析,实现模拟响应的数字特征提取,对国际标准电路中的19个故障的实验表明：子带滤波序列的能量计算适合诊断硬故障; 相关分析既可诊断硬故障,又可诊断软故障,实验还表明该方法对故障的分辨率远高于文献[7]。     

用于传感器信号获取的模数转换器研究进展

物联网和人工智能等应用的快速发展需要各种类型高灵敏度传感器的支撑,而传感器获取信号的质量和获取效率在很大程度上取决于读出电路中模数转换器(ADC)的性能。文章在简要介绍2种典型全集成传感器的特点和工作原理的基础上,详细讨论用于传感器信号获取的ADC研究进展,主要包括目前被广泛研究和应用的4类ADC(Σ-ΔADC、逐次逼近型ADC、双积分型ADC以及混合型ADC)的工作原理、优缺点、应用范围和发展动态。     

A VLSI model for residue number system architectures

Combining the Residue Number System as a computational tool and VLSI as a fabrication medium promises to provide modular and cost efficient implementation of many digital signal processing algorithms. In this paper, a memory model has been developed. It is a low level model, which is used to derive relationships between the size of each modulus (in the chosen number system), and both chip area and time required for implementing the corresponding look-up tables. The memory model allows the selection of the most efficient layout for memories which do not have power of two dimensions. A set of multi-look-up table modules has been proposed as building block units for implementing digital signal processing algorithms. A procedure has been developed to optimize the area and time of those modules.     

一种适合于低代价、低功耗VLSI实现的块匹配运动估值算法

本文给出了一种用于块匹配运动估值的改进的多分辨率望远镜搜索(MRTlcS)算法.它以望远镜的逆向搜索取代了传统的望远镜搜索,这一改进有效地降低了VLSI实现时对片上存储器容量和带宽的要求.此外本文还采用运动跟踪和自适应搜索窗技术来减小运动估值的计算复杂性.适合于低代价、低功耗VLSI实现是新算法的显著特点.模拟结果表明新算法要求的平均运算量仅为MRTlcS算法的30%左右,而仍然可以得到相似的视频解码图质量.本文也给出了新算法和MRTlcS算法用于VLSI实现时的硬件代价和功耗比较.     

运动补偿预测残差稀疏重构的分布式压缩视频传感

针对低复杂度视频编码需求,基于压缩传感(CS：Compressive Sensing)理论,提出了一种分布式压缩视频传感算法。低复杂度的编码器独立随机投影关键帧和CS帧,采集压缩视频数据;在解码端进行运动补偿预测以利用帧间相关性,对预测残差稀疏重构实现CS帧重建。仿真测试表明,与现有的三种压缩视频传感算法相比,所提算法重建的视频质量更好,适合无线视频监控及无线视频传感网络等应用。     

A CMOS Image Processing Sensor for the Detection of Image Features

A compact CMOS vision sensor for the detection of higher level image features, such as corners, junctions (T-, X-, Y-type) and linestops, is presented. The on-chip detection of these features significantly reduces the data amount and hence facilitates the subsequent processing of pattern recognition. The sensor performs a series of template matching operations in an analog/digital mixed mode for various kinds of image filtering operations including thinning, orientation decomposition, error correction, set operations, and others. The analog operations are done in the current domain. A design procedure, based on the formulation of the transistor mismatch, is applied to fulfill both accuracy and speed requirements. The architecture resembles a CNN-UM that can be programmed by a 30-bit word. The results of an experimental 16 × 16 pixel chip demonstrate that the sensor is able to detect features at high speed due to the pixel-parallel operation. Over 270 individual processing operations are performed in about 54 μsec. Masatoshi Nishimura was born in 1962 in Japan. He received his B.S. degree in mathematical engineering and information physics from the University of Tokyo in 1984. In 2001 he received his Ph.D. in Electrical Engineering from the University of Pennsylvania. His Ph.D. research focused on biologically inspired algorithms for the feature detection in visual images. Except for the three years he spent at University of Pennsylvania, he has been working for Sankyo since 1984, where he has been involved in the research and development of medical instruments including a microchip for capillary electrophoresis. He is currently working in the field of bioinformatics. Jan Van der Spiegel received his Masters and Ph.D. degrees in Electrical Engineering from the University of Leuven, Belgium, in 1974 and 1979, respectively. He joined the University of Pennsylvania in 1981 where he is currently a Professor of Electrical and Systems Engineering and the director of the Center for Sensor Technologies. He was the chairman of the Department of Electrical Engineering from 1998 to 2002 and the interim chairman of the Electrical and Systems Engineering department at the University of Pennsylvania from 2002 to 2004. His research interests are in mixed-mode VLSI design, biologically based sensors and sensory information processing systems, micro-sensor technology, and analog-to-digital converters. He is the author of over 150 journal and conference papers and holds 4 patents. He is a Fellow of the IEEE (2002) and the recipient of the IEEE Third Millennium Medal, the UPS Foundation Distinguished Education Chair and the Bicentennial Class of 1940 Term Chair. He received the Christian and Mary Lindback Foundation, and the S. Reid Warren Award for Distinguished Teaching. He was also Editor of Sensors and Actuators A for North and South America from 1983 to 2004.     

A Folded Configuration of a Fiber Sagnac-Based Sensor Array

We introduce a folded configuration of a previously described Sagnac interferometer-based sensor array. It is shown that the folded configuration lessens the detrimental effects of distributed phase modulations in the delay coil while also reducing the required delay coil length by a factor of 2. A prototype two-sensor array was constructed and measured to perform according to theory, exhibiting a phase sensitivity of roughly in a single-port detection configuration and in a balanced detection configuration. The desensitization of the delay coil was measured to agree with theory.     

基于改进PSO的WMSNs覆盖增强算法

对无线多媒体传感器网络(WMSNs)的覆盖增强问题进行了研究.在WMSNs网络中,视频、图像节点的视角范围有限,只能监控周围的部分区域.由于节点数量众多、部署方式受限等原因,网络中往往存在大量的监测重叠与监控盲区,需要对各节点的感知方向进行优化,以提高网络的监控质量.文中基于有向感知模型,提出了一种覆盖增强算法MCE.MCE对各节点的感知方向进行调整,并使用了改进的PSO算法来计算求解.仿真实验表明,MCE算法能够有效地提高网络的覆盖率.