可预置绝热触发器的设计及其应用

研究了采用交流能源的可预置绝热触发器。首先对CMOS电路的能量恢复原理进行了分析，在此基础上，提出了性能良好的低功耗绝热触发器，并设置了它的预置控制端，使该触发器可方便地应用于时序电路设计。验征了采用该触发器设计时序系统的实例。SPICE模拟表明，所设计的电路具有正确的逻辑功能及低功耗的优点。     

绝热电路稳定性和三时钟绝热同步时序电路

因为稳定性对绝热同步时序电路实现的重要性，该文首先提出绝热记忆电路的稳定性条件。依据稳定性条件，该文证明三相时钟是满足电路稳定性的最小值。在此基础上该文又提出三相时钟绝热动静态触发器，用此触发器设计出带有反馈清0的绝热可变计数电路。最后用计算机模拟程序检验绝热触发器和可变计数电路的结果。     

绝热无比型动态触发器和同步时序电路综合

该文从电路三要素理论出发研究低功耗电路，定量描述绝热无比型动态记忆电路。绝热无比型动态触发器利用电容接收和保存信息，避免目前绝热电路中电容上的信息得而复失的现象，其中绝热D和T'触发器只用6管，带‘与或非’输入的绝热D触发器只用9管。在上述理论基础上该文提出绝热无比型动态同步时序电路综合方法，用此法设计出绝热5421BCD码十进制计数器，仅用32管，总功耗小于一个PAL－2N四位二进制计数器的功耗，计算机模拟验证该文方法正确。     

基于AERL的低功耗绝热JK触发器的研究

提出了一种低功耗的绝热JK触发器电路。在绝热AERL(Approved Energy Recovery Logic)反相器电路的基础上,提出了AERL反相器级联及AERL JK触发器的实现方法。在0.5微米PTM工艺下用Spice工具对提出的电路进行了模拟仿真。结果显示与传统的CMOS JK触发器和ECRL JK触发器相比,AERL JK触发器具有更低的功耗。     

三值低功耗多米诺JKL触发器设计及应用

通过对三值触发器和绝热多米诺电路的研究,提出一种新颖低功耗多米诺JKL触发器开关级设计方案。该方案首先利用开关—信号理论,根据三值JKL触发器真值表,推导出三值绝热多米诺JKL触发器开关级结构式;然后利用三值JKL触发器实现三值正循环门电路和三值反循环门电路的设计;最后,经Spice软件模拟证明所设计的三值绝热多米诺JKL触发器逻辑功能正确,与常规三值多米诺JKL触发器相比,能耗节省约69%。     

采用交流能源的低功耗绝热触发器

研究采用交流能源的绝热触发器。首先提出绝热触发器结构并进行了详细分析，然后讨论绝热时序电路的设计，通过扭环形计数器的设计演示了绝热时序电路的设计方法。应用MOSIS的0．25μmCMOS工艺参数，经SPICE模拟证实了设计的电路具有正确的逻辑功能与可观的能量节省。     

静态绝热CMOS记忆电路和信息恢复能力

通过等效电路分析、考虑参数选取和整体时序电路的实现,提出具有信息恢复能力的静态绝热CMOS记忆电路.认为整体绝热电路结构最好融合输入、输出电路和记忆电路、时序电路为一体,由主触发器集合和从触发器集合相互连接构成,其中含有输出和反馈从触发器.采用绝热取样输入电路实现信息记忆单元接收代码和保存信息时将信息单元与外输入隔离.还设计出5421BCD码10进制和7进制可变计数器(带有进位输出从触发器和反馈清0从触发器),用计算机模拟程序检验电路的正确性.     

静态绝热CMOS记忆电路和信息恢复能力

通过等效电路分析、考虑参数选取和整体时序电路的实现,提出具有信息恢复能力的静态绝热CMOS记忆电路.认为整体绝热电路结构最好融合输入、输出电路和记忆电路、时序电路为一体,由主触发器集合和从触发器集合相互连接构成,其中含有输出和反馈从触发器.采用绝热取样输入电路实现信息记忆单元接收代码和保存信息时将信息单元与外输入隔离.还设计出5421BCD码10进制和7进制可变计数器(带有进位输出从触发器和反馈清0从触发器),用计算机模拟程序检验电路的正确性.     

静态绝热CMOS记忆电路和信息恢复能力

通过等效电路分析、考虑参数选取和整体时序电路的实现 ,提出具有信息恢复能力的静态绝热 CMOS记忆电路 .认为整体绝热电路结构最好融合输入、输出电路和记忆电路、时序电路为一体 ,由主触发器集合和从触发器集合相互连接构成 ,其中含有输出和反馈从触发器 .采用绝热取样输入电路实现信息记忆单元接收代码和保存信息时将信息单元与外输入隔离 .还设计出 5 4 2 1BCD码 10进制和 7进制可变计数器 (带有进位输出从触发器和反馈清 0从触发器 ) ,用计算机模拟程序检验电路的正确性     

交叉耦合绝热动态触发器及同步动态时序电路

本文提出交叉耦合绝热动态触发器及其同步时序电路综合方法。首先利用文献[1]的电路三要素理论定量描述交叉耦合型绝热锁存器，由绝热主锁存器和从锁存器构成一个单相输入的绝热触发器。在交叉耦合型绝热触发器的基础上，本文提出绝热同步动态时序电路综合方法，用此法设计出绝热8421BCD码错码检测电路（仅用50管），总功耗小于三个绝热ADL非门的功耗，计算机模拟验证本文方法的正确性。     

基于绝热逻辑的低功耗乘法器电路设计

基于绝热开关理论的能量回收逻辑与传统的静态CMOS逻辑相比,能够大大减少电路的功率消耗。这里介绍了一种使用单相正弦电源时钟的能量回收逻辑,分别用静态CMOS逻辑和这种能量回收逻辑设计,并仿真了一个两位乘法器电路,比较了这两种电路的性能。研究表明,采用能量回收逻辑设计的乘法器显著降低了电路的功率消耗。     

Improved structure for adiabatic CMOS circuits design

Two adiabatic circuits with complementary structure and operation are proposed in this paper. They employ two-phase sinusoidal power clock. The power consumption of the proposed circuits is comparable to that of some previously reported circuits. The problem of floating output nodes is solved by connecting two MOS transistors to the power clock. In particular, using the proposed architecture more than one stage of gates can be computed simultaneously within a single clock-phase, compared to only one stage is computed in every phase by most other adiabatic logic families. With this feature, the latency of the complex logic circuit is greatly improved and the number of buffers required for a pipelining circuit is also reduced. In this paper, a 2:1 multiplexer and full adder are illustrated and simulated. From the PSPICE simulation results, the effectiveness of the proposed approach and the low power characteristic of the designed circuits are validated.     

A Low Power 16‐Bit RISC Microprocessor Using ECRL Circuits

This paper presents a low power 16‐bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a 0.35 µm CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four‐phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non‐adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.     

Adiabatic-CMOS/CMOS-adiabatic logic interface circuit

This paper describes the design of an adiabatic-CMOS/CMOS-adiabatic logic interface circuit for a group of low-power adiabatic logic families with a similar clocking scheme. The circuit provides interfacing between several recently proposed low-power adiabatic logic circuits and traditional digital CMOS circuits. One advantage of this design is that it is insensitive to clock overlap. With the proposed interface circuit, both adiabatic and CMOS logic circuits are able to co-exist on a single chip, taking advantage of the strengths of each approach in the design of low power systems.     

Design of ternary adiabatic multiplier on switch-level

The design of ternary adiabatic multiplier adopting switch-level design techniques is proposed in this paper. First by using the theory of three essential circuit elements, the switch-level functional expressions of the carry and product circuit models, which compose one bit ternary adiabatic multiplier, are derived. Consequently, the corresponding circuit structures can be obtained, and the evaluation and energy recovery for ternary circuit can be realized by bootstrapped NMOS transistors and cross-memory structure. Based on the designed circuits, the four bits ternary adiabatic multiplier is further realized by adopting the ripple carry manner. The PSPICE simulation results indicate that the designed circuits have correct logic function and are characterized with distinctive low power consumption.     

A 32×32-b adiabatic register file with supply clock generator

A 32×32-b adiabatic register file with one read port and one write port is designed. A four-phase clock generator is also designed to provide supply clocks for adiabatic circuits. All the word line and bit line charge on the capacitive interconnections is recovered to save energy. Adiabatic circuits are based on efficient charge recovery logic (ECRL) and are integrated using 0.8 μm complimentary metal-oxide-semiconductor (CMOS) technology. Measurement results show that power consumption of the core is significantly reduced by a factor of up to 3.5 compared with a conventional circuit     

nMOS reversible energy recovery logic for ultra-low-energyapplications

We propose a new fully reversible adiabatic logic, nMOS reversible energy recovery logic (nRERL), which uses nMOS transistors only and a simpler 6-phase clocked power. Its area overhead and energy consumption are smaller, compared with the other fully adiabatic logics. We employed bootstrapped nMOS switches to simplify the nRERL circuits. With the simulation results for a full adder, we confirmed that the nRERL circuit consumed substantially less energy than the other adiabatic logic circuits at low-speed operation. We evaluated a test chip implemented with 0.8-μm CMOS technology, which included a chain of nRERL inverters integrated with a clocked power generator. The nRERL inverter chain of 2400 stages consumed the minimum energy at V_dd=3.5 V at 55 kHz, where the adiabatic and leakage losses are about equal, which is only 4.50% of the dissipated energy of its corresponding CMOS circuit at V_dd=0.9 V. In conclusion, nRERL is more suitable than the other adiabatic logic circuits for the applications that do not require high performance but low energy consumption     

Design of a DTCTGAL circuit and its application

By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic (DTCTGAL) circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25 μm CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.     

An efficient charge recovery logic circuit

Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows four to six times power reduction with a practical loading and operation frequency range. An inductor-based supply clock generation circuit is proposed. Circuits are designed using 1.0-μm CMOS technology with a reduced threshold voltage of 0.2 V     

QSERL: quasi-static energy recovery logic

A new quasi-static energy recovery logic family (QSERL) using the principle of adiabatic switching is proposed in this paper. Most of the previously proposed adiabatic logic styles are dynamic and require complex clocking schemes. The proposed QSERL uses two complementary sinusoidal supply clocks and resembles the behavior of static CMOS. Thus, switching activity is significantly lower than dynamic logic. In addition, QSERL circuits can be directly derived from static CMOS circuits. A high-efficiency clock generation circuitry, which generates two complementary sinusoidal clocks compatible to QSERL, is also presented in this paper. The adiabatic clock circuitry locks the frequency of clock signals, which makes it possible to integrate adiabatic modules into a VLSI system. We have designed an 8×8 carry-save multiplier using QSERL logic and two phase sinusoidal clocks. SPICE simulation shows that the QSERL multiplier can save 34% of energy over static CMOS multiplier at 100 MHz