Low-temperature mobility measurements on CMOS devices

The surface channel mobility of carriers in n- and p-MOS transistors fabricated in a CMOS process was accurately determined at low temperatures down to 5 K. The mobility was obtained by an accurate measurement of the inversion charge density using a split C-V technique and the conductance at low drain voltages. The split C-V technique was validated at all temperatures using a one-dimensional Poisson solver (MOSCAP) which was modified for low-temperature application. The mobility dependence on the perpendicular electric field for different substrate bias values appeared to have different temperature dependences for n- and p-channel devices. The electron mobility increased with a decrease in temperature at all gate voltages. On the other hand, the hole mobility exhibited a different temperature behavior depending upon whether the gate voltage corresponded to strong inversion or was near threshold     

Design of a comprehensive process evaluation vehicle for development of small geometry CMOS process

The design of a comprehensive process evaluation vehicle for thorough evaluation of a small geometry CMOS process has been discussed in this paper. The process evaluation vehicle includes both parametric and functional test structures and is considered to be particularly useful for the development of a small geometry CMOS process.     

CMOS器件抗静电措施的研究

由于CMOS器件静电损伤90%是延迟失效,对整机应用的可靠性影响太大,因而有必要对CMOS器件进行抗静电措施。本文描述了CMOS器件受静电损伤的机理,从而对设计人员提出了几种在线路设计中如何抗静电,以保护CMOS器件不受损伤。     

Effects of high field stresses on threshold voltage of CMOS transistors

In this paper, the threshold voltage instabilities of CMOS transistors under gate bias stress at high gate oxide electric fields have been investigated. It is shown that in presence of the negative gate bias stress threshold voltage of n-channel MOSTs decreases, while threshold voltage of p-channel MOSTs increases. These results are explained by positive fixed oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps. On the other hand, it is shown that in the presence of the positive gate bias stress threshold voltage of n-channel MOSTs decreases at the beginning as well, but after a certain time period starts to increase, while threshold voltage of p-channel MOSTs continuously increases. The initial threshold voltage behaviour is explained by positive fixed oxide charge increase as well; however, in this case it is caused by the electron tunneling from oxide electron traps into oxide conduction band. The later threshold voltage increase of n-channel MOSTs is explained by surface state charge increase due to tunnel current flowing through the oxide.     

Analyzing hot-carrier effects on cold CMOS devices

The operation of discrete and integrated CMOS ring oscillators was evaluated over the temperature range 77-300 K. Gate delays typically decreased by a factor of two at 77 K. Hot-carrier effects were enhanced by low-temperature operation, and transistor transconductance degradation occurred at low temperatures, which did not occur at room temperature as measured in the forward and inverse transistor curves. In marked contrast to dc stressing, ac stressing caused very little circuit degradation at low temperatures. By modeling the low-temperature phenomena at the MOSFET source junction, both hot-electron and hot-hole carrier effects were analyzed.     

Characterization of CMOS devices for VLSI

CMOS bulk and SOS technologies are discussed for VLSI with emphasis on static and dynamic characteristics of two-input NAND gates. Optimum performance (minimum figure of merit FM = tpdPd) is obtained for a CMOS/SOS two-input NAND gate (FO = 2, CL= 22 fF) with an electrical channel length L = 0.75 µm, channel width W = 5.0 µm, and oxide thickness Xo= 450 Å with VDD= 3.0 V, to yield tpd= 400 ps and Pd= 250 µW (tpdPd= 100 fJ) at room temperature. Bulk technology performs within a factor of 2 of SOS for tpdand Pd. CMOS technologies offer subnanosecond propagation delays, similar to ECL bipolar, at the low submilliwatt power levels of CMOS. An analytical expression for tpddescribes the performance of two-input NAND gates in terms of device modeling and fabrication parameters. Such an expression provides a hierarchial modeling approach to characterize minicells for VLSI.     

The effect of field dependent mobility on the threshold voltage of a small geometry MOSFET

Threshold voltage calculations for small geometry MOSFET's typically assume a constant mobility. Calculations are performed with a two-dimensional computer model to determine the effect of field dependent mobility on the threshold voltage. The field dependent mobility is seen to decrease the threshold voltage as compared with the constant mobility case as the drain voltage is increased. For low to moderate drain voltages, this effect is not of significant magnitude to be of concern.     

CMOS micromachined cantilever-in-cantilever devices with magneticactuation

A novel magnetically actuated cantilever microactuator which produces a large angular deflection is described. The device is a nested cantilever structure for improved sensitivity, and is fabricated entirely using a standard CMOS process. The cantilever deflects bidirectionally, and has a static deflection of more than 2.5°. It has a response time of 25 μs and at resonance has a deflection of more than 25°     

Low temperature characterization of silicon CMOS devices

A brief review of the main physical results concerning the low temperature characterization of Si CMOS devices is presented. More specifically, the carrier mobility law, saturation velocity, short channel effects, impact ionization phenomenon, hot carrier effects and parasitic leakage current are discussed.     

CMOS mean field learning

Analogue CMOS circuits which implement contrastive Hebbian learning have been designed, fabricated, and tested. A 19 neuron, 342 synapse mean field network, or deterministic Boltzmann machine (4.16*2.76 mm/sup 2/ in 1.2 mu m CMOS) has been constructed based on these synaptic circuits. Very small learning step size may be employed in this chip, which is advantageous for reliable mean field learning.<>     

3D CMOS devices in recrystallized silicon

A 2 μm scale three-dimensional CMOS process has been developed which allows the fabrication of MOS devices in two independent active device layers. NMOS transistors have been fabricated in the substrate and CMOS devices, including inverters and ring oscillators, in a thin laser-recrystallized polysilicon layer. The processing parameters were determined carefully in order to obtain a monocrystalline top layer and to avoid any damage to the underlying devices already existing.     

Submicrometer CMOS devices in zone-melting-recrystallized SOI films

CMOS devices with effective channel lengths ranging from 0.7 to 4.0 µm have been fabricated in zone-melting-recrystallized (ZMR) silicon-on-insulator (SOI) films prepared by the graphite-strip-heater technique. Low-temperature processing was utilized to minimize dopant diffusion along subboundaries in the films. Both n- and p-channel devices have low leakage current (<0.1-pA/µm channel width) and good subthreshold characteristics. For ring oscillators with a transistor channel length of 0.8 µm, the propagation delay is 95 ps at a supply voltage of 5 V.     

Double-gate CMOS: symmetrical- versus asymmetrical-gate devices

Numerical device-simulation results, supplemented by analytical characterizations, are presented to argue that asymmetrical double-gate (DG) CMOS, utilizing n⁺ and p⁺ polysilicon gates, can be superior to symmetrical-gate counterparts for several reasons, only one of which is its previously noted threshold-voltage control. The most noteworthy result is that asymmetrical DG MOSFETs, optimally designed with only one predominant channel, yield comparable, and even higher drive currents at low supply voltages. The simulations further give good physical insight pertaining to the design of DG devices with channel lengths of 50 nm and less     

Improved floating-gate devices using standard CMOS technology

A standard 2-μm, double-polysilicon, CMOS technology has been used to fabricate a floating-gate MOSFET. The 12-μm×17-μm device is electrically programmed using hot-electron injection and electrically erased using Fowler-Nordheim tunneling. Both operations can be performed with voltages lower than the junction breakdown voltage of the process, allowing high integration density and improved reliability. Programming times of hundreds of microseconds and erase times of tends of milliseconds are reported, both for a ΔV_t of 3 V. The programming time is about five orders of magnitude shorter than that of previously reported devices in a similar technology. The device is suitable for both analog and digital applications     

[110]-surface strained-SOI CMOS devices

We have newly developed [110]-surface strained-silicon-on-insulator (SOI) n- and p-MOSFETs on [110]-surface relaxed-SiGe-on-insulator substrates with the Ge content of 25%, fabricated by applying the Ge condensation technique to SiGe layers grown on [110]-surface SOI wafers. We have demonstrated that the electron and the hole mobility enhancement of [110]-surface strained-SOI devices amounts to 23% and 50%, respectively, against the mobilities of [110]-surface unstrained MOSFETs. As a result, the electron and the hole mobility ratios of [110]-surface strained-SOI MOSFETs to the universal mobility of (100)-surface bulk-MOSFETs increase up to 81% and 203%, respectively. Therefore, the current drive imbalance between n- and p-MOS can be reduced. Moreover, both the electron and the hole mobilities of the [110]-surface strained-SOIs strongly depend on the drain current flow direction, which is qualitatively explained by the anisotropic effective mass characteristics of the carriers on a [110]-surface Si. As a result, the [110]-surface strained-SOI technology with optimization of the current flow directions of n- and p-MOS is promising for realizing higher speed scaled CMOS.     

Precise characterization of long-distance mismatch of CMOS devices

A new test structure is presented for the characterization of long-distance mismatch of complimentary metal-oxide-semiconductor (CMOS) devices. A single circuit is used to characterize both transistors and resistors. High resolution is achieved by applying a four-terminal method with regulated reference potential to compensate for parasitic resistance effects. Measured data are presented for 0.5-, 0.35-, and 0.25-μm CMOS processes to demonstrate the performance of this approach. In particular, the long distance matching behavior is compared to that of neighboring devices. Examples for linear and nonlinear distance dependencies are shown. The long-distance mismatch has to be taken into account in circuit designs with short channel transistors and with narrow resistors     

CMOS为移动通信设备设置影像标准

CMOS传感器具有许多CCD传感器无法比拟的优点,比如更快的帧速率,更少的元件数目,更低的系统成本和更低的耗电量.本文将与您一起探讨CMOS图像传感器将如何改变移动通信设备.     

The characteristics of CMOS devices in oxygen-implantedsilicon-on-insulator structures

The characteristics of CMOS devices fabricated in oxygen-implanted silicon-on-insulator (SOI) substrates with different oxygen doses are studied. The results show that transistor junction leakage currents are improved by orders of magnitude when the oxygen dose is decreased from 2.25×10¹⁸ cm^-2 to 1.4×10¹⁸ cm^-2 . The floating-body effect, i.e. transistor turn-on at lower gate voltage with dramatic improvement in subthreshold slope when the drain voltage is increased, is enhanced by the reduction in leakage current and hence the oxygen dose. In SOI substrates implanted with 1.4×10¹⁷ cm^-2 oxygen dose and annealed at 1150°C, back-channel mobilities are decreased by several orders of magnitude compared to the mobilities in the precipitate-free silicon film. These device characteristics are correlated with the microstructure at the silicon-buried-oxide interface, which is controlled by oxygen implantation and post-oxygen-implantation anneal     

Digital characteristics of CMOS devices at cryogenic temperatures

The results of measurements of the digital characteristics of CMOS devices as a function of temperature between 77 and 300 K and of supply voltage between 3 and 20 V are presented. Using a fixed supply of 5 V, the low noise margin decreased from 2.54 to 2.11 V, but the high noise margin increased from 2.18 to 2.40 V as the temperature was increased from 77 to 300 K. On lowering the temperature from 300 to 77 K, both V_II and V_IH increased and the transition between these input logic voltages became more abrupt. These and other digital characteristics including noise immunity. V _H-V_I, and V_IH-V _II all showed a smooth monotonic improvement as the temperature decreased. These results can be qualitatively explained due to the increase in the absolute threshold voltages of the NMOS and PMOS transistors and to the decrease in the β_N/β_P ratio as the temperature is lowered     

Operation of SOI CMOS devices at liquid-nitrogen temperature

Liquid-nitrogen-temperature (LNT) operation of silicon-on-insulator (SOI) CMOS devices has been investigated experimentally. The maximum carrier mobilities in these devices increase by factors from 1.25 to 4.5 between room temperature and LNT. At LNT, the increase in depletion-layer width and the resulting threshold-voltage increase are limited by the silicon film thickness. For SOI devices with a body contact, the series resistance between channel and body contact increases at lower temperature, resulting in a current kink in saturation I-V characteristics