Lithography with high depth of focus by an ion projection system

Ion projection lithography is developed to generate structures with minimum feature sizes in the 100-nm range with a high pixel transfer rate. The high depth of focus (DOF) resulting from the telecentric beam path concept is also noteworthy. A silicon wafer exhibiting 200-μm-deep cavities, which are fabricated by anisotropic etching, is patterned with a grating of 0.6 μm periodicity running with identical spacings from the bottom to the top. SiO₂ serves as an inorganic ion sensitive resist. Exposed to 73 keV helium ions, SiO₂ shows an enhanced etching rate in hydrofluoric acid, the structure developing agent. The patterning techniques considered are promising for the fabrication of two-dimensional reflecting mirrors or sensoric elements distributed on spherical surfaces     

Silicon micromachining using in situ DC microplasmas

This paper reports on the generation of spatially confined plasmas and their application to silicon etching. The etching is performed using SF₆ gas and dc power applied between thin-film electrodes patterned on the silicon wafer to be etched. The electrodes also serve as a mask for the etching. The typical operating pressure and power density are in the range of 1-20 Torr and 1-10 W/cm², respectively. The plasma confinement can be varied from <100 μm to >1 cm by varying the electrode area, operating pressure, and power. High power densities can be achieved at moderate currents because the electrode areas are small. Etch rates of 4-17 μm/min., which enable through-wafer etching and varying degrees of anisotropy, have been achieved. The etch rate increases with power density, whereas the etch rate per unit power density increases with operating pressure. Scaling effects are explored for varying sized mask openings. Plasma resistance measurements and electric field modeling are used to provide an initial assessment of the microplasmas     

Plasma planarization for sensor applications

Filling trenches in silicon using phosphosilicate glass (PSG) provides many possibilities for novel device structures for sensors and actuators. This paper describes a plasma planarization technique that provides fully planarized PSG filled silicon trenches for sensor applications. The technique consists of planarizing the substrate using two photoresist layers and plasma etching-back. The lower resist layer is the AZ5214 image reversal resist, which is patterned and then thermally cured. The upper resist layer is a global HPR204 coating. The plasma etching-back is carried out using CHF₃/C₂F ₆ gas mixture with an O₂ addition. It is shown that by using the image reversal photoresist approach, fully planarized surface coating can be obtained without resorting to an additional mask. By adding 25 sccm (14%) O₂ into the 137 sccm CHF₃+18 sccm C₂F₆ gas mixture, the etch rates for the photoresist and PSG can be matched. Process optimization for the two layer resist coating and plasma etching is discussed     

Cryogenic Etching of Silicon: An Alternative Method for Fabrication of Vertical Microcantilever Master Molds

This paper examines the use of deep reactive ion etching of silicon with fluorine high-density plasmas at cryogenic temperatures to produce silicon master molds for vertical microcantilever arrays used for controlling substrate stiffness for culturing living cells. The resultant profiles achieved depend on the rate of deposition and etching of an $hbox{SiO}_{x}hbox{F}_{y}$ polymer, which serves as a passivation layer on the sidewalls of the etched structures in relation to areas that have not been passivated with the polymer. We look at how optimal tuning of two parameters, the $ hbox{O}_{2}$ flow rate and the capacitively coupled plasma power, determine the etch profile. All other pertinent parameters are kept constant. We examine the etch profiles produced using electron-beam resist as the main etch mask, with holes having diameters of 750 nm, 1 $muhbox{m}$ , and 2 $muhbox{m}$. $hfill$[2008-0317]      

Towards a versatile DRIE: silicon pit structures combined with electrochemical etch stop

A novel approach for fabricating low-pitch arrays of silicon membranes on standard CMOS wafers by combining deep-reactive ion etching (DRIE) and electrochemical etching (ECE) techniques is presented. These techniques have been used to fabricate membrane-based sensors and sensor arrays featuring different membrane sizes on a single wafer with a well defined etch stop. The described procedure is particularly useful in cases when the usage of SOI wafers is not an option. The combination of a grid-like mask pattern featuring uniform-size etch openings for the DRIE process with a reliable ECE technique allowed to fabricate silicon membranes with sizes ranging from 0.01 mm/sup 2/ to 2.2 mm/sup 2/. The development of this new method has been motivated by the need to design a compact n-well-based calorimetric sensor array, where the use of a standard ECE technique would have significantly increased the overall size of the device.     

Deep sub micron high aspect ratio polymer structures produced by hard X-ray lithography

Microfabrication using X-ray lithography is a well established process in many laboratories worldwide. Radiation spectra, mask technology and process conditions are optimized for patterning resist thicknesses of several hundred micrometers with lateral dimensions of a few microns. This article provides first results as to how far these technologies can be extended to form structures with sub-micrometer lateral dimensions in resist layers of a few micrometers thickness. Available equipment and processes of the 2.5 GeV electron storage ring ANKA and the process technology of the Institut für Mikrostrukturtechnik (IMT) in Karlsruhe, Germany, have been applied. An X-ray mask with a 2.7 m Ti-membrane and 20 m thick Au-absorbers is used to expose 1.6 m PMMA resist on silicon wafers. As the smallest features on the mask are 2 m, a double exposure with an intermediate deliberate relative movement between mask and resist generated sub-micron resist test structures. Smallest feature sizes are between 300 and 400 nm. They are not yet limited by diffraction, but by different process conditions that lead to adhesion loss, resist cracking and surface rounding. It has been shown that an intermediate layer of 1.2 m thick polyimide between resist and substrate significantly enhances adhesion and reduces resist cracking. Reducing the beam power impinging onto the sample from typically 21 to 0.4 W leads to a 50% reduction of the surface rounding at the top of the microstructures. To demonstrate the capability to pattern thicker resist layers, first samples with an increased resist thickness of 4.1 m and an aspect ratio of up to 8 were processed. Finally, a metal mesh with 2 m thick Au-absorbers and 900 nm hexagonal holes was applied to pattern showpieces of sub micron features using a reduced electron energy of 1.3 GeV.The high resolution metal mesh was provided by R. Fettig of IMT.     

Simulation and fabrication of piezoresistive membrane type MEMS strain sensors

Two piezoresistive (n-polysilicon) strain sensors on a thin Si₃N₄/SiO₂ membrane with improved sensitivity were successfully fabricated by using MEMS technology. The primary difference between the two designs was the number of strips of the polysilicon patterns. For each design, a doped n-polysilicon sensing element was patterned over a thin 3 μm Si₃N₄/SiO₂ membrane. A 1000×1000 μm² window in the silicon wafer was etched to free the thin membrane from the silicon wafer. The intent of this design was to fabricate a flexible MEMS strain sensor similar in function to a commercial metal foil strain gage. A finite element model of this geometry indicates that strains in the membrane will be higher than strains in the surrounding silicon. The values of nominal resistance of the single strip sensor and the multi-strip sensor were 4.6 and 8.6 kΩ, respectively. To evaluate thermal stability and sensing characteristics, the temperature coefficient of resistance [TCR=(ΔR/R₀)/ΔT] and the gage factor [GF=(ΔR/R₀)/] for each design were evaluated. The sensors were heated on a hot plate to measure the TCR. The sensors were embedded in a vinyl ester epoxy plate to determine the sensor sensitivity. The TCR was 7.5×10⁻⁴ and 9.5×10⁻⁴/°C for the single strip and the multi-strip pattern sensors. The gage factor was as high as 15 (bending) and 13 (tension) for the single strip sensor, and 4 (bending) and 21 (tension) for the multi-strip sensor. The sensitivity of these MEMS sensors is much higher than the sensitivity of commercial metal foil strain gages and strain gage alloys.     

Millimeter-scale actuator with fiber-optic roller bearings

A technique combining semiconductor processing and fiber-optic technology has been developed to micromachine a 1-cm² silicon die that rolls on two wheels above a flat substrate. Each wheel consists of a glass capillary surrounding a fixed solid glass fiber axle. A 100-silicon die is anisotropically etched to create two variable width v-grooves. Each v-groove has a wide center section and two narrow ends, which is schematically illustrated as -==-. The capillary is free to rotate about the axle in the wide v-groove section while the axle is anodically bonded into the narrow v-groove ends. The gap between the die and the substrate is determined by the narrow v-groove width, fiber diameter, and capillary wall thickness. Several rolling die have been fabricated with 210-120 μm gaps. The coefficient of static friction (μ_S) has been investigated on several substrates as a function of the load on the die. Values for μ_S are compared to an unetched die with a silicon nitride coating. With loads ranging from 0-10 grams, the wheels reduce μ_S by more than 50% on borosilicate glass     

Metallic thin-film thermocouple for thermoelectric microgenerators

A new metallic thin-film thermocouple orientated towards thermoelectric microgenerators has been developed. It consists of a 3 μm thick NiCr/SiO₂/Sb multilayer structure sputter deposited onto a thermally oxidized silicon substrate. A relative Seebeck coefficient of _ab = 76 μV K⁻¹ and an optimal figure of merit of z_ab = 0.08 × 10⁻³ K⁻¹ have been measured for this material combination. Both parameters are very close to the theoretical values.     

Released Si microstructures fabricated by deep etching and shallowdiffusion

A novel etch-diffusion process is developed for fabricating high-aspect-ratio Si structures for microsensors. This is accomplished by first dry etching narrow gap Si microstructures using an electron cyclotron resonance (ECR) source, followed by a shallow B diffusion to fully convert the etched microstructures to p⁺⁺ layer. Microstructures up to 40 μm deep with 2-μm-wide gaps were etched with a Cl₂ plasma generated using the ECR source. Vertical profile and smooth morphology were obtained at low pressure. A shallow B diffusion at 1175°C for 5.5 h. was then carried out to convert the 40-μm-thick resonant elements to p⁺⁺ layer. A second dry etching step was used to remove the thin p⁺⁺ layer around the bottom of the resonant elements, followed by bonding to glass and selective wet etch. Released high-aspect-ratio Si microsensors with thicknesses of 35 μm have been demonstrated. At atmospheric pressure, only 5 V_dc driving voltage is needed for 2.5 μm vibration amplitude, which is less than the 10 V_dc required to drive 12-μm-thick resonators fabricated by conventional dissolved wafer process     

Fabrication of ultrathin p++ silicon microstructuresusing ion implantation and boron etch-stop

This paper discusses the fabrication of submicron p⁺⁺ silicon microstructures for a number of MEMS applications using boron ion implantation, rapid thermal annealing, and boron etch-stop. To form these thin structures, the silicon is implanted with boron at an energy of 40 keV and doses of 5×10¹⁵ cm^-2 and 7×10¹⁵ cm^-2, which produce a peak concentration of more than 10²⁰ cm^-3, sufficient for achieving an effective etch-stop in ethylene diamine pyrocathecol. The thickness of the p⁺⁺ layer varies from 0.2 to 0.3 μm depending on the annealing time and temperature. SUPREM simulation has been used to determine optimum implantation and annealing conditions. A number of microstructures, including thin silicon diaphragms as large as 2 mm on a side and 0.2 μm thick, hot wire anemometers with a temperature coefficient of resistance of ~1600 ppm/°C, and piezoresistive sound detectors, have been fabricated with high reproducibility, uniformity, and yield     

Development of Microfabricated Cylindrical Ion Trap Mass Spectrometer Arrays

A novel approach, in which microelectromechanical systems (MEMS) technology is used for constructing miniature cylindrical ion trap (CIT) mass spectrometer (MS) arrays in silicon (Si), is described. MEMS processes were used to fabricate precise CIT geometries in a stack of Si, SiO₂, and Si₃N₄. These geometries were then selectively coated with conductive (Cr/Au) layers to obtain a functional CIT array with individual CIT radii (r₀) of 360 mum, half-thickness (z₀) of 351 mum, and aperture size (r_H) of 162 mum. Each trap of a 5 times 5 CIT array was operated in the mass selective instability mode to analyze trichloroethylene and perfluorotributylamine at a pressure of 10^-5 torr. Mass spectra from individual CITs in the array were obtained using a rasterable electron beam for internal ionization. Investigation of the operation of individual CITs in the array is a critical step toward the understanding of the overall functioning of MS arrays.     

Vertical Mirror Fabrication Combining KOH Etch and DRIE of (110) Silicon

This paper presents fabrication of MEMS-actuated optical-quality vertical mirrors as the key active optical components in a silicon optical bench (SOB) technology. The fabrication process is based on a combination of potassium hydroxide (KOH) etch and deep reactive ion etching (DRIE) of (110) SOI wafers. The process starts by creating optical-quality vertical surfaces by KOH etch, followed by an oxidation step to protect them. The patterned wafer is then etched by DRIE to define actuators. The process is designed to allow the KOH etch and DRIE to be independently optimized without compromising either while at the same time meeting the challenge of lithography on high-aspect-ratio structures. Three variations of the fabrication process are demonstrated, two that use double masking layers and one that uses a silicon masking layer. We demonstrate in-plane scanners and fast translational vertical mirrors fabricated using these processes. In addition, we propose extensions of the fabrication process to account for DRIE aspect-ratio limitations. Mask layouts of key SOB building blocks, including vertical mirrors, beam splitters, and parallel-plate actuators, are also presented.$hfill$ [2008-0146]      

A new pre-etching pattern to determine 〈110〉 crystallographic orientation on both (100) and (110) silicon wafers

Since the etching rate of anisotropic wet etching of silicon is highly orientation-dependent, it is important to determinate the crystallographic orientation before etching. In this paper, a new mask pattern based on the pre-etching process is designed to find out the 110 crystal orientation on both (100) and (110) silicon wafers observably and to align the subsequent masks more easily and conveniently. Because of a compensation of the quantization error due to the limitated scanning resolution of a mask generator and an optimum design, a pre-etching mask pattern with a resolution of 0.00625° and a span angle of ±2° is achieved with a consumption area of 560 × 14,472 m². To evaluate the precision of the misorientation angle determined by the pre-etching process based on the proposed pattern, both (100) and (110) wafers with 60 pre-etching patterns on each of them were etched. After statistic analysis, the precision of ±0.0467° for (100) wafers and ±0.025° for (110) wafers are achieved in our experiments which suggest the precision of determination of the crystallographic misorientation by the pre-etching process may be limited even though the resolution of the pre-etching mask pattern is high.We would like to thank the National Science Council of the Republic of China for financially supporting this research under contract No. NSC882218E009014.     

A high-Tc superconductor bolometer on a silicon nitridemembrane

In this paper, we describe the design, fabrication, and performance of a high-T_c GdBa₂Cu₃O_7-δ superconductor bolometer positioned on a 2× 2-mm² 1-μm-thick silicon nitride membrane. The bolometer structure has an effective area of 0.64 mm² and was grown on a specially developed silicon-on-nitride (SON) layer. This layer was made by direct bonding of silicon nitride to silicon after chemical mechanical polishing. The operation temperature of the bolometer is 85 K. A thermal conductance G=3.3·10^-5 W/K with a time constant of 27 ms has been achieved. The electrical noise equivalent power (NEP) at 5 Hz is 3.7·10^-2 WHz^-1/2, which is very close to the theoretical phonon noise limit of 3.6·10^-12 WHz ^-1/2, meaning that the excess noise of the superconducting film is very low. This bolometer is comparable to other bolometers with respect to high electrical performance. Our investigations are now aimed at decreasing the NEP for 84-μm radiation by further reduction of G and adding an absorption layer to the detector. This bolometer is intended to be used as a detector in a Fabry-Perot (FP)-based satellite instrument designed for remote sensing of atmospheric hydroxyl     

A merged process for thick single-crystal Si resonators and BiCMOScircuitry

A simple process has been developed which combines thick single-crystal Si micromechanical devices with a bipolar complimentary metal-oxide-semiconductor (BiCMOS) integrated circuit process. This merged process allows the integration of Si mechanical resonators as thick as 11 μm with any integrated circuit process with the addition of only a single masking step. The process does not require the use of Si on insulator wafers or any type of wafer bonding. The Si resonators were etched in an inductively coupled plasma source which allowed deep trenches to be fabricated with high aspect ratios and smooth sidewall surfaces. Clamped-clamped beam Si resonators that were 500 μm long, 5 μm wide, and 11 μm thick have been fabricated and tested. A typical resonator had a resonance frequency of 28.9 kHz and a maximum amplitude of vibration at resonance of 4.6 μm in air. The average measured resonance frequency across a 4-in-diameter Si wafer was within 0.5% of that predicted by theory. Working NMOS transistors were fabricated and tested on the same chip as the resonator with measured threshold voltages of 0.6 V and an output conductance of 2.0×10 ^-5 Ω^-1 for a gate voltage of 4 V     

Comparative study of spin coated and sputtered PMMA as an etch mask material for silicon micromachining

SiO₂ and Si₃N₄, are usually used to mask the selected portions during etching of silicon in anisotropic etchants like KOH but polymers are expected to be very good alternative to SiO₂ and Si₃N₄ as masking materials for MEMS applications. An adherent spin coated PMMA layer is reported to work as a mask material. It is a low temperature process, cheaper and films can be easily deposited and removed. One of the problems in its use is its adhesion to the substrate. Our previous experience in the field made us feel that sputtered PMMA will act as better mask because of its better adhesion to silicon. In the present article, a comparative study of spin coated PMMA with sputtered PMMA as an etch mask for silicon micromachining is reported. Structural and adhesive characteristics of the films are determined and compared with those available in the literature. These films deposited on silicon wafer were exposed to anisotropic etchant, KOH, to estimate the masking behavior. The maximum masking time of 32 min in 20 wt.% KOH at 80 °C was obtained for spin coated PMMA samples, which were prebaked at 90 °C. Masking time of sputter deposited PMMA films was found to be 300 min under similar conditions such as 20 wt.% KOH at 80 °C. This masking time is sufficient for fabrication of various MEMS structures, thus indicating candidature of sputtered PMMA as masking material. Various properties of the films are discussed and compared with the ones obtained through literature.     

Low temperature wafer direct bonding

A pronounced increase of interface energy of room temperature bonded hydrophilic Si/Si, Si/SiO₂, and SiO₂/SiO ₂ wafers after storage in air at room temperature, 150°C for 10-400 h has been observed. The increased number of OH groups due to a reaction between water and the strained oxide and/or silicon at the interface at temperatures below 110°C and the formation of stronger siloxane bonds above 110°C appear to be the main mechanisms responsible for the increase in the interface energy. After prolonged storage, interface bubbles are detectable by an infrared camera at the Si/Si bonding seam. Desorbed hydrocarbons as well as hydrogen generated by a reaction of water with silicon appear to be the major contents in the bubbles. Design guidelines for low temperature wafer direct bonding technology are proposed     

NOx sensing properties of In2O3 nanoparticles prepared by metal organic chemical vapor deposition

In₂O₃ nanoparticles were deposited by low-temperature metal organic chemical vapor deposition. The response of 10-nm thick In₂O₃ particle containing layers to NO_x and O₂ gases is investigated. The lowest detectable NO_x concentration is 200 ppb and the sensor performance is strongly dependent on the gas partial pressure as well as on the operating temperature. The sensor response towards 200 ppm of NO_x is found to be above 10⁴. Furthermore, the cross-sensitivity against O₂ is very low, demonstrating that the In₂O₃ nanoparticles are very suitable for the selective NO_x detection.     

Titania NOx sensors for exhaust monitoring

Oxide semiconductors have been examined to develop NO_x sensors for exhaust monitoring. Titania doped with trivalent elements, such as Al³⁺, Sc³⁺, Ga³⁺ or In³⁺, has a good sensitivity and selectivity to NO between 450 and 550 °C, and shows rapid response. A sensor probe for monitoring exhaust NO_x has been fabricated. Many kinds of interference gases, such as C₃H₆, CO and SO₂, have been found to have only a slight influence on the sensor response to NO. The influence of O₂ and H₂O is also negligible, except for the cases of 0% H₂O and fuel-rich conditions. In accordance with these results, the sensor probe operates satisfactority in the exhaust gas of various combustion conditions without interference from the various kinds of gas species in the exhaust gases.