共查询到20条相似文献,搜索用时 15 毫秒
1.
2.
Yamaguchi Y. Nishimura T. Akasaka Y. Fujibayashi K. 《Electron Devices, IEEE Transactions on》1992,39(5):1179-1183
The salicide technology using rapid thermal annealing was applied to MOSFETs on thin-film SOI. Since the SOI film was limited to a thickness of less than 100 nm, the silicidation reaction between Ti and Si atoms on the SOI surface exhibited new features that depended on the initial thickness of the deposited Ti. There was an optimum thickness of as-deposited Ti on silicidation due to the restricted thickness of the Si layer. Beyond the optimum point, the region adjacent to the silicided Si layer works as a Si source to assure stoichiometric TiSi2. The subthreshold slopes and carrier mobilities were not changed by the salicide process. Junction leakage characteristics were slightly degraded; however, the change was small enough for device application. The influence on AC characteristics was well demonstrated for a high-speed CMOS ring oscillator with a gate length of 0.7 μm. The minimum delay time/stage was 46 ps/stage at 5 V. This gives 1.8 times higher speed operation than the controlled bulk CMOS ring oscillators with the same design rule 相似文献
3.
An insightful study of the subthreshold characteristics of deep-submicrometer fully depleted SOI MOSFET's, based on two-dimensional numerical (PISCES) device simulations, shows that the gate swing and off-state current are governed by gate bias-dependent source/drain charge sharing, which controls back-channel as well as front-channel conduction. The insight from this study guides the development of a physical, two-dimensional analytic model for the subthreshold current and charge, which is linked to our strong-inversion formalism in SOISPICE for circuit simulation. The model is verified by PISCES simulations of scaled devices. The utility of the model in SOISPICE is demonstrated by using it to define a viable design for deep-submicrometer fully depleted SOI CMOS technology based on simulated speed and static power in low-voltage digital circuits 相似文献
4.
5.
《Electron Device Letters, IEEE》1987,8(9):410-412
The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion. This original method of transistor operation offers excellent device performance, in particular great increases in subthreshold slope, transconductance, and drain current. A simulation program and experiments on SIMOX structures are used to study the new device. 相似文献
6.
7.
8.
Modeling the effect of back gate bias on the subthreshold behavior of a SiGe-channel SOI PMOS device
This paper reports on a simulation study on the back gate bias effect on the subthreshold behavior of a SiGe-channel SOI PMOS device using a device simulator. With a SiGe channel, the SOI PMOS device shows a smaller back gate bias effect as compared to the one without it. 相似文献
9.
The effect of back-gate bias on the subthreshold behavior and the switching performance in an ultrathin SOI CMOS inverter operating at 300 and 77 K is investigated using a low-temperature device simulator. The simulation results show that the nonzero back-gate bias induces hole pile-up at the back interface, which causes opposite effects on the NMOS and PMOS subthreshold characteristics at 300 and 77 K. Throughout the transient process, at 300 K, for V B=-5 V operation, hole pile-up at the back interface always exists in the NMOS device. Compared to the zero back-gate bias case, at V B=-5 V, the risetime of the SOI CMOS inverter is over 5% shorter at 77 and 300 K and the falltime is 5% longer. Prepinch-off velocity saturation in the NMOS device dominates the pull-down transient as a result of the smaller electron critical electric field 相似文献
10.
Modifications of the Ortiz-Conde et al., model which take into account either apparent or physical bandgap narrowing have been presented. The influence of high doping effects is investigated by means of a comparison of the modified models with their original, version for various device parameters. It is shown that the inclusion of bandgap narrowing is essential for accurate simulation of I-V characteristics of a SOI MOSFET in the subthreshold and near-threshold regions. A new analytical model with bandgap narrowing has been derived for the subthreshold region 相似文献
11.
Ali A. Orouji 《Microelectronic Engineering》2006,83(3):409-414
In this paper, we present the unique features exhibited by a novel double gate MOSFET in which the front gate consists of two side gates as an extension of the source/drain. The asymmetrical side gates are used to induce extremely shallow source/drain regions on either side of the main gate. Using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing and the hot carrier effect. Based on our simulation results, we demonstrate that the proposed symmetrical double gate SOI MOSFET with asymmetrical side gates for the induced source/drain is far superior in terms of controlling the short-channel effects when compared to the conventional symmetrical double gate SOI MOSFET. We show that when the side gate length is equal to the main gate length, the device can be operated in an optimal condition in terms of threshold voltage roll-off and hot carrier effect. We further show that in the proposed structure the threshold voltage of the device is nearly independent of the side gate bias variation. 相似文献
12.
Matloubian M. Chen C.-E.D. Mao B.-Y. Sundaresan R. Pollack G.P. 《Electron Devices, IEEE Transactions on》1990,37(9):1985-1994
n-channel SOI MOSFETs with floating bodies show a threshold voltage shift and an improvement in subthreshold slope at high drain biases. The magnitude of this effect depends on the device parameters and the starting SOI substrate. A simple device model is presented that explains the observed characteristics to be due to MOS back-bias effects resulting from the positively charged floating body. The improvement in the subthreshold slope is the outcome of positive feedback between the body potential and the transistor channel current 相似文献
13.
14.
Balestra F. Benachir M. Brini J. Ghibaudo G. 《Electron Devices, IEEE Transactions on》1990,37(11):2303-2311
Analytical models are proposed for thin- and ultra-thin film silicon-on-insulator (SOI) MOSFETs operating in weak or strong inversion. The models take into account all the device parameters. The cases of two and three interfaces with a silicon substrate are considered in the modeling and compared with one another. These models give the main electrical MOSFET parameters in ohmic operation (subthreshold swing and threshold voltage) for these structures. The basic approximation is the consideration of a linearly varying potential in the Si film, which has been inferred on the basis of numerical simulations. Various behaviors depending on the Si film and the buried insulator thickness as well as the interface charges, Si film doping, or substrate regime are simulated to assess the properties and the performances of SOI MOS transistors and to validate the analytical models 相似文献
15.
Xinnan Lin Chuguang Feng Shengdong Zhang Wai-Hung Ho Mansun Chan 《Solid-state electronics》2004,48(12):2315-2319
A simple process to fabricate double gate SOI MOSFET is proposed. The new device structure utilizes the bulk diffusion layer as the bottom gate. The active silicon film is formed by recrystallized amorphous silicon film using metal-induced-lateral-crystallization (MILC). While the active silicon film is not truly single crystal, the material and device characteristics show that the film is equivalent to single crystal SOI film with high defect density, like SOI wafers produced in early days. The fabricated double gate MOSFETs are characterized, which demonstrate excellent device characteristics with higher current drive and stronger immunity to short channel effects compared to the single gate devices. 相似文献
16.
Sung-Weon Kang Jong-Son Lyu Jin-Young Kang Sang-Won Kang Jin-Hyo Lee 《Electron Device Letters, IEEE》1995,16(6):236-238
Leakage current through the parasitic channel formed at the sidewall of the SOI active region has been investigated by measuring the subthreshold I-V characteristics. Partially depleted (PD, ~2500 Å) and fully depleted (FD, ~800 Å) SOI NMOS transistors of enhancement mode have been fabricated using the silicon direct bonding (SDB) technology. Isolation processes for the SOI devices were LOCOS, LOCOS with channel stop ion implantation or fully recessed trench (FRT). The electron concentration of the parasitic channel is calculated by the PISCES IIb simulation. As a result, leakage current of the FD mode SOI device with FRT isolation at the front and back gate biases of 0 V was reduced to ~pA and no hump was seen on the drain current curve 相似文献
17.
本文在分析薄膜全耗尽SOI器件特殊物理效应的基础上,建立了可细致处理饱和区工作特性的准二维电流模型。该模型包括了场效应载流子迁移率、速度饱和以及短沟道效应等物理效应,可以描述薄膜全耗尽SOI器件所特有的膜厚效应、正背栅耦合(背栅效应)等对器件特性的影响,并且保证了电流、电导及其导数在饱和点的连续性。将模型模拟计算结果与二维器件数值模拟结果进行了对比,在整个工作区域(不考虑载流子碰撞离化的情况下)二者吻合得很好。 相似文献
18.
Faynot O. Cristoloveanu S. Auberton-Herve A.J. Raynaud C. 《Electron Devices, IEEE Transactions on》1995,42(4):713-719
A systematic experimental investigation of the influence of the silicon film thickness on the properties of accumulation-mode SOI MOSFET's has been performed, and the relevant original results are presented. Interface coupling mechanisms and their effects on the major device parameters (threshold voltages, subthreshold swing, and transconductance) are analyzed. The feasibility of ultrathin accumulation-mode SIMOX MOSFET's for future submicrometer applications is demonstrated and discussed. Floating-body effects, which stand as critical aspects for SOI devices, are also investigated and the benefit of the silicon film thinning on the breakdown behavior of accumulation-mode devices is clearly established 相似文献
19.
Nishiguchi K. Fujiwara A. Ono Y. Inokawa H. Takahashi Y. 《Electron Device Letters, IEEE》2007,28(1):48-50
Low current leakage characteristics of a novel silicon-on-insulator (SOI) device are investigated in view of application to a gain-cell dynamic random access memory (DRAM). The device consists of a two-layered poly-Si gate. Since, in this device, the memory node is electrically formed by the gate in undoped SOI wire, no p-n junction is required. The retention is found to be dominated by the subthreshold leakage, which leads to long data retention. The device also achieved a fast (10 ns) writing time and its fabrication process is compatible with those of SOI MOSFETs. The present results, thus, strongly suggest a way of conducting a gain-cell DRAM to be embedded into logic circuits 相似文献
20.
Walker P.M. Mizuta H. Uno S. Furuta Y. Hasko D.G. 《Electron Devices, IEEE Transactions on》2004,51(2):212-219
A polycrystalline-silicon thin-film transistor (TFT), with a single grain boundary (GB) present in the channel, is simulated using two-dimensional numerical simulation, which includes a model of deep trap states at GBs. It is observed that the potential barrier resulting from a GB in the channel acts to suppress current flowing through the channel when the barrier height is greater than the thermal voltage. The conduction mechanism in the subthreshold regime is clarified. The turn-on characteristics of the device are controlled primarily by gate-induced grain barrier lowering as opposed to modulation of carriers in the channel by the gate voltage. In the negative bias region it is found that suppression of the off current is aided by the GB potential barrier. Scaling of the various geometrical parameters of the device are investigated. Improved subthreshold characteristics, compared to an equivalent silicon-on-insulator (SOI) structure, are found for aggressively scaled devices, due to the presence of a GB in the channel. 相似文献