Measurement of Fowler-Nordheim tunneling currents in MOS structures under charge trapping conditions

The Fowler-Nordheim (FN) tunneling of electrons into thermal SiO₂ at high levels of injection has been studied. A modified I–V measurement technique has been developed to correct for charge trapping phenomena, which are unavoidable under the high field and current conditions. It is shown that the results fit a universal FN type current-field dependence which is insensitive to oxide thickness and free of the commonly observed hysteresis phenomena.     

Fowler-Nordheim stress degradation in gate oxide: results fromgate-to-drain capacitance and charge pumping current

The buildup of positive oxide charge and interface trap charge, due to Fowler-Nordheim stress, is observed in the gate-drain overlap region of the MOSFET. Results from gate-to-drain capacitance and charge pumping current show a steady increase in positive charge near the anode interface. Interface trap generation becomes significant when injected electron fluence exceeds ~10¹⁴ cm^-2, and dominates net charge creation at higher fluence     

Gate oxide thickness dependence of edge charge trapping in NMOS transistors caused by charge injection under constant-current stress

This brief reports a study of charge injection-induced edge charge trapping in the gate oxide overlapping the drain extension which has an impact on the drain leakage current. The edge charge trapping is determined for the gate oxide thickness of 6.5, 3.9, and 2.0 nm by using a simple approach to analyze the change of the band-to-band tunneling current measured with a three-terminal gate-controlled-diode configuration. The edge charge trapping has a strong dependence on the gate oxide thickness, and it is different from the charge trapping in the oxide over the channel. A plausible explanation for both the oxide thickness dependence of the edge charge trapping and the difference between the edge charge trapping and the charge trapping over the channel is presented.     

Evolution of oxide charge trapping under bias temperature stressing

Transient oxide-charge trapping and detrapping, commonly regarded as a parasitic effect in the interpretation of dynamic bias-temperature stress (BTS) data, may play an important role on the long term reliability of the gate oxide as revealed by recent studies on the SiON and HfO₂ gate dielectrics. Specifically, it is found that transient charge trapping (one which relaxes upon removal of the applied electrical stress) is transformed into more permanent trapped charge when the applied electrical cum thermal stress exceeds a certain threshold. Below the threshold, cyclical transient charge trapping and detrapping behavior is observed. The observations imply that the oxide structure may be modified by the applied stress, making it susceptible to permanent defect generation. In addition, it is found that when the transformation of hole trapping occurs under negative-bias temperature stress, a correlated increase of the gate current is always observed, which points to the transformation process being the origin for bulk oxide trap generation. However, when the transformation of electron trapping occurs under positive-bias temperature stress, an increase of the gate current is not always observed. From ab initio simulation, we show that an intrinsic oxide defect – the oxygen vacancy-interstitial (V_O − O_i) – could consistently explain the experimental observations. An interesting feature of the V_O − O_i defect is that it can exists in various metastable configurations with the interstitial oxygen O_i in different positions around the vacancy V_O, corresponding to different trap energy states in the oxide bandgap. This characteristic is able to account for the BTS induced generation of deep-level trapped charges as well as transformation of transient (or shallow) to permanent (or deep) charge trapping.     

Study of gate oxide leakage and charge trapping in ZMR and SIMOXSOI MOSFETs

Characterization of gate oxides grown on zone-melting-recrystallized (ZMR) and silicon-implanted-with-oxygen (SIMOX) films indicates oxide leakage and charge trapping to be several orders of magnitude greater than their bulk silicon counterparts. Electron trapping is the primary trapping mechanism for constant current injection in the gate oxides of these SOI (silicon-on-insulator) films. Similar type of traps are observed in ZMR and SIMOX oxides     

Assessment of oxide charge density and centroid from Fowler-Nordheim derivative characteristics in MOS structures after uniform gate stress

A new method for the extraction of the oxide charge density and distribution centroid based on the exploitation of the Fowler plot derivative characteristics is proposed. The comparison with the DiMaria method confirms the overall consistency of the new approach. The presence of negative charge within the oxide is shown to be responsible for an increase in the apparent Fowler barrier height after uniform gate stress.     

Circuit implications of gate oxide breakdown

A model for the oxide breakdown (BD) current–voltage (I–V) characteristics has been experimentally verified on CMOS inverters. The implications of oxide BD on the performance of various CMOS circuit elements are discussed. Examples are shown of cell stability and bitline differentials in static memory (SRAM), signal timing, and inverter chains.     

Influence of charge trapping on oxide scaling down

The aim of this work is the characterization, in terms of trapped charge and charge to breakdown, of the quality of an oxide with reduced thickness. A comparison between two evaluation methods, the widely used exponentially ramped current stress (ERCS) and the constant current stress (CCS), is established obtaining contradictory results. A measurement of the charge trapped in the oxide bulk is performed by sensing the modification of the Fowler–Nordheim barrier under constant current stress. Using this technique it is possible to correlate the charge trapping characteristics with the charge to breakdown and to explain the inconsistencies.     

Time dependent breakdown of ultrathin gate oxide

Time dependent dielectric breakdown (TDDB) of ultrathin gate oxide (<40 Å) was measured for a wide range of oxide fields (3.4<|E_ox|<10.3 MV/cm) at various temperatures (100⩽T⩽342°C). It was found that TDDB of ultrathin oxide follows the E model. It was also found that TDDB t₅₀ starts deviating from the 1/E model for fields below 7.2 MV/cm. Below 4.8 MV/cm, TDDB t₅₀ of intrinsic oxide increased above the value predicted by the E model obtained for fields >4.8 MV/cm. The TDDB activation energy for this type of gate oxide was found to have linear dependence on oxide field. In addition, we found that γ (the field acceleration parameter) decreases with increasing temperature. Furthermore, it was found that testing at high temperatures (up to 342°C) and low electric field values did not introduce new gate oxide failure mechanism. It is also shown that TDDB data obtained at very high temperature (342°C) and low fields can be used to generate TDDB model at lower temperatures and low fields. Our results (an enthalpy of activation of 1.98 eV and dipole moment of 12.3 eÅ) are in complete agreement with previous results by McPherson and Mogul. Additionally, it was found that TDDB is exponentially dependent on the gate voltage     

The nature of charge trapping responsible for thin-oxide breakdown under a dynamic field stress

The trapping of positive and negative charges in silicon dioxide was studied as a function of injection current density and pulse width during dynamic high-field/high-current stress. Trapping of negative charges in oxide under dynamic stress conditions was found to give an accumulated charge to breakdown (Qbd) that was independent of stressing current density if the total injected charge per pulse was kept constant. However, the trapping of positive charges increased significantly as current density was increased. Under dynamic stress with fixed current density, the trapping of negative charge in the oxide increased with increasing pulse width while the trapping of positive charge was independent of pulse width. The experimental data for dynamically stressed devices suggest a strong correlation between the breakdown of thin oxides and the amount of negative charge trapped in them.     

Influence of gate oxide breakdown on MOSFET device operation

The degradation of MOS transistor operation due to soft breakdown and thermal breakdown of the gate oxide was studied. Important transistor parameters were monitored during homogeneous stress at elevated temperature until a breakdown event occurred. In case of NMOSFETs the only noticeable signature of soft breakdown is an increase in off current due to enhanced gate induced drain leakage current (GIDL). A model is proposed and it is concluded that this effect only arises if the soft breakdown is located within the gate-to-drain overlap region. The influence of soft breakdown on PMOSFETs is discussed based on the model of enhanced GIDL for NMOSFETs. The degradation due to thermal breakdown of the gate oxide was investigated in detail. As a conclusion, a careful selection of device parameters is necessary in order to detect a device breakdown caused by thermal gate oxide breakdown.     

On physical models for gate oxide breakdown

Electrical breakdown of thin (32-nm) SiO2films subjected to constant-current stressing is studied. By studying the effects of reversing the polarity of the constant-current bias and the effects of thermal annealing on the charge-to-breakdown it is determined that electrical breakdown of SiO2is not caused by the widely-cited accumulation of trapped electrons. Rather it is caused by the buildup of positive charges near the cathode at localized areas. The positive charges are not mobile ions but exhibit many characteristics of trapped holes. We conclude that electrical breakdown in SiO2is caused by the accumulation of holes, generated by impact ionization in the oxide.     

Role of hole fluence in gate oxide breakdown

A simple model which links the primary hole and Fowler-Nordheim (FN) electron injections to oxide breakdown is established and the calculation based on this model is in good agreement with our experiments. When the sum of the active trap density D^pri due to primary hole injection and the active trap density Dⁿ due to FN electron injection reaches a critical value D_cri, the oxide breaks down. The hole is two orders of magnitude more effective than FN electron in causing breakdown. These new findings are imperative in predicting oxide reliability and device lifetime     

New insights in polarity-dependent oxide breakdown for ultrathin gate oxide

In this work, a quantitative analysis is applied to resolve the newly reported polarity-dependent charge-to-breakdown (Q/sub BD/) data from thick oxides of 6.8 nm down to ultrathin oxides of 1.9 nm. Three independent sets of Q/sub BD/ data, i.e., n/sup +/poly/NFET stressed under inversion and accumulation, and p/sup +/ poly/PFET under accumulation are carefully investigated. The Q/sub BD/ degradation observed for p-type anodes, either poly-Si or Si-substrate, can be nicely understood with the framework of maximum energy released by injected electrons. Thus, this work provides a universal and quantitative account for a variety of experimental observations in the time-to-breakdown (T/sub BD/) and Q/sub BD/ polarity-dependence of oxide breakdown.     

Effects of fluorine implants on induced charge components ingate-oxides under constant-current Fowler-Nordheim stress

Charge defects in MOS capacitors formed with fluorine-incorporated oxides are analyzed by Fowler-Nordheim (F-N) tunnelling injection stress. Like previous studies, fluorinated gate oxides prove to have better performance in aspects of overall flatband voltage shifts and interface trapped charge density. However, these advantages result from more complex combinations of effects. In this study, comparisons of induced charging components between fluorinated and control oxides expose complicated variations of trapped charge generation in both bulk and interface regions. A relationship is found between the amount of fluorine at/near the Si/SiO₂ interface and induced charges in the bulk     

Investigation of gate oxide breakdown in CMOS integrated circuits

Investigation of gate oxide breakdown in CMOS integrated circuits, aimed at establishing its dependence on substrate doping (type and level) and its acceleration by an electric field, has been performed in this paper. In order to do this, time-zero-dielectric-breakdown (ramp-voltage-stressed I-V) and time-dependent-dielectric-breakdown (constant-voltage-stressed I-t) tests were carried out and the gate oxide breakdown histograms and electric field acceleration factor were determined and discussed in detail.     

Impact of MOSFET gate oxide breakdown on digital circuit operationand reliability

The influence of FET gate oxide breakdown on the performance of a ring oscillator circuit is studied using statistical tools, emission microscopy, and circuit analysis. It is demonstrated that many hard breakdowns can occur in this circuit without affecting its overall function. Time-to-breakdown data measured on individual FETs are shown to scale correctly to circuit level. SPICE simulations of the ring oscillator with the affected FET represented by an equivalent circuit confirm the measured influence of the breakdown on the circuit's frequency, the stand-by and the operating currents. It is concluded that if maintaining a digital circuit's logical functionality is the sufficient reliability criterion, a nonzero probability exists that the circuit will remain functional beyond the first gate oxide breakdown. Consequently, relaxation of the present reliability criterion in certain cases might be possible     

New positive charge trapping dynamics in SiO2 gate oxide, based on bulk impact ionization processes under Fowler–Nordheim stress

A new charge trapping dynamics is proposed to analyze theoretically the gate oxide degradation in metal oxide silicon structures under Fowler–Nordheim (F–N) stress (6–10 MV/cm) at a low injected electron fluence. Devices studied were MOS capacitors with 22-, 27-, and 33-nm-thick, thermally grown silicon dioxide (SiO₂) on (100) n-Si. Our model includes tunneling electron initiated band-to-band impact ionization and trap-to-band ionization, as the possible mechanisms for the generation of hole and positive charge in the bulk of the oxide, respectively. The results from our model are in good agreement with the experimental results of gate voltage shift with injected electron fluence under constant current stress. Based on the developed coupled dynamics, we have compared the degradation under F–N stress at a constant current and gate voltage.     

Monitoring trapped charge generation for gate oxide under stress[MOS capacitors]

A measurement method to extract the respective quantities and centroids of positive and negative trapped charges, i.e., Q_p and Q_n, generated by the negative current stress for gate oxides is proposed and demonstrated. The method is based on neutralization of and by a low positive current stress to differentiate the effects of Q_p and Q_n. From the extracted quantities and centroids of Q_p and Q_n of negatively stressed oxides, it was found that Q_p and Q_n are generated near the oxide/substrate interface and Q_p is initially much larger than Q_n. After the continuous stressing, Q_p saturates and moves closer to the interface, but Q_n keeps increasing and moves away from the interface, especially for those oxides after the post-poly anneal (PPA) treatment. Q_p is very unstable and easily neutralized, either by a small stress of opposite polarity or the same polarity. For the latter, Q_p is mainly dependent on the level of the final stressing field