The effect of high-K gate dielectrics on deep submicrometer CMOSdevice and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K_gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K_gate for different target subthreshold leakage currents has been identified     

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking

This paper presents a complete circuit-compatible compact model for single-walled carbon-nanotube field-effect transistors (CNFETs) as an extension to Part 1 of this two-part paper. For the first time, a universal circuit-compatible CNFET model including the practical device nonidealities is implemented with HSPICE. In addition to the nonidealities included in the companion paper, this paper includes the elastic scattering in the channel region, the resistive source/drain (S/D), the Schottky-barrier resistance, and the parasitic gate capacitances. More than one nanotube per device can be modeled. Compared to silicon technology, the CNFETs show much better device performance based on the intrinsic gate-delay metric (six times for nFET and 14 times for pFET) than the MOSFET device at the 32-nm node, even with device nonidealities. This large speed improvement is significantly degraded (by a factor of five to eight) by interconnect capacitance in a real circuit environment. We performed circuit-performance comparison with all the standard digital library cells between CMOS random logic and CNFET random logic with HSPICE simulation. Compared to CMOS circuits, the CNFET circuits with one to ten carbon nanotubes per device is about two to ten times faster, the energy consumption per cycle is about seven to two times lower, and the energy-delay product is about 15-20 times lower, considering the realistic layout pattern and the interconnect wiring capacitance.     

Carbon Nanotube Field-Effect Transistors for High-Performance Digital Circuits—Transient Analysis, Parasitics, and Scalability

Silicon-based CMOS is the dominant technology choice for high-performance digital circuits. While silicon technology continues to scale, researchers are investigating other novel materials, structures, and devices to introduce into future technology generations, if necessary, to extend Moore's law. Carbon nanotubes (CNTs) have been explored as a possibility due to their excellent carrier mobility. The authors studied and compared different carbon-nanotube-based field-effect transistors (CNFETs) including Schottky-barrier (SB) CNFETs, MOS CNFETs, and state-of-the-art Si MOSFETs systematically from a circuit/system design perspective. Parasitics play a major role in the performance of CNT-based circuits. The data in this paper show that CNFET design's performance is limited by the gate overlap capacitance and the quality of nanocontacts to these promising transistors. Transient analysis of high-performing single-tube SB CNFET transistors and circuits revealed that 1-1.5 nm is the optimum CNT diameter resulting in best power-performance tradeoff for high-speed digital applications. The authors determined optimal spacing and layout of CNT arrays, an architecture that is most likely required for driving capacitive loads and interconnects in digital applications. CNTs have an intrinsic capability to improve performance, but many serious technological and experimental challenges remain that require more research to harvest their potential     

Impact of High-k Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs

The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-effect transistors is studied over a wide range of dielectric permittivities k. It is observed that there is a decrease in the parasitic outer fringe capacitance C_of in addition to an increase in the internal fringe capacitance C_if with high-k dielectrics, which degrades the short-channel effects significantly. It is shown that fin width scaling is the most suitable approach to recover the degradation in the device performance due to high-k integration. Furthermore, from the circuit perspective, for the 32-nm technology generation, the presence of an optimum k for a given target subthreshold leakage current has been identified by various possible approaches such as fin width scaling, fin-doping adjustment, and gate work function engineering     

Modeling and optimization of fringe capacitance of nanoscale DGMOS devices

We analyze the impact of gate electrode thickness and gate underlap on the fringe capacitance of nanoscale double-gate MOS (DGMOS) transistors. We propose an analytical fringe capacitance model considering gate underlap and finite source/drain length. A comparison with the simulation results show that the model can accurately estimate the fringe capacitance of the device. We show that an optimum gate underlap can significantly reduce the fringe capacitance resulting in higher performance and lower power consumption. Also, the effects of process variation in gate underlap devices are discussed. Simulation results on a three-stage ring oscillator show that with optimum gate underlap 32% improvement in delay can be achieved.     

Effects of Parasitic Capacitance, External Resistance, and Local Stress on the RF Performance of the Transistors Fabricated by Standard 65-nm CMOS Technologies

Effects of parasitic capacitance, external resistance, and local stress on the radio-frequency (RF) performance of the transistors fabricated by 65-nm CMOS technology have been investigated. The effect of parasitic capacitance, particularly C_gb, becomes significant due to the reduced spacing between the gate and the substrate contact (SC) in proportion to scaling down. Current drivability (I_dsat) per unit width has been improved through introduction of mobility enhancement techniques. The influence of external resistance becomes more pronounced for large-dimensional RF transistors due to severe IR drop. Such improved current drivability and large external resistance is responsible for dc performance (g_m) degradation and, eventually, cutoff frequency (f_T) degradation. Local stress effects associated with silicon nitride capping layer and STI stress have been investigated. f_T is largely affected by local stress change, i.e., g_m degradation at minimal gate poly (GP) pitch and gate-to-active spacing, f_T is dominated by increased parasitic capacitance (C_gb) with increasing GP pitch and gate-to-active spacing. Above 10% improvement in f_T has been observed through layout optimization for C_gb reduction by increasing the transistor active-to-SC spacing.     

Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

In deep submicrometer MOSFETs the device performance is limited by the parasitic capacitance and resistance. Hence a circuit model is needed to treat these effects correctly. In this work, we have developed circuit models for the parasitic capacitances in conventional and high-K gate dielectric MOS transistors by taking into account the presence of source/drain contact plugs. The accuracy of the model is tested by comparing the modeled results with the results obtained from three-dimensional (3-D) Monte-Carlo simulations and two-dimensional (2-D) device simulations over a wide range of channel length and oxide thickness. The model is also used to study the dependence of parasitic capacitance on gate length, gate electrode thickness, gate oxide thickness, gate dielectric constant, and spacer width.     

AlGaN/GaN HEMT器件工艺的研究进展

首先论述了Al GaN/GaN高电子迁移率晶体管(HEMT)在微波大功率领域的应用优势和潜力;其次,介绍并分析了影响Al GaN/GaN HEMT性能的主要参数,分析表明要提高Al-GaN/GaN HEMT的频率和功率性能,需改善寄生电阻、电容、栅长和击穿电压等参数。然后,着重从材料结构和器件工艺的角度阐述了近年来Al GaN/GaN HEMT的研究进展,详细归纳了目前主要的材料生长和器件制作工艺,可以看出基本的工艺思路是尽量提高材料二维电子气的浓度和材料对二维电子气的限制能力的同时减小器件的寄生电容和电阻,增强栅极对沟道的控制能力。另外,根据具体情况调节栅长及沟道电场。最后,简要探讨了Al GaN/GaN HEMT还存在的问题以及面临的挑战。     

Variability and reliability analysis of CNFET technology: Impact of manufacturing imperfections

Carbon nanotube field-effect transistors (CNFETs) are promising candidates to substitute silicon transistors. Boasting extraordinary electronic properties, CNFETs exhibit characteristics rivaling those of state-of-the-art Si-based metal–oxide–semiconductor field-effect transistors (MOSFETs). However, as any technology that is in development, CNFET fabrication process still have some imperfections that results in carbon nanotube variations, which can have a severe impact on the devices’ performance and jeopardize their reliability (in this work the term reliability means time-zero failure due to manufacturing variations). This paper presents a study of the effects on transistors of the main CNFET manufacturing imperfections, including the presence of metallic carbon nanotubes (m-CNTs), imperfect m-CNT removal processes, chirality drift, CNT doping variations in the source/drain extension regions, and density fluctuations due to non-uniform inter-CNT spacing.     

Reduction of parasitic capacitance in vertical MOSFETs by spacer local oxidation

Application of double gate or surround-gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their layout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple self-aligned process has been developed to reduce the parasitic overlap capacitance in vertical MOSFETs using nitride spacers on the sidewalls of the trench or pillar and a local oxidation. This will result in an oxide layer on all exposed planar surfaces, but no oxide layer on the protected vertical channel area of the pillar. The encroachment of the oxide on the side of the pillar is studied by transmission electron microscopy (TEM) which is used to calibrate the nitride viscosity in the process simulations. Surround gate vertical transistors incorporating the spacer oxidation have been fabricated, and these transistors show the integrity of the process and excellent subthreshold slope and drive current. The reduction in intrinsic capacitance is calculated to be a factor of three. Pillar capacitors with a more advanced process have been fabricated and the total measured capacitance is reduced by a factor of five compared with structures without the spacer oxidation. Device simulations confirm the measured reduction in capacitance.     

Determination of mobility in modulation-doped FET's using magnetoresistance effect

A simple measurement technique based on the magnetoresistance effect is developed to obtain the differential and average mobilities of modulation-doped field-effect transistors (MODFET's) with respect to gate bias voltage. The effect of parasitic series resistances can be neglected by using a low magnetic field. The measurement is not affected by parasitic gate capacitance and therefore constitutes an effective tool for characterizing fully processed ultra-short gate-length MODFET's.     

MOSFET-like CNFET based logic gate library for low-power application: a comparative study

The next generation of logic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLSI. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average power-delay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.     

Comparing carbon nanotube transistors - the ideal choice: a novel tunneling device design

Three different carbon nanotube (CN) field-effect transistor (CNFET) designs are compared by simulation and experiment. While a C-CNFET with a doping profile similar to a "conventional" (referred to as C-CNFET in the following) p-or n-MOSFET in principle exhibits superior device characteristics when compared with a Schottky barrier CNFET, we find that aggressively scaled C-CNFET devices suffer from "charge pile-up" in the channel. This effect which is also known to occur in floating body silicon transistors deteriorates the C-CNFET off-state substantially and ultimately limits the achievable on/off-current ratio. In order to overcome this obstacle we explore the possibility of using CNs as gate-controlled tunneling devices (T-CNFETs). The T-CNFET benefits from a steep inverse subthreshold slope and a well controlled off-state while at the same time delivering high performance on-state characteristics. According to our simulation, the T-CNFET is the ideal transistor design for an ultrathin body three-terminal device like the CNFET.     

Analysis of Geometry-Dependent Parasitics in Multifin Double-Gate FinFETs

This paper analyzes the geometry-dependent parasitic components in multifin double-gate fin field-effect transistors (FinFETs). Parasitic fringing capacitance and overlap capacitance are physically modeled as functions of gate geometry parameters using a conformal mapping method. Also, a physical gate resistance model is presented, combined with parasitic capacitive couplings between source/drain fins and gates. The effects of geometrical parameters on FinFET design under different device configurations are thoroughly studied     

High-performance hydrogenated amorphous-Si TFT for AMLCD and AMOLED applications

A novel technology for manufacturing high-performance hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) is developed in this letter. In the bottom gate light-shield a-Si:H TFT structure, the side edge of a-Si:H island is capped with extra deposition of heavily phosphorous-doped a-Si layer. Such an ingenuity can effectively eliminate the leakage path between the parasitic contacts of source/drain metal and the sidewall of a-Si:H island edge. In addition, electrical performance of the novel a-Si:H TFT device exhibits superior effective carrier mobility as high as 1.05 cm/sup 2//Vs, due to the enormous improvement in parasitic resistance. The impressively high performance of the proposed a-Si:H TFT provides the potential to apply foractive matrix liquid crystal display and active matrix organic light-emitting diode technology.     

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.     

Submicrometer-channel CMOS for low-temperature operation

A 0.5-µm-channel CMOS design optimized for liquid-nitrogen temperature operation is described. Thin gate oxide (12.5 nm) and dual polysilicon work functions (n⁺-poly gate for n-channel and p⁺-poly for p-channel transistors) are used. The power supply voltage is chosen to be 2.5 V based on performance, hot-carrier effects, and power dissipation considerations. The doping profiles of the channel and the background (substrate or well) are chosen to optimize the mobility, substrate sensitivity, and junction capacitance with minimum process complexity. The reduced supply voltage enables the use of silicided shallow arsenic and boron junctions, without any intentional junction grading, to control short-channel effects and to reduce the parasitic series resistance at 77 K. The same self-aligned silicide over the polysilicon gate electrode reduces the sheet resistance (as low as 1 Ω/sq at 77 K) and provides the strapping between the gates of the complementary transistors. The design has been demonstrated by a simple n-well/p-substrate CMOS process with very good device characteristics and ring-oscillator performance at 77 K.     

An analytical approach to the capacitance-voltage characteristicsof double-heterojunction HEMTs

The two-dimensional electron gas concentration and capacitance in AlGaAs/GaAs/AlGaAs double-heterojunction high-electron-mobility transistors (DH-HEMTs) are calculated as a function of gate voltage using simple iterative solutions of analytical equations. The results show very good agreement with experimental data, as well as with characteristics predicted by complex numerical methods. The calculations are extended to predict the capacitance-voltage characteristics in the presence of parasitic conduction when the gate does not fully control the two-dimensional gas. The developed charge control and capacitance models are easy and inexpensive to run. They are therefore very useful for microwave circuit designs. Furthermore, they can be used for performance prediction and design optimization of DH-HEMTs. The influence of technological parameters, such as layer thickness and aluminum composition, on device performance are presented     

Modeling and Significance of Fringe Capacitance in Nonclassical CMOS Devices With Gate–Source/Drain Underlap

Parasitic gate–source/drain (G–S/D) fringe capacitance in nonclassical nanoscale CMOS devices, e.g., double-gate (DG) MOSFETs, is shown, using two-dimensional numerical simulations, to be very significant, gate bias-dependent, and substantially reduced by a well-designed G–S/D underlap. Analytical modeling of the outer and inner components of the fringe capacitance is developed and verified by the numerical simulations; a BOX-fringe component is modeled for single-gate fully depleted silicon-on-insulator MOSFETs. With the new modeling implemented in UFDG, our process/physics-based generic compact model for DG MOSFETs, UFDG/Spice3 shows how nanoscale DG CMOS speed is severely affected by the fringe capacitance and how this effect can be moderated by an optimal underlap, which yields a good tradeoff between the parasitic capacitance and the S/D resistance.     

50-nm Self-Aligned and “Standard” T-gate InP pHEMT Comparison: The Influence of Parasitics on Performance at the 50-nm Node

Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In_0.7Ga_0.3As channel 50-nm self-aligned and "standard" T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and fT up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT system