A Full On-Chip CMOS Clock-and-Data Recovery IC for OC-192 Applications

In this paper, a fully integrated OC-192 clock-and-data recovery (CDR) architecture in standard 0.18-mum CMOS is described. The proposed architecture integrates the typically large off-chip filter capacitor by using two feed-forward paths configuration to generate zero and pole and satisfies SONET jitter requirements with a total power dissipation (including the buffers) of 290 mW. The measured RMS jitter of the recovered data is 0.74 ps with a bit-error rate less than 10^-12 when the input pseudorandom bit sequence (PRBS) data pattern has a pattern length of 2¹⁵ - 1 and a total horizontal eye closure of 0.54 peak-to-peak unit interval (Ul_pp) due to the added intersymbol interference distortion by passing data through 9-in FR4 printed circuit board trace. The chip exceeds SONET OC-192 jitter tolerance mask, and high-frequency jitter tolerance is over 0.31 Ul_pp by applying PRBS data with a pattern length of 2³¹ - 1.     

A 40–44 Gb/s 3× Oversampling CMOS CDR/1:16 DEMUX

A CMOS CDR and 1:16 DEMUX fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3times blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5 GHz clock from 48 demultiplexed samples spanning 16 UI. Conformance to the ITU-T G.8251 jitter tolerance mask (BER <10^-12 with a 2³¹-1 PRBS source) is demonstrated using both an on-chip and an external BERT.     

A CMOS clock recovery circuit for 2.5-Gb/s NRZ data

This paper describes a phase-locked clock recovery circuit that operates at 2.5 Gb/s in a 0.4-μm digital CMOS technology. To achieve a high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase technique to operate reliably across a wide range. A sample-and-hold phase detector is also described that combines the advantages of linear and nonlinear phase detectors. The recovered clock exhibits an rms jitter of 10.8 ps for a PRBS sequence of length 2⁷-1 and a phase noise of -80 dBc/Hz at a 5-MHz offset. The core circuit dissipates a total power of 33.5 mW from a 3.3-V supply and occupies an area of 0.8×0.4 mm²     

A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector

This paper presents a 10-Gb/s clock and data recovery (CDR) and demultiplexer IC in a 0.13-mum CMOS process. The CDR uses a new quarter-rate linear phase detector, a new data recovery circuit, and a four-phase 2.5-GHz LC quadrature voltage-controlled oscillator for both wide phase error pulses and low power consumption. The chip consumes 100 mA from a 1.2-V core supply and 205 mA from a 2.5-V I/O supply including 18 preamplifiers and low voltage differential signal (LVDS) drivers. When 9.95328-Gb/s 2³¹-1 pseudorandom binary sequence is used, the measured bit-error rate is better than 10^-15 and the jitter tolerance is 0.5UIpp, which exceeds the SONET OC-192 standard. The jitter of the recovered clock is 2.1 psrms at a 155.52MHz monitoring clock pin. Multiple bit rates are supported from 9.4 Gb/s to 11.3 Gb/s     

A 10-Gb/s silicon bipolar IC for PRBS testing

A 10 Gb/s silicon bipolar IC for pseudorandom binary sequence (PRBS) testing was fabricated and tested. The IC features PRBS generation of the sequences of length 2¹⁵-1 and 2²³-1 b up to 10 Gb/s according to CCITT recommendations. Furthermore, the IC is capable of analyzing PRB sequences of the same length and generation polynomials so that a full test of components is possible. In addition, a new PRBS test word synchronization can be provided between two chips for external multiplexing of the sequences up to 40 Gb/s. The IC can be connected to a standard PC, so evaluation of the error test data can be performed in a flexible way. The IC was fabricated with the HP25 process of Hewlett Packard company, the chip size is 32 mm², and it consumes 6.2 W at the nominal supply voltage of -5 V     

A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology

A 33.6–33.8 Gb/s burst-mode clock/data recovery circuit (BMCDR) is presented in this paper. To reduce the data jitter and generate the high-frequency output clock, the LC gated voltage-controlled oscillator is presented. To receive and transmit the broadband data, a wideband input matching circuit and a wideband data buffer are presented, respectively. The phase selector is proposed to overcome the false phase lock due to the full-rate operation. This proposed BMCDR has been fabricated in a 90 nm CMOS process. The measured peak-to-peak and rms jitters for the recovered data are 7.56 ps and 1.15 ps, respectively, for a 33.72 Gb/s, 2 $^{11} -$1 PRBS. The measured bit error rate is less than $10^{-8}$ for a 33.72 Gb/s, 2$^{7} -$1 PRBS. It consumes 73 mW without buffers from a 1.2 V supply.      

A 12.5 Gb/s Si bipolar IC for PRBS generation and bit errordetection up to 25 Gb/s

This paper describes a Si bipolar IC which features PRBS generation, bit error detection, (de-) scrambling, and trigger derivation up to 12.5 Gb/s. The sequence length is switchable between 2 ¹¹-1 and 2¹⁵-1 b. Two input/output channels are provided which allow PRBS testing up to 25 Gb/s with one external MUX/DMUX. The 3×4 mm², 1377 transistor chip uses 0.4 μm emitter 25-GHz-f_T single-poly self-aligned Si bipolar technology and dissipates 4.6 W from a single -5 V supply     

A 3.3-V 21-Gb/s PRBS generator in AlGaAs/GaAs HBT technology

We present a pseudorandom bit sequence (PRBS) generator that outputs a 2⁷-1 bit pattern at rates up to 21 Gb/s. The circuit is implemented in a 40-GHz AlGaAs/GaAs heterojunction bipolar transistor (HBT) standard production process, operates from a single 3.3-V power supply, and consumes 1.1 W of power. We discuss variations of PRBS architecture and digital circuit topologies which exploit unique characteristics of AlGaAs/GaAs HBT devices. The work demonstrates the feasibility of using AlGaAs/GaAs HBT technology with low-voltage/low-power design techniques in complex high-speed circuits     

40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS

High-speed front-end amplifiers and CDR circuits play critical roles in broadband data receivers as the former needs to perform amplification at high data rate and the latter has to retime the data with the extracted low-jitter clock. In this paper, the design and experimental results of 40 Gb/s transimpedance-AGC amplifier and CDR circuit are described. The transimpedance amplifier incorporates reversed triple-resonance networks (RTRNs) and negative feedback in a common-gate configuration. A mathematical model is derived to facilitate the design and analysis of the RTRN, showing that the bandwidth is extended by a larger factor compared to using the shunt-series peaking technique, especially in cases when the parasitic capacitance is dominated by the next stage. Operating at 40 Gb/s, the amplifier provides an overall gain of 2 kOmega and a differential output swing of 520 mV_pp with for input spanning from to . The measured integrated input-referred noise is 3.3muA_rms. The half-rate CDR circuit employs a direction-determined rotary-wave quadrature VCO to solve the bidirectional-rotation problem in conventional rotary-wave oscillators. This guarantees the phase sequence while negligibly affecting the phase noise. With 40 Gb/s 2³¹ - 1 PRBS input, the recovered clock jitter is and 0.7ps_rms. The retimed data exhibits 13.3 ps_pp jitter with BER . Fabricated in 90 nm digital CMOS technology, the overall amplifier consumes 75 mW and the CDR circuit consumes 48 mW excluding the output buffers, all from a 1.2 V supply.     

A Power-Efficient Clock and Data Recovery Circuit in 0.18 μm CMOS Technology for Multi-Channel Short-Haul Optical Data Communication

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two main design parameters for the proposed topology to explore the main tradeoffs in design of low-power GO CDRs. Based on this approach, a top-down design methodology is presented to implement a low-power CDR unit while the JTOL and FTOL requirements of the system are simultaneously satisfied. Using standard digital 0.18 mum CMOS technology, an 8-channel CDR system has been realized consuming 4.2 mW/Gb/s/channel and occupying a silicon area of 0.045 mm² /channel, with the total aggregate data bit rate of 20 Gb/s. The measured FTOL is plusmn3.5% and no error was detected for a 2³¹-1 pseudo-random bit stream (PRBS) input data for 30 minutes, meaning that the bit error rate (BER) is smaller than 10^-12. Meanwhile, a shared-PLL (phase-locked loop) with a wide tuning range and compensated loop gain has been introduced to tune the center frequency of all CDR channels to the desired value.     

A 10-Gb/s CMOS clock and data recovery circuit with a half-ratelinear phase detector

A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-μm CMOS technology in an area of 1.1×0.9 mm², the circuit exhibits an RMS jitter of 1 ps, a peak-to-peak jitter of 14.5 ps in the recovered clock, and a bit-error rate of 1.28×10^-6, with random data input of length 2²³-1. The power dissipation is 72 mW from a 2.5-V supply     

SiGe clock and data recovery IC with linear-type PLL for 10-Gb/sSONET application

An integrated 10 Gb/s clock and data recovery (CDR) circuit is fabricated using SiGe technology, It consists of a linear-type phase-locked loop (PLL) based on a single-edge version of the Hogge phase detector, a LC-tank voltage-controlled oscillator (VCO) and a tri-state charge pump. A PLL equivalent model and design method to meet SONET jitter requirements are presented. The CDR was tested at 9.529 GB/s in full operation and up to 13.25 Gb/s in data recovery mode. Sensitivity is 14 mV_pp at a bit error rate (BER)=10^-9 . The measured recovered clock jitter is less than 1 ps RMS. The IC dissipates 1.5 W with a -5 V power supply     

A circuit design for 2-Gbit/s Si bipolar crosspoint switch LSIs

An 8×8 and an expandable 16×16 crosspoint switch LSI utilizing a new circuit design and super self-aligned process technology (SST-1A) are discussed. The LSIs successfully switched with a bit error rate of less than 10^-9 at 2.5 Gb/s using a 2⁹-1 pseudorandom NRZ sequence. Pulse jitter was limited to less than 80 ps at 1.2 Gb/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell, including a selector. The LSIs have an ECL-compatible interface, -4-V and -2-V power supply voltages, and a power dissipation of less than 0.9 W for the 8×8 LSI and 2.8 W for the expandable 16×16 LSI     

A monolithic 2.3-Gb/s 100-mW clock and data recovery circuit insilicon bipolar technology

A monolithic clock and data recovery PLL circuit is implemented in a digital silicon bipolar technology without modification. The only external component used is the loop filter capacitor. A self-aligned data recovery architecture combined with a novel phase-detector design eliminates the need for nonlinear processing and phase shifter stages. This enables a simpler design with low power and reduced dependence on the bit rate. At 2.3 Gb/s, the test chip consumes 100 mW from a -3.6-V supply, excluding the input and output buffers. The worst-case rms jitter of the recovered clock is less than 14 ps with 2²³-1 pseudorandom bit sequence     

A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-/spl mu/m CMOS

A monolithic 10-Gb/s clock/data recovery and 1:2 demultiplexer are implemented in 0.18-/spl mu/m CMOS. The quadrature LC delay line oscillator has a tuning range of 125 MHz and a 60-MHz/V sensitivity to power supply pulling. The circuit meets SONET OC-192 jitter specifications with a measured jitter of 8 ps p-p when performing error-free recovery of PRBS 2/sup 31/-1 data. Clock and data recovery (CDR) is achieved at 10 Gb/s, demonstrating the feasibility of a half-rate early/late PD (with tri-state) based CDR on 0.18-/spl mu/m CMOS. The 1.9/spl times/1.5 mm/sup 2/ IC (not including output buffers) consumes 285 mW from a 1.8-V supply.     

High-Performance Optical 3R Regeneration for Scalable Fiber Transmission System Applications

This paper proposes and demonstrates optical 3R regeneration techniques for high-performance and scalable 10-Gb/s transmission systems. The 3R structures rely on monolithically integrated all-active semiconductor optical amplifier-based Mach-Zehnder interferometers (SOA-MZIs) for signal reshaping and optical narrowband filtering using a Fabry-Peacuterot filter (FPF) for all-optical clock recovery. The experimental results indicate very stable operation and superior cascadability of the proposed optical 3R structure, allowing error-free and low-penalty 10-Gb/s [pseudorandom bit sequence (PRBS) 2²³-1 ] return-to-zero (RZ) transmission through a record distance of 1 250 000 km using 10 000 optical 3R stages. Clock-enhancement techniques using a SOA-MZI are then proposed to accommodate the clock performance degradations that arise from dispersion uncompensated transmission. Leveraging such clock-enhancement techniques, we experimentally demonstrate error-free 125 000-km RZ dispersion uncompensated transmission at 10 Gb/s (PRBS 2²³-1) using 1000 stages of optical 3R regenerators spaced by 125-km large-effective-area fiber spans. To evaluate the proposed optical 3R structures in a relatively realistic environment and to investigate the tradeoff between the cascadability and the spacing of the optical 3R, a fiber recirculation loop is set up with 264- and 462-km deployed fiber. The field-trial experiment achieves error-free 10-Gb/s RZ transmission using PRBS 2²³-1 through 264 000-km deployed fiber across 1000 stages of optical 3R regenerators spaced by 264-km spans     

A Si bipolar phase and frequency detector IC for clock extractionup to 8 Gb/s

A phase and frequency detector IC is presented that operates up to an NRZ bit rate of 8 Gb/s. The IC comprises a phase detector (PD), a quadrature phase detector (QPD), and frequency detector (FD). In the PD and QPD the VCO signal and the quadrature VCO signal are sampled by the NRZ input signal. The two beat notes provided by this operation are subsequently processed in the FD. The superposition of the FD output and the PD output signals are then fed into a passive loop filter (lag/lead filter). The loop filter and the VCO are external components. The measured pull-in range is >±100 MHz at 8 Gb/s. The measured r.m.s. time jitter of the extracted clock is less than 1.9 ps for a pseudorandom bit sequence (PRBS) length of 2²³-1. A 0.9-μm 12-GHz f_T silicon bipolar process was used to fabricate the chip with a total power consumption of 1.4 W     

Optical phase-locked PSK heterodyne experiment at 4 Gb/s

A 4 Gb/s phase-locked optical PSK (phase shift keying) heterodyne communication system is demonstrated. The receiver was implemented with a single 100-Ω loaded p-i-n photodiode and a 1320-nm diode-pumped miniature Nd:YAG laser as a local oscillator. For a 2⁷-1 PRBS (pseudorandom bit sequence), the receiver sensitivity was -34.2 dBm or 631 photons/bit. The corresponding power on the surface of the detector was -37.3 dBm or 309 photons/bit. With a 2¹⁵-1 PRBS, a 2.6 dB additional sensitivity degradation was observed due to the nonideal frequency response of the phase modulator and the receiver amplifiers     

2.5-Gb/s low-jitter low-power monolithically integrated optical receiver

A high-scale integrated optical receiver including a preamplifier, a limiting amplifier, a clock and data recovery (CDR) block, and a 1:4 demultiplexer (DEMUX) has been realized in a 0.25???m CMOS technology. Using the loop parameter optimization method and the low-jitter circuit design technique, the rms and peak-to-peak jitter of the recovered 625-MHz clock are 9.4 and 46.3?ps, respectively, which meet the jitter specifications stipulated in ITU-T recommendation G.958. The recovered and frequency divided 625?MHz clock has a phase noise of ?83.8 dBc/Hz at 20?kHz offset in response to 2.5?Gb/s PRBS input data (2²³?C1), and the 2.5?Gb/s PRBS data has been demultiplexed into four 625?Mb/s data. The power dissipation is only 0.3?W under a single 3.3 V supply (excluding output buffers).     

A fully integrated SiGe receiver IC for 10-Gb/s data rate

A silicon germanium (SiGe) receiver IC is presented here which integrates most of the 10-Gb/s SONET receiver functions. The receiver combines an automatic gain control and clock and data recovery circuit (CDR) with a binary-type phase-locked loop, 1:8 demultiplexer, and a 2 ⁷-1 pseudorandom bit sequence generator for self-testing. This work demonstrates a higher level of integration compared to other silicon designs as well as a CDR with SONET-compliant jitter characteristics. The receiver has a die size of 4.5×4.5 mm2 and consumes 4.5 W from -5 V