Global design of analog cells using statistical optimization techniques

We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. This methodology enables us to design complex analog cells from scratch within reasonable CPU time. Three different specification types are covered: strong constraints on the electrical performance of the cells, weak constraints on this performance, and design objectives. A mathematical cost function is proposed and a bunch of heuristics is given to increase accuracy and reduce CPU time to minimize the cost function. A technique is also presented to yield designs with reduced variability in the performance parameters, under random variations of the transistor technological parameters. Several CMOS analog cells with complexity levels up to 48 transistors are designed for illustration. Measurements from fabricated prototypes demonstrate the suitability of the proposed methodology.     

The modeling, characterization, and design of monolithic inductorsfor silicon RF IC's

The results of a comprehensive investigation into the characteristics and optimization of inductors fabricated with the top-level metal of a submicron silicon VLSI process are presented. A computer program which extracts a physics-based model of microstrip components that is suitable for circuit (SPICE) simulation has been used to evaluate the effect of variations in metallization, layout geometry, and substrate parameters upon monolithic inductor performance. Three-dimensional (3-D) numerical simulations and experimental measurements of inductors were also used to benchmark the model accuracy. It is shown in this work that low inductor Q is primarily due to the restrictions imposed by the thin interconnect metallization available in most very large scale integration (VLSI) technologies, and that computer optimization of the inductor layout can be used to achieve a 50% improvement in component Q-factor over unoptimized designs     

Loop-based interconnect modeling and optimization approach for multigigahertz clock network design

A highly efficient loop-based interconnect modeling methodology is proposed for multigigahertz clock network design and optimization. Closed-form loop resistance and inductance models are proposed for fully shielded global clock interconnect structures, which capture high-frequency effects including inductance and proximity effects. The models are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip. This modeling methodology greatly improves the clock interconnect simulation efficiency and enables fast physical design exploration. Examples of interconnect performance optimization are demonstrated and design guidelines are proposed.     

Design methodology for synthesizing clock distribution networksexploiting nonzero localized clock skew

An integrated top-down design methodology is presented in this brief for synthesizing high performance clock distribution networks based on application dependent localized clock skew. The methodology is divided into four phases: (1) determining an optimal clock skew schedule composed of a set of nonzero clock skew values and the related minimum clock path delays; (2) designing the topology of the clock distribution network with delays assigned to each branch based on the circuit hierarchy, the aforementioned clock skew schedule, and minimizing process and environmental delay variations; (3) designing circuit structures to emulate the delay values assigned to the individual branches of the clock tree; and (4) designing the physical layout of the clock distribution network. The clock distribution network synthesis methodology is based on CMOS technology. The clock lines are transformed from distributed resistive capacitive interconnect lines into purely capacitive interconnect lines by partitioning the RC interconnect lines with inverting repeaters. Variations in process parameters are considered during the circuit design of the clock distribution network to guarantee a race-free circuit. Nominal errors of less than 2.5% for the delay of the clock paths and 7% for the clock skew between any two registers belonging to the same global data path as compared with SPICE Level-3 are demonstrated     

Sensor-based design of a Delta parallel robot

This paper proposes a sensor-based design methodology in order to design a Delta robot with guaranteed accuracy performance for a dedicated sensor-based controller. This sensor-based design methodology takes into account the accuracy performance of the controller in the design process in order to find optimal geometric parameters of the robot. Three types of controllers are envisaged to be applied to the Delta robot, leading to three different optimal designs: leg-direction-based visual servoing, line-based visual servoing and image moment visual servoing. Based on these three controllers, positioning error models taking into account the error of observation coming from the camera are developed, and the controller singularities are analyzed. Then, design optimization problems are formulated in order to find the optimal geometric parameters and relevant parameters of the camera for the Delta robot for each type of controller. Prototypes of Delta robots have been manufactured based on the obtained optimum design parameters in order to test the performance of the pair {robot-controller}.     

考虑工艺波动的快速RC互连延时统计计算

本文提出了一种考虑工艺波动影响的计算延时和过渡时间的快速统计模型。模型中使用优化的二阶模型描述工艺波动的影响,使用了闭合表达式来表示相关工艺参数和工艺波动影响下的延时和过渡时间之间的关系。仿真实验表明：提出的模型和传统算法有相似的精度和相似的统计特性,而计算效率大大高于基于HSPICE的模特卡罗分析和传统方法。     

Fast statistical delay evaluation of RC interconnect in the presence of process variations

Fast statistical methods of interconnect delay and slew in the presence of process fluctuations are proposed. Using an optimized quadratic model to describe the effects of process variations, the proposed method enables closed-form expressions of interconnect delay and slew for the given variations in relevant process parameters. Simulation results show that the method, which has a statistical characteristic similar to traditional methodology, is more efficient compared to HSPICE-based Monte Carlo simulations and traditional methodology.     

Effect of parameter variations at chip and wafer level on clockskews

In this paper, a methodology is proposed to determine clock skews and the performance of clock architectures considering parameter variations in an early stage of technology development. With this methodology, it is possible to separate process-induced clock skew from other effects like imperfect loading. Parameter variations are seen as one of the most important effects influencing chip performance in future. By comparing a 0.45- and a 0.25-μm technology, it is shown that in the future, process variations will increase clock skew. The clock skews are determined by measuring the relevant device and metal line parameters as a function of position over chip and wafer. In the past, parameters like IDS, Vth, and resistances could be measured very precisely, although it was difficult to measure low capacitances of single metal lines in the range of femto farad. Thus a new measurement method is used to determine interconnect capacitances extremely precisely. Based on these measurement data, a netlist of a defined clock tree is created by a C-program, and the clock signal delay is simulated. From the delay simulation, we calculate the clock skew for each chip dependent on the parameter variations. Experimental results are separated into a basic random fluctuation part and processing-related contributions on the chip and wafer levels. In addition, the effect of temperature gradients on each chip to the clock skew is simulated. The methodology presented is not restricted to just one clocktree but allows investigation of all kinds of clock distribution circuits. The method has clear advantages with respect to chip area against clocktree realizations on a testchip. No direct and costly measurement of signal delays by voltage contrast methods is required, since all parameters are determined by measurement on the device level     

VLSI随机工艺变化下互连线建模与延迟分析

目前互连线的工艺变化问题已成为影响超大规模集成电路性能的重要因素.考虑了互连线工艺变化的空间相关性,将工艺参数变化建模为具有自相关性的随机过程,采用数值仿真及拟合方法得到寄生参数的近似表达式,最后基于Elmore延迟度量分析了随机工艺变化对互连延迟的影响,提出了工艺变化下互连延迟统计特性的估算方法,并通过仿真实验对方法的有效性进行了验证.     

Mass characterisation of organic transistors and Monte-Carlo circuit simulation

We present a method for designing organic circuits using Monte-Carlo based circuit simulation. The organic devices suffer from mismatch and variations that are due to systematic and random fluctuations in the process and material characteristics. In this work, we have used the variable range hopping model to extract the model parameters using a mass characterisation technique. The parameter fluctuations of organic transistors are taken into account and process corners determined based on static (noise margin) and transient (delay) characteristics. Thus a methodology is developed to find the parameter range of individual devices, within which the circuits are having good performance, for instance inverters working with desired noise margin. We also found out the critical parameters of the transistor, that predominantly affects the static and transient performance of an inverter. These critical parameters can be provided as input to the process engineers to fine tune the process. This information can also be used in developing robust circuit design techniques, which can overcome the variation effects of these critical parameters. Thus, a mass characterisation of transistors combined with the proposed method, allows robust circuit design in the presence of huge process variations.     

Statistical modeling of MOS devices for parametric yield prediction

In the manufacturing of VLSI circuits, engineering designs should take into consideration random variations arising from processing. In this paper, statistical modeling of MOS devices is reviewed, and effective and practical models are developed to predict the performance spread (i.e., parametric yield) of MOS devices and circuits due to the process variations. To illustrate their applications, the models are applied to the 0.25 μm CMOS technology, and measured data are included in support of the model calculations.     

Statistical Timing Models for Large Macro Cells and IP Blocks Considering Process Variations

Integrated circuits today rely on extensive reuse of IP bocks and macro cells to meet the demand for high performance system-on-chip. We propose a methodology for extracting timing models of IP blocks and macro cells for statistical timing analysis considering process variations and spatial correlations. We develop efficient models for capturing both inter-die and intra-die variations in device and interconnect parameters. Increasing spatial correlations in variability of the process parameters in subnanometer designs requires instance-specific characterization of these design blocks. We propose a novel technique for instance-specific calibration of precharacterized timing model. The proposed approach was evaluated on large industrial designs of 1.2- and 3.5-M gates in 65-nm technology and validated against SPICE for accuracy.      

Statistical computer-aided design for microwave circuits

A useful methodology for microwave circuit design is presented. A statistical technique known as Design of Experiments is used in conjunction with computer-aided design (CAD) tools to obtain simple mathematical expressions for circuit responses. The response models can then be used to quantify response trade-offs, optimize designs, and minimize circuit variations. The use of this methodology puts the designer's intelligence back into design optimization while making “designing for circuit manufacturability” a more systematic and straightforward process. The method improves the design process, circuit performance, and manufacturability. Two design examples are presented in context to the new design methodology     

SPICE modeling of process variation using location depth corner models

For robust designs, the influence of process variations has to be considered during circuit simulation. We propose a nonparametric statistical method to find sets of simulation parameters that cover the process spread with a minimum number of simulation runs. Process corners are determined from e-test parameter vectors using a location depth algorithm. The e-test corner vectors are then transformed to SPICE parameter vectors by a linear mapping. A special corner extension algorithm makes the resulting simulation setup robust against moderate process shifts while preserving the underlying correlation structure. To be applicable in a production and circuit design environment, the models are integrated into an automated model generation flow for usage within a design-framework. The statistical methods are validated for analog/mixed-signal benchmark circuits.     

Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models

Interconnects constitute a dominant source of circuit delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this paper, a practical interconnect delay and slew analysis technique is presented to facilitate efficient evaluation of wire performance variability. By harnessing a collection of computationally efficient procedures and closed-form formulas, process variations are directly mapped into the variability of the output delay and slew. An efficient method based on sensitivity analysis is implemented to calculate driving point models under variations for gate-level timing analysis. The proposed adjoint technique not only provides statistical performance variations of the interconnect network under analysis, but also produces delay and slew expressions parameterized in the underlying process variations in a quadratic parametric form. As such, it can be harnessed to enable statistical timing analysis while considering important statistical correlations. Our experimental results have indicated that the presented analysis is accurate regardless of location of sink nodes and it is also robust over a wide range of process variations.     

On the Impact of Process Variations for Carbon Nanotube Bundles for VLSI Interconnect

Bundles of single-walled carbon nanotubes (SWCNTs) have been proposed as a possible replacement for on-chip copper interconnect due to their large conductivity and current-carrying capabilities. Given the manufacturing challenges associated with future nanotube-based interconnect solutions, determining the impact of process variations on this new technology relative to standard copper interconnect is vital for predicting the reliability of nanotube-based interconnect. In this paper, we investigate the impact of process variations on future interconnect solutions based on carbon nanotube bundles. Leveraging an equivalent RLC model for SWCNT bundle interconnect, we calculate the relative impact of ten potential sources of variation in SWCNT bundle interconnect on resistance, capacitance, inductance, and delay. We compare the relative impact of variation for SWCNT bundles and standard copper wires as process technology scales and find that SWCNT bundle interconnect will typically have larger overall three-sigma variations in delay. In order to achieve the same percentage variation in both SWCNT bundles and copper interconnect, the percentage variation in bundle dimensions must be reduced by up to 63% in 22-nm process technology     

A methodology for the calculation of stress migration in die-level interconnects

An analytic methodology is presented for the examination of stress migration in the built up interconnect structures on integrated circuit die. The methodology uses finite element analysis combined with a presumed diffusion mechanism to define a vacancy accumulation site and to characterize the flux of vacancies. This physics-based approach accounts for the effects of time, temperature, material systems and interconnect geometry on stress migration. The method should be generally applicable to a wide range of interconnect structures and will find utility in the design of stress migration tolerant designs as well as in failure analysis.Through examples, stress migration within copper lines and vias with low-k and SiO₂ dielectrics is examined. The methodology predicts increased vacancy fluxes with increases in exposure time, line width and temperatures within the range studied. A fundamental mechanism suggesting heightened vacancy fluxes with a low-k dielectric over a SiO₂ dielectric is described. Finally, the methodology is exercised to demonstrate that the apparent activation energy obtained through stress migration testing of built up interconnect structures may not correspond with the governing diffusion mechanism.     

Wire Topology Optimization for Low Power CMOS

An increasing fraction of dynamic power consumption can be attributed to switched interconnect capacitances. Non-uniform wire spacing depending on activity had shown promising power reductions for on-chip buses. In this paper, a new and fast routing optimization methodology based on non-uniform spacing is proposed for entire circuits. No area investment is required, since whitespace remaining after detailed routing is exploited. The proposed methodology has been implemented and tapped into an industry-proven design flow. Wire power reductions of up to 9.55% for modern multiprocessor benchmarks with tight area constraints are demonstrated, twice as much as approaches that do not take switching activities into account. Timing is not adversely affected, and the yield limit is slightly improved.      

Thermal-mechanical optimization of a novel nanocomposite-film typed flip chip technology

The paper aims at optimization of the residual thermal-mechanical behaviors of a novel Flip Chip (FC) technology during and after the fabrication process. In this study, we first introduce the novel adhesive-typed FC packaging technology, consisting of a nanocomposite film for anisotropic electrical conduction and a nonconductive paste (NCP) for developing NCP joints. In the optimization work, the material and geometry properties and the bonding process parameters are considered as the design parameters, and the constraints on the residual behaviors and the design parameters are included. To deal with the multi-criteria design optimization problem, an effective metamodeling-based design optimization scheme is applied, which integrates parametric finite element (FE) analysis, a response surface methodology (RSM) and an updating scheme. Moreover, to assess the residual behaviors, a process-dependent simulation methodology that integrates both transient thermal and nonlinear contact FE analyses and a “death-birth” meshing scheme is carried out. The validity of the process-dependent FE simulation methodology is confirmed through experiment. Finally, two design practices are performed, and the calculated optimal designs are compared with each other and with the original design.It turns out that the present optimization methodology can be very effective and robust in seeking the optimal design of the FC technology with a better residual thermal-mechanical performance after the NCP bonding process.     

一种基于目标延迟约束缓冲器插入的互连优化模型

基于分布式RLC传输线,提出在互连延迟满足目标延迟的条件下,利用拉格朗日函数改变插入缓冲器数目与尺寸来减小互连功耗和面积的优化模型. 在65nm CMOS工艺下,对两组不同类型的互连线进行计算比较,验证该模型在改善互连功耗与面积方面的优点. 此模型更适合全局互连线的优化,而且互连线越长,优化效果越明显,能够应用于纳米级SOC的计算机辅助设计和集成电路优化设计.