A new p-channel MOSFET with large-tilt-angle implanted punchthroughstopper (LATIPS)

A buried-channel p-MOSFET with a large-tile-angle implanted punchthrough stopper (LATIPS) is described. In this device the n⁺ LATIPS region was successfully realized adjacent to the p⁺ source/drain, even without a sidewall spacer, by taking advantage of the n⁺ large-tilt-angle implant. In spite of the relatively deep p⁺ junction of 0.2-μm depth and the low n-well concentration of 1×10¹⁶ cm^-3, the 0.5-μm LATIPS device (with corresponding channel length of 0.3 μm) achieved high punchthrough resistance, e.g. a low subthreshold swing of 95 mV/decade with a high transconductance of 135 mS/mm     

Deep-submicrometer large-angle-tilt implanted drain (LATID)technology

Deep-submicrometer large-angle-tilt implanted drain (LATID) technology is described. It is found by Monte Carlo process simulation and SIMS measurements that a sufficiently long n^- region can be formed under the gate by taking advantage of large-angle-tilt implant and successfully without ion channeling by taking care of the implant direction. A design that offsets the n⁺ implant by sidewall spacers to suppress the n⁺-gate overlap to zero while keeping the n^- region fully overlapped with the gate is found to be crucial for improved performance and reliability. The device performance, such as current drivability and short-channel effects, is described, and the circuit speed is investigated. Hot-carrier effects such as lateral electric field and device lifetime over a wide range of drain structures are also investigated. The tradeoff between device performance and hot-carrier reliability in deep-submicrometer LATID FETs is discussed     

New grooved-gate MOSFET with drain separated from channel implanted region (DSC)

A new grooved-gate MOSFET with its drain separated from channel implanted regions (DSC structure) is proposed for the purpose of obtaining higher breakdown voltages: drain sustaining voltage and highest applicable voltage placed by hot-carrier effects. Nonimplanted regions between channel implanted and source/drain regions are a unique feature of this device structure. The self-aligned nonimplanted region in the channel is obtained by using silicon dioxide and resist overhangs. These overhangs are fabricated by grooving the silicon substrate. The DSC structure helps reduce the electric field at the drain. Characteristics of experimental devices are presented and compared with those of conventional MOSFET's, from the viewpoint of overall VLSI device design. This device structure is shown to provide remarkable improvements, achieving a 3- or 4-V increase in drain sustaining voltage, as well as a 1- or 2-V increase in the highest applicable voltage as limited by hot-electron injection. In addition, the proposed device can alleviate such short-channel effects as Vthlowering, and in particular, diminish narrow-channel effects. The influence of nonimplanted length on breakdown voltage is also clarified using the CADDET, two-dimensional analysis program.     

A new MOSFET structure with self-aligned polysilicon source and drain electrodes

A new MOSFET structure whose source and drain electrodes are self-aligned to the gate electrode is proposed. The new structure utilizes a second layer of polysilicon which is defined by a preferrential etching to form the source and drain regions. Due to the self-alignment property of the source and drain regions, the total device size is decreased by about 50 percent over the conventional MOS transistors when the same design rule is used. Experimental results of the new structure are presented.     

A novel elevated MOSFET source/drain structure

A vertically layered elevated drain structure is proposed which is suitable, in terms of reliability and performance for MOSFET scaling down to the 0.25-μm level without a reduction of the supply voltage below 3.3 V. In this structure, a low-doped polysilicon or crystalline silicon spacer (layer) is used to solve the hot-carrier problem. In contrast to existing device structures, which try to minimize the impact ionization rate, this structure rests on the idea that high-impact ionization and even high hot-carrier injection (HCl) rates can be tolerated as long as they are not detrimental to the device characteristics     

A new short channel MOSFET structure (UMOST)

A new MOSFET structure with a trapezoidal U-shaped channel defined by anisotropic etching is described. The structure results in very short channel devices almost free of short channel effects and achieves higher speed without the use of submicron photolithography. A simplified theory for the structure is presented and compared with experimental results obtained on 1–10 μm channel length devices. This structure may prove useful in the study of conduction in short channel MOSFETs without introducing the complicating two dimensional short channel effects.     

A new cell structure with a spread source/drain (SSD) MOSFET and acylindrical capacitor for 64-Mb DRAM's

A new cell structure for realizing a small memory cell size has been developed for 64-Mb dynamic RAMs (DRAMs). The source/drain regions of a switching transistor are raised by using a selective silicon growth technique. Because of lateral growth of the silicon over gate and field regions, the bitline contact can overlap the gate and field regions. The shallow source/drain junction by the raised source/drain structure realizes a reduction of gate length and isolation spacing. As a result, the DRAM memory cell area can be reduced to 37% of that using the conventional LDD MOSFET. In the fabrication of an experimental DRAM cell, a new stacked capacitor structure has been introduced to maintain enough storage capacitance, even in the small-cell area. The new capacitor is made by a simple and unique process using a cylindrical silicon-nitride sidewall layer. It has been verified that this cell structure has the potential to realize multimegabit DRAMs, such as 64-Mb DRAMs     

A high power MOSFET with a vertical drain electrode and a meshed gate structure

A MOSFET with a maximum power of 200 W in a 5/spl times/5 mm/SUP 2/ chip which exhibits 20-A current, 3000-millimho transconductance and 100-V breakdown voltage has been developed. The features of the device structure are a vertical drain electrode which makes it possible to use most of the surface area for the source electrode, and a meshed gate structure which realizes an increase in the channel width per unit area. The p-channel device with an offset gate structure was fabricated from an n on p/SUP +/ epitaxial wafer by using polysilicon gate and ion implantation processes. The device can be operated stably at ambient temperatures up to 180/spl deg/C. While the bipolar transistor is a suitable power device in the low voltage region, the MOSFET looks more promising in the high voltage region than the V-FET and the bipolar transistor.     

MOSFET drain breakdown voltage

The grounded-gate or gate-assisted drain breakdown voltage of n-channel MOSFET's has been characterized for wide ranges of oxide thickness and substrate doping concentration. Two distinct regimes, one being channel-doping limited and the other being oxide-thickness limited, have been identified. We propose that these two regimes reflect two possible locations of breakdown-at the n+-p junction and in the deep-depletion layer in the n+ drain. They can be separated by their different breakdown voltage dependences on Vgand require different approaches to process improvement.     

A self-aligned elevated source/drain MOSFET

An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior     

A new vertical power MOSFET structure with extremely reduced on-resistance

A new vertical power MOSFET structure called rectangular-grooved MOSFET (RMOS) is proposed, in which the vertical channels are provided along the sidewalls of the rectangular grooves formed by a reactive ion-beam etching (RIBE) technique. The structure is characterized by reduced ON-resistance and high packing density. The relationship between the ON-resistance and the packing density in the new structure is calculated. It is demonstrated that the structure essentially possesses a lower ON-resistance per unit area than VMOS and DMOS structures. Experimental results are also described in detail.     

An n-channel MOSFET with Schottky source and drain

An n-channel MOSFET with Schottky source and drain (SBMOSFET) has been successfully fabricated using tantalum for the Schottky electrodes. For long gatelengths (100 µm), there are no significant differences in the characteristics of these SBMOSFET's compared to those of conventional MOSFET's. A significant current reduction is observed in SBMOSFET's having 10-µm gatelengths, however, due to the barrier between source and channel. In spite of the substantial barrier height (0.7 V) between tantalum and p-silicon, still larger barriers and a reduction in the isolation gap between source and channel are desirable for high-drive-high-speed device operation.     

A new symmetrical double gate nanoscale MOSFET with asymmetrical side gates for electrically induced source/drain

In this paper, we present the unique features exhibited by a novel double gate MOSFET in which the front gate consists of two side gates as an extension of the source/drain. The asymmetrical side gates are used to induce extremely shallow source/drain regions on either side of the main gate. Using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing and the hot carrier effect. Based on our simulation results, we demonstrate that the proposed symmetrical double gate SOI MOSFET with asymmetrical side gates for the induced source/drain is far superior in terms of controlling the short-channel effects when compared to the conventional symmetrical double gate SOI MOSFET. We show that when the side gate length is equal to the main gate length, the device can be operated in an optimal condition in terms of threshold voltage roll-off and hot carrier effect. We further show that in the proposed structure the threshold voltage of the device is nearly independent of the side gate bias variation.     

A new 0.25-μm recessed-channel MOSFET with selectivelyhalo-doped channel and deep graded source/drain

To improve the performance and reliability of deep submicron MOS devices, a gate-recessed MOSFET (GR-MOSFET), which has a selectively halo-doped recessed channel and a deep graded source/drain formed without counterdoping, is proposed. The GR-MOS structure, which adopts a new doping concept, eliminates the tradeoff between drain-induced barrier lowering (DIBL) and hot-carrier effect, which are important to deep submicron device design. It also reduces the V_T lowering effect and the lateral electric field at the drain. A 0.25-μm GR-MOSFET with a 10-nm gate oxide has exhibited 15% higher transconductance and 10% increased saturation current at V_D=V _G=3.3 V, 1 V higher BV_DSS, and six times less substrate current compared with an LDD-MOSFET of the same device dimensions     

MOSFET drain engineering analysis for deep-submicrometerdimensions: a new structural approach

A new MOS transistor structural approach (hot-carrier-induced MOSFET) capable of substantially suppressing adverse hot-carrier effects, while maintaining the other desired performance and manufacturability characteristics of deep-submicrometer MOSFETs (L _gate⩽0.35 μm) is described. This structure is unique in having a lower doped N^- region located behind (or above) a very shallow, steeply profiled source/drain junction. In contrast, LDD types of MOSFETs have an N^- region with a more graded doping profile immediately adjacent to the channel region. The simulated characteristics of the HCS MOSFET structure indicate approximately one order of magnitude less substrate current in comparison to an LDD type of MOSFET whose structure and doping parameters are optimized for combined performance, reliability, and manufacturability. In terms of combined performance, reliability, and manufacturability, the HCS MOSFET should permit MOSFET devices to be more successfully scaled at deep-submicrometer dimensions     

Raised source/drain MOSFET with dual sidewall spacers

A raised source/drain (S/D) MOSFET with sidewall spacers formed both before and after selective epitaxial silicon deposition in S/D regions is discussed. The second spacer overlies any faceted regions of the epitaxial silicon near the gate edge and has advantages for MOSFETs with implant-doped or in-situ doped epitaxial silicon regions. In particular, the spacer can prevent S/D dopants from being implanted through any thinner faceted regions near the gate edge, which would otherwise result in a deeper than desired junction depth in the silicon substrate. Additionally, the spacer can prevent source-to-substrate salicide shorts through the thinner faceted regions     

Arsenic and phosphorus double ion implanted source/drain junctionfor 0.25and sub-0.25-μm MOSFET technology

An arsenic and phosphorus double implanted source/drain junction is proposed for 0.25- and sub-0.25-μm NMOSFET technology. Arsenic is for the shallow high concentration region beneath the silicide, and phosphorus is for the slightly deeper junction to increase junction quality and to reduce junction capacitance. The arsenic and phosphorus double implantation is performed after sidewall formation. The double implanted source/drain junction shows a drastic reduction of reverse leakage current and little effect on the short channel characteristics compared with an arsenic only implanted device. Moreover, the circuit performance is improved by about 2.5%     

A novel source/drain on void (SDOV) MOSFET implemented by local co-implantation of hydrogen and helium

In this paper a novel device named as SDOV MOSFET is proposed for the first time. This structure features localized void layers under the source and drain regions. The short channel effects of this device can be improved due to the SOI-like source/drain structure. In addition, without the dielectric layer under the channel region, this device can avoid some weaknesses of UTB SOI devices caused by the thin silicon film and the underlying buried oxide, such as mobility degradation, film thickness fluctuation and self-heating effect. Based on self-aligned hydrogen and helium co-implantation technology, the new device can be fabricated by a process compatible with the standard CMOS process. The SDOV MOSFETs with 50 nm gate length are experimentally demonstrated for verification.     

Self-align recessed source drain ultrathin body SOI MOSFET

In this letter, a self-aligned recessed source/drain (ReS/D) ultrathin body (UTB) silicon-on-insulator (SOI) MOS technology is proposed and demonstrated. The thick diffusion regions of ReS/D are placed on a recessed trench, which is patterned on the buried oxide and go under the SOI film. The new structure reduces the parasitic S/D resistance without increasing the gate-to-drain Miller capacitance, which is the major advantage over the elevated S/D structure. Fabrication details and experimental results are presented. The scalability of the UTB MOSFETs and the larger design window due to reduced parasitics are demonstrated.     

Influence of dielectric breakdown on MOSFET drain current

Breakdown of gate dielectric is one of the most dangerous threats for reliability of MOSFET devices in operating conditions. Not only the gate leakage resulting from breakdown is a problem for power consumption issues, but the "on" drain current can be strongly affected. In this paper, we show that in recent technologies, featuring ultrathin gate dielectrics, the corruption of drain current due to breakdown can be modeled as the effect of a portion of channel being damaged by the opening of the breakdown spot. Devices featuring 2.2- and 3.5-nm-thick gate oxide and various channel widths are stressed by using a specialized setup, and the degradation of transistor parameters is statistically studied. The analysis shows that the radius of the damaged region responsible for drain current degradation can be estimated between 1.4 and 1.8 /spl mu/m.