Evaluation of solder joint reliability in flip-chip packages during accelerated testing

The microstructural investigation and thermomechanical reliability evaluation of the Sn-3.0Ag-0.5Cu solder bumped flip-chip package were carried out during the thermal shock test of the package. In the initial reaction, the reaction product between the solder and Cu mini bump of chip side was Cu₆Sn₅ intermetallic compound (IMC) layer, while the two phases which were (Cu,Ni)₆Sn₅ and (Ni,Cu)₃Sn₄ were formed between the solder and electroless Ni-P layer of the package side. The cracks occurred at the corner solder joints after the thermal shocks of 400 cycles. The primary failure mechanism of the solder joints in this type of package was confirmed to be thermally-activated solder fatigue failure. The premature brittle interfacial failure sometimes occurred in the package side, but nearly all of the failed packages showed the occurrence of the typical fatigue cracks. The finite-element analyses were conducted to interpret the failure mechanisms of the packages, and revealed that the cracks were induced by the accumulation of the plastic work and viscoplastic shear strains.     

Effects of Phase Change of Pb-Free Flip-Chip Solders During Board-Level Interconnect Reflow

The impact of phase change (from solid to liquid) on the reliability of Pb-free flip-chip solders during board-level interconnect reflow is investigated. Most of the current candidates for Pb-free solder are tin-based with similar melting temperatures near 230 degC. Thus, Pb-free flip-chip solders melt again during the subsequent board-level interconnect reflow cycle. Solder volume expands more than 4% during the phase change from solid to liquid. The volumetric expansion of solder in a volume constrained by chip, substrate, and underfill creates serious reliability issues. The issues include underfill fracture and delamination from chip or substrate. Besides decreasing flip-chip interconnect reliability in fatigue, bridging through underfill cracks or delamination between neighboring flip-chip interconnects by the interjected solder leads to failures. In this paper, the volume expansion ratio of tin is experimentally measured, and a Pb-free flip-chip chip-scale package (FC-CSP) is used to observe delamination and solder bridging after solder reflow. It is demonstrated that the presence of molten solder and the interfacial failure of underfill can occur during solder reflow. Accordingly, Pb-free flip-chip packages have an additional reliability issue that has not been a concern for Pb solder packages. To quantify the effect of phase change, a flip-chip chip-scale plastic ball grid array package is modeled for nonlinear finite-element analysis. A unit-cell model is used to quantify the elongation strain of underfill and stresses at the interfaces between underfill and chip or underfill and substrate generated by volume expansion of solder. In addition, the strain energy release rate of interfacial crack between chip and underfill is also calculated     

Board level solder joint reliability analysis of stacked die mixed flip-chip and wirebond BGA

Stacked die BGA has recently gained popularity in telecommunication applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of lead-free stacked die BGA with mixed flip-chip (FC) and wirebond (WB) interconnect is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. Based on the FC–WB stack die configuration, the critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house lead-free TFBGA46 (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyzes are performed to study the effects of 20 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, thinner PCB and mold compound, thicker substrate, larger top or bottom dice sizes, thicker top die, higher solder ball standoff, larger solder mask opening, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. SnAgCu is a common lead-free solder, and it has much better board level reliability performance than eutectic solder based on modeling results, especially low stress packages.     

高密度陶瓷倒装焊封装可靠性试验开路后的失效定位

陶瓷材料具有优良的综合特性,被广泛应用于高可靠微电子封装.陶瓷倒装焊封装的特殊结构使得对其进行失效分析相较其他传统封装形式更为困难.针对一款在可靠性试验中发生开路的高密度陶瓷倒装焊封装器件,制定了一套从非破坏性到破坏性的试验方案对其进行分析.通过时域反射计(TDR)测试排除了基板内部失效的可能性,通过X射线(X-ray)检测、超声扫描显微镜(SAM)和光学显微分析初步断定失效位置,并最终通过扫描电子显微镜和X射线能谱仪实现了对该器件的准确的失效定位,确定失效位置为基板端镀Ni层.该失效分析方法对其他陶瓷倒装焊封装的失效检测及分析有一定的借鉴意义.     

A new experimental method to evaluate creep fatigue life of flip-chip solder joints with underfill

A new accelerated stress test method was developed to evaluate creep life of flip-chip solder joints with underfill. With this method, a cyclic creep test can be done simply by applying a displacement to the FR-4 printed circuit board (PCB) board in the axial direction. The creep fatigue test was performed under displacement control with real-time electrical continuity monitoring. Test results show that the displacement arising from the force is equivalent to the thermal stress during thermal expansion. It was found that the magnitude of displacement was proportional to the inelastic strain sustained by the solder joints. This indicates that the creep fatigue life obtained will not only reflect the quality of the solder joints, but can also be used to characterize the reliability of the flip-chip assembly. Finite element modeling was also performed to confirm the agreement of deformation of the solder joints under mechanical and thermal loading. Results suggest that deformation and strain of the flip-chip assembly are consistent or comparable between the mechanical and thermal cycling. The failure analysis indicates that fatigue cracks often initiate from the top edge of a corner solder joint in the creep fatigue test, which is similar to what would happen in thermal cycling test. Lastly, the effect of underfill on the creep fatigue test is discussed. It is postulated that the test method is applicable to other flip-chip assemblies, such as conductive adhesive interconnections.     

Impact life prediction modeling of TFBGA packages under board level drop test

Reliability performance of IC packages during drop impact is critical, especially for handheld electronic products. Currently, there is no model that provides good correlation with experimental measurements of acceleration and impact life. In this paper, detailed drop tests and simulations are performed on TFBGA (thin-profile fine-pitch BGA) and VFBGA (very-thin-profile fine-pitch BGA) packages at board level using testing procedures developed in-house. The packages are susceptible to solder joint failures, induced by a combination of PCB bending and mechanical shock during impact. The critical solder ball is observed to occur at the outermost corner solder joint, and fails along the solder and PCB pad interface. Various testing parameters are studied experimentally and analytically, to understand the effects of drop height, drop orientation, number of PCB mounting screws to fixture, position of component on board, PCB bending, solder material, etc. Drop height, felt thickness, and contact conditions are used to fine-tune the shape and level of shock pulse required. Board level drop test can be better controlled, compared with system or product level test such as impact of mobile phone, which sometimes has rather unpredictable results due to higher complexity and variations in drop orientation. At the same time, dynamic simulation is performed to compare with experimental results. The model established has close values of peak acceleration and impact duration as measured in actual drop test. The failure mode and critical solder ball location predicted by modeling correlate well with testing. For the first time, an accurate life prediction model is proposed for board level drop test to estimate the number of drops to failure for a package. For the correlation cases studied, the maximum normal peeling stresses of critical solder joints correlate well with the mean impact lives measured during the drop test. The uncertainty of impact life prediction is within ±4 drops, for a typical test of 50 drops. With this new model, a failure-free state can be determined, and drop test performance of new package design can be quantified, and further enhanced through modeling. This quantitative approach is different from traditional qualitative modeling, as it provides both accurate relative and absolute impact life prediction. The relative performance of package may be different under board level drop test and thermal cycling test. Different design guidelines should be considered, depending on application and area of concern.     

Ceramic packages for liquid-nitrogen operation

To evaluate their compatibility for use in a liquid-nitrogen computer, metallized ceramic packages with test chips using controlled-collapse solder (Pb-Sn) technology were cycled between 30°C and liquid-nitrogen temperature. Room-temperature electrical resistance measurements were made at regular intervals of cycles to determine whether solder failure accompanied by a significant resistance increase had occurred. For the failed solder joints characterized by the highest thermal shear strain amplitude of 3.3%, it was possible to estimate the number of liquid-nitrogen cycles needed to produce the corresponding failure rate using a room-temperature solder lifetime model. Cross-sectional examination of the failed solder joints using scanning electron microscopy (SEM) and energy-dispersive X-ray analysis indicated solder cracking occurring at the solder-ceramic interface. Chip-pull tests on cycled packages yielded strengths far exceeding the minimal requirement. Mechanisms involving the formation of intermetallics are proposed to account for the observed solder fracture modes after liquid-nitrogen cycling and after chip pull. SEM examination of pulled chips in cycled packages found no apparent sign of cracking in quartz and polyimide for chip insulation     

Random vibration reliability of BGA lead-free solder joint

Solder joint fatigue failure under vibration loading has been a great concern in microelectronic industry. High-cycle fatigue failure of lead-free solder joints has not been adequately addressed, especially under random vibration loading. This study aims to understand the lead-free solder joint behavior of BGA packages under different random vibration loadings. At first, non-contact TV Laser holography technology was adopted to conduct experimental modal analysis of the test vehicle (printed circuit board assembly) in order to understand its dynamic characteristics. Then, its first order natural frequency was used as the center frequency and narrow-band random vibration fatigue tests with different kinds of acceleration power spectral density (PSD) amplitudes were respectively carried out. Electrical continuity through each BGA package is monitored during the vibration event in order to detect the failure of package-to-board interconnects. The typical dynamic voltage histories of failed solder joints were obtained simultaneously. Thirdly, failed solder joints were cross-sectioned and metallurgical analysis was applied to investigate the failure mechanisms of BGA lead-free solder joints under random vibration loading. The results show that the failure mechanisms of BGA lead-free solder joint vary as the acceleration PSD amplitude increases. Solder joint failure locations are changed from the solder bump body of the PCB side to the solder ball neck, finally to the Ni/intermetallic compound (IMC) interface of the package side. The corresponding failure modes are also converted from ductile fracture to brittle fracture with the increase of vibration intensity.     

Parametric reliability analysis of no-underfill flip chip package

This research proposes a parametric analysis for a flip chip package with a constraint-layer structure. Previous research has shown that flip-chip type packages with organic substrates require underfill for achieving adequate reliability life. Although underfill encapsulant is needed to improve the reliability of flip chip solder joint interconnects, it will also increase the difficulty of reworkability, increase the packaging cost and decrease the manufacturing throughput. This research is based on the fact that if the thermal mismatch between the silicon die and the organic substrate could be minimized, then the reliability of the solder joint could be accordingly enhanced. This research proposes a structure using a ceramic-like material with CTE close to silicon, mounted on the backside of the substrate to constrain the thermal expansion of the organic substrate. The ceramic-like material could reduce the thermal mismatch between silicon die and substrate, thereby enhancing the reliability life of the solder joint. Furthermore, in order to achieve better reliability design of this flip chip package, a parametric analysis using finite element analysis is performed for package design. The design parameters of the flip chip package include die size, substrate size/material, and constraint-layer size/material, etc. The results show that this constraint-layer structure could make the solder joints of the package achieve the same range of reliability as the conventional underfill material. More importantly, the flip chip package without underfill material could easily solve the reworkability problem, enhance the thermal dissipation capability and also improve the manufacturing throughput     

Materials characterization of the effect of mechanical bending on area array package interconnects

The mechanical integrity of solder joint interconnects in PWB assemblies with micro-BGA, chip scale, and land grid array packages is being questioned as the size and pitch decrease. Some consumer products manufacturers have mechanically reinforced fine pitch package interconnects with an adhesive underfill, and others are evaluating the need for underfill on a case-by-case basis. Three-point cyclic bend testing provides a useful tool for characterizing the expected mechanical cycling fatigue reliability of PWB assemblies. Cyclic bend testing is useful for characterizing bending issues in electronic assemblies such as repetitive keypad actuation in cell phone products. This paper presents the results of three-point bend testing of PWB assemblies with fine pitch packages. The solder joints on ceramic components performed better than a laminate interposer component in bend testing, because of the stiffening effect of the ceramic packaging materials. The methodology of materials analyses of the metallurgy of solder interconnects following mechanical bending and thermal cycle testing is described. The microstructure and fracture surfaces of solder joint failures in bend test samples differed significantly from thermal cycle test samples.     

Optimization of board-level thermomechanical reliability of high performance flip-chip package assembly

In this paper, we study board-level thermomechanical reliability of a high performance flip-chip ball grid array package assembly subjected to an accelerated thermal cycling test condition. Different control factors are considered for an optimal design towards enhancement of the thermal fatigue resistance of solder joints. These factors include solder composition, underfill, substrate size, lid thickness, stiffener ring width, test board size, soldermask opening on the substrate side, and pad size on the test board. The shape of solder joints after reflow is estimated using Surface Evolver. The optimal design is obtained using an L₁₈ orthogonal array according to the Taguchi optimization method. Importance of these control factors on the board-level thermomechanical reliability of the package is also ranked.     

ENIG Corrosion Induced by Second-Phase Precipitation

Materials analysis of a flip-chip package lot with solder bump interconnect failures revealed a new mechanism for corrosion of electroless nickel immersion gold surface finish. Detailed scanning and transmission electron microscopy (SEM and TEM) in conjunction with focused ion beam microscopy and electron dispersion analysis of the unsoldered ball grid array substrate pads on packages that exhibited flip-chip solder bump interconnect failures revealed an unusual and subtle defect in the original Ni(P) layer, which was ultimately responsible for flip-chip joint failure. Detailed TEM analysis of the defect regions showed that they consisted of Ni(P) particles of slightly different composition than the bulk Ni(P) layer. Microstructure changes around these incorporated particles indicated that the second-phase particles were deposited from the plating bath during the Ni(P) growth stage. The second-phase particles provided additional surface area for nucleation and growth of Ni(P). Ultimately, a low-density boundary region in the growing Ni(P) layer formed where the particle-induced growth front and the planar Ni(P) film growth front intersected. This low-density interface eventually terminated at the surface of the Ni(P) layer. In addition the growth from the second-phase particle created localized surface topology that was different than that of the surrounding Ni(P) layer. The low-density interfaces as well as the surface topology led to enhanced corrosion of the Ni(P) layer when exposed to the immersion gold plating process. In some cases the corrosion was severe enough to create voids in the Ni(P) layer. The exposed, oxidized Ni(P) surfaces in and around these enhanced corrosion regions did not wet when exposed to solder. This led to degradation in the strength of the solder joint and subsequent solder interconnect failure.     

集成电路陶瓷外壳析出物失效模式分析

为了集成电路的可靠性保证,往往需要对集成电路外壳进行验收。验收项目中,有一个耐湿试验分组,用来加速评定外壳的抗腐蚀性能及相应的质量可靠性能。在该试验分组中发现,陶瓷外壳失效除了已有的常规模式外,还有一种很严重的析出物失效模式。发现焊框与陶瓷结合处有胶体状析出物,析出物以流质状态析出,然后凝固,严重的还会造成焊框漏气,从而引起外壳失效。     

Failure mechanism study of anisotropic conductive film (ACF) packages

Anisotropic conductive film (ACF) consists of an adhesive polymer matrix with dispersed conductive particles. In flip-chip technology, ACF has been used in place of solder and underfill for chip attachment to glass or organic substrates. The filler particles establish the electrical contacts between the interconnecting areas. ACF flip-chip bonding provides finer pitch, higher package density, reduced package size and improved lead-free compatibility. Nevertheless, the interconnection is different from traditional solder joints, the integrity and durability of the ACF interconnects have major concerns. Failures in anisotropic conductive film (ACF) parts have been reported after temperature cycling, moisture preconditioning and autoclave. The failures have not been well understood and have been attributed to a wide variety of causes. This paper investigates the failure mechanism of ACF using finite element simulation. From a failure-initiation point of view, the response of ACF packages to environmental (temperature and humidity) exposure is very different from standard underfilled packages. These differences cause the ACF package to fail in different ways from an underfilled package. Simulation results have shown that moisture-induced ACF swelling and delamination is the major cause of ACF failure. With moisture absorption, the loading condition at the interface is tensile-dominant, which corresponds to lower interface toughness (or fracture resistance). This condition is more prone to interface delamination. Therefore, the reliability of ACF packages is highly dependent on the ACF materials. The paper suggests a new approach toward material selection for reliable ACF packages. This approach has very good correlation with experimental results and reliability testing of various ACF materials.     

Computational modelling for reliable flip-chip packaging at sub-100 μm pitch using isotropic conductive adhesives

This paper presents the assembly process using next generation electroformed stencils and Isotropic Conductive Adhesives (ICAs) as interconnection material. The utilisation of ICAs in flip-chip assembly process is investigated as an alternative to the lead and lead-free solder alloys and aims to ensure a low temperature (T < 100 °C) assembly process. The paper emphasizes and discusses in details the assembly of a flip-chip package based on copper columns bumped die and substrate with stencil printed ICA deposits at sub-100 μm pitch. A computational modelling approach is undertaken to provide comprehensive results on reliability trends of ICA joints subject to thermal cycling of the flip-chip assembly based on easy to use damage criteria and damage evaluation. Important design parameters in the package are selected and investigated using numerical modelling techniques to provide knowledge and understanding of their impact on the thermo-mechanical behaviour of the flip-chip ICA joints. Sensitivity analysis of the damage in the adhesive material is also carried out. Optimal design rules for enhanced performance and improved thermo-mechanical reliability of ICA assembled flip-chip packages are finally formulated.     

陶瓷封装倒装焊器件Sn-Pb微焊点的电迁移行为

高密度陶瓷封装倒装焊器件的焊点尺寸已降低至100μm以下,焊点电流密度达到10~4 A/cm~2以上,由此引发的电迁移失效成为不可忽视的问题。以陶瓷封装菊花链倒装焊器件为研究对象,开展了Sn10Pb90、Sn63Pb37焊点热电环境可靠性评估试验,通过电连接检测及扫描电子显微镜(SEM)等方法对焊点互连情况进行分析。结果表明,Sn63Pb37焊点阴极侧金属间化合物(IMC)增长明显,表现出明显的极化现象,IMC厚度的平方与通电时间呈线性关系。通电时间达到576 h后Sn63Pb37焊点阴极侧产生微裂纹,而Sn10Pb90焊点在通电576 h后仍未出现异常,表现出优异的电迁移可靠性。研究结果对于直径100μm微焊点的陶瓷封装倒装焊器件的应用具有重要的意义。     

CQFP器件板级温循可靠性的设计与仿真

温度循环是考核封装产品板级可靠性的重要试验之一。陶瓷四边引脚扁平封装(CQFP)适用于表面贴装,由于陶瓷材料与PCB热膨胀系数的差异,温循过程中引线互联部分产生周期性的应力应变,当陶瓷壳体面积较大时,焊点易出现疲劳失效现象。CQFP引线成形方式分顶部成形和底部成形两类。针对CQFP引线底部成形产品在板级温循中出现的焊接层开裂现象,采用有限元方法对焊接层的疲劳寿命进行了预测分析。采用二次成形方法对引线进行再次成形以缓解和释放热失配产生的应力。仿真和试验结果显示,引线二次成形有利于提高焊接层的温循疲劳寿命。与引线底部成形相比,当引线采用顶部成形时,焊接层的温循疲劳寿命显著提高。     

Hygrothermal Failures From Small Defects in Lead-Free Solder Reflowed Electronic Packages

Steam-driven delamination failure is a main failure mode in electronics packages during solder reflow. Steam pressures built up within interfaces in packages are sensitive functions of the reflow temperature. The switch to lead-free soldering will raise re-flow temperature by more than 20degC and double the equilibrium saturated steam pressure within defects in the package. The effects of saturated steam driven interfacial failure was analyzed using finite element in this study. Analyses revealed that packages which are thin and made using high thermal conductivity materials are at higher risk of failure than conventional packages made using standard materials. This suggests that electronics made with thick and inexpensive encapsulants are less prone to failure when switched to lead-free solder. Portable and mobile electronics which have low profiles and are made of high thermal conductive encapsulants are at higher risk when switched to lead-free solder reflow. Moreover, the study found that the critical temperature for failure is dependent on the defect size in the package. Reduction of initial defect size can reduce failures in high risk packages in lead-free solder reflow.     

Local melting induced by electromigration in flip-chip solder joints

A new electromigration failure mechanism in flip-chip solder joints is reported. The solder joints failed by local melting of a PbSn eutectic solder. Local melting occurred due to a sequence of events induced by the microstructure changes in the flip-chip solder joint. The formation of a depression in the current-crowding region of a solder joint induced the local electrical resistance to increase. The rising local resistance resulted in a larger Joule heating, which, in turn, raised the local temperature. When the local temperature rose above the eutectic temperature of the PbSn solder, the solder joint melted and consequently failed. The results of this study suggest that a dynamic, coupled simulation that takes into account the microstructure evolution, current density distribution, and temperature distribution may be needed to fully solve this problem.     

Calibration of electromigration reliability of flip-chip packages by electrothermal coupling analysis

Electromigration reliability of solder interconnects is dominated by current density and temperature inside the interconnects. For flip-chip packages, current densities around the regions where the traces connect a solder bump increase significantly due to the differences in feature sizes and electric resistivities between the solder bump and its adjacent traces. This current-crowding effect along with induced Joule heating accelerates electromigration failures. In this paper, the effects of current crowding and Joule heating in a flip-chip package are examined and quantified by three-dimensional electrothermal coupling analysis. We apply a volumetric averaging technique to cope with the current-crowding singularity. The volumetrically averaged current density and the maximum temperature in a solder bump are integrated into Black’s equation to calibrate the experimental electromigration fatigue lives. An erratum to this article is available at .