Low-level programming in modula-2: An experience with local area network access

Access to a computer network, which is currently a topic of some importance to the high-level language programmer, can be provided in a number of ways. This paper describes one such example, where users of the language Modula-2 were given access to a local area network. The author discusses the type of problem that needs to be overcome, when a language such as Modula-2, which was designed as part of an integrated systems architecture, is used for low-level programming in a different architectural environment.     

Specifying and enforcing high-level semantic obligation policies

Obligation policies specify management actions that must be performed when a particular kind of event occurs and certain conditions are satisfied. Large scale distributed systems often produce event streams containing large volumes of low-level events. In many cases, these streams also contain multimedia data (consisting of text, audio or video). Hence, a key challenge is to allow policy writers to specify obligation policies based on high-level events, that may be derived after performing appropriate processing on raw, low-level events. In this paper, we propose a semantic obligation policy specification language called Eagle, which is based on patterns of high-level events, represented as RDF graph patterns. Our policy enforcement architecture uses a compiler that builds a workflow for producing a stream of events, which match the high-level event pattern specified in a policy. This workflow consists of a number of event sources and event processing components, which are described semantically. We present the policy language and enforcement architecture in this paper.     

An optimizing compiler for an SPAP architecture using AI tools

A methodology that allows users to efficiently bridge the gap between high-level language and low-level microcode when implementing intensive mathematical operations and manipulations algorithms is discussed. The use of an optimized special-purpose array processor (SPAP) architecture for numerical computation and a host microprocessor for nonnumerical computation operations is described. The advantages of the optimizing compiler, the target architecture, and the compiler's implementation using AI tools are examined     

Intelligent Control for Robotic Rehabilitation after Stroke

The paper presents a new control approach to robot-assisted rehabilitation for stroke patients. The control architecture is represented in terms of a hybrid system model combining a high-level and a low-level assistive controller. The high-level controller is designed to monitor the progress and safety of the rehabilitation task. The high-level controller also makes decisions on the modification of the task that might be needed for the therapy. A design of a low-level assistive controller that provides robotic assistance for an upper arm rehabilitation task and works in coordination with the proposed high-level controller is discussed. Experimental results on unimpaired participants are presented to demonstrate the efficacy of both the high-level and low-level assistive controllers.     

A Low-Level Analysis Library for Architecture Recovery

We discuss low-level program analyses that are reusable in many high-level analyses for architecture recovery. They include both program structure analyses known from compiler front-ends and data-flow analyses. In general, high-level analyses use the low-level results only partially. We argue that it is necessary to perform the low-level analyses completely, though. To deal with large systems and to adapt to different high-level analyses, it is, however, necessary to control the low-level analyses' precision and scope.     

Texture synthesis techniques for computer graphics

Five primary approaches to texture synthesis for computer graphics are surveyed: a syntactic approach, a statistical approach, a growth model approach, a computer drafting approach, and a stochastic modeling approach. Most of these methods, derived from texture analysis techniques or from mathematical models of texture, have a relatively low-level, cumbersome way to define, manipulate, or input textures. As an alternative, a high-level language approach is proposed. It provides easy-to-use coding mechanisms to define, synthesize, and manipulate textures. The high-level approach is introduced by means of the Texture Synthesis Language (TSL).     

Book Reviews

This book presents a survey of some of the elements of high-level language computer architecture in the form of individual papers.     

Security types preserving compilation

Starting from the seminal work of Volpano and Smith, there has been growing evidence that type systems may be used to enforce confidentiality of programs through non-interference. However, most type systems operate on high-level languages and calculi, and “low-level languages have not received much attention in studies of secure information flow” (Sabelfeld and Myers, [Language-based information-flow security. IEEE Journal on Selected Areas in Communications 2003; 21:5–19]). Therefore, we introduce an information flow type system for a low-level language featuring jumps and calls, and show that the type system enforces termination-insensitive non-interference.Furthermore, information flow type systems for low-level languages should appropriately relate to their counterparts for high-level languages. Therefore, we introduce a compiler from a high-level imperative programming language to our low-level language, and show that the compiler preserves information flow types.     

一种用于Java程序验证编译的标签类型

在基于语言考虑代码安全性的工作中,往往需要将高级语言程序翻译成类型化低级语言的程序进行类型检查.许多高级语言具有类型调度结构,在向低级语言的编译过程中需要用标签机制来实现.针对具有多继承接口的Java程序包含的一种特殊的类型调度结构,提出了一种新的标签类型.包含这种标签类型的低级语言能够有效地实现Java程序中的接口调用.这种对接口调用的编译方法被用在一个以类型化低级语言为验证语言的Java字节码即时编译器中.     

A New FPGA/DSP-Based Parallel Architecture for Real-Time Image Processing

In this article, we present a new reconfigurable parallel architecture oriented to video-rate computer vision applications. This architecture is structured with a two-dimensional (2D) array of FPGA/DSP-based reprogrammable processors P_ij. These processors are interconnected by means of a systolic 2D array of FPGA-based video-addressing units which allow video-rate links between any two processors in the net to overcome the associated restrictions in classic crossbar systems such as those which occur with butterfly connections. This architecture has been designed to deal with parallel/pipeline procedures, performing operations which handle various simultaneous input images, and cover a wide range of real-time computer vision applications from pre-processing operations to low-level interpretation. This proposed open architecture allows the host to deal with final high-level interpretation tasks. The exchange of information between the linked processorsP_ij of the 2D net lies in the transfer of complete images, pixel by pixel, at video-rate. Therefore, any kind of processor satisfying such a requirement can be integrated. Furthermore, the whole architecture has been designed host-independent.     

基于深度学习的图像检索系统

基于内容的图像检索系统关键的技术是有效图像特征的获取和相似度匹配策略.在过去,基于内容的图像检索系统主要使用低级的可视化特征,无法得到满意的检索结果,所以尽管在基于内容的图像检索上花费了很大的努力,但是基于内容的图像检索依旧是计算机视觉领域中的一个挑战.在基于内容的图像检索系统中,存在的最大的问题是“语义鸿沟”,即机器从低级的可视化特征得到的相似性和人从高级的语义特征得到的相似性之间的不同.传统的基于内容的图像检索系统,只是在低级的可视化特征上学习图像的特征,无法有效的解决“语义鸿沟”.近些年,深度学习技术的快速发展给我们提供了希望.深度学习源于人工神经网络的研究,深度学习通过组合低级的特征形成更加抽象的高层表示属性类别或者特征,以发现数据的分布规律,这是其他算法无法实现的.受深度学习在计算机视觉、语音识别、自然语言处理、图像与视频分析、多媒体等诸多领域取得巨大成功的启发,本文将深度学习技术用于基于内容的图像检索,以解决基于内容的图像检索系统中的“语义鸿沟”问题.     

An innovative software architecture to improve information flow from CAM to CNC

Over the years, machine tool evolution has allowed faster equipment, using new configurations, to manufacture parts that were almost impossible to machine in the past. Despite this tremendous evolution in machine and control technologies, the metalworking industry is still using the old ISO 6983 G-Codes programming interface to control the motion of these machines. This programming interface is not the most flexible or most appropriate for use by new open-architecture machine controllers and object-oriented high-level machining interfaces such as ISO 14649 (STEP-NC). This work proposes an innovative language, the ‘Base Numerical Control Language (BNCL),’ which is based on a low-level simple instruction set-like approach. The architecture is designed around two concepts: the BNCL virtual machine, which acts as a virtual microprocessor, and the BNCL virtual hardware, which is an abstraction of the machine tool. The language is characterised by its simplicity and flexibility, two qualities that are critical in a market in which the capabilities and performance of machines are constantly improving. The proposed architectural concepts are validated through various computer simulation and physical tests, including performance throughput, trajectory driving, and CNC controller extension capabilities.     

Agile enterprise architecture modelling: Evaluating the applicability and integration of six modelling standards

ContextAgile enterprise architecture artefacts are initially architected at the high-level and the details of those artefacts iteratively evolve in small project increments. There is a need to model agile enterprise architecture artefacts both at the high and low detailed level for a particular context. ArchiMate is relatively a new high-level architecture modelling standard. There is a growing interest amongst organisations in applying ArchiMate for high-level agile enterprise architecture modelling. However, organisations are unsure how to effectively apply ArchiMate at high-level and integrate it with their existing low detailed level modelling standards in practice for supporting end-to-end agile enterprise architecture modelling.ObjectiveThis paper evaluates the applicability and integration of high-level ArchiMate modelling standard with the existing low-level modelling standards such as BPMN (Business Process Model and Notation), UML (Unified Modelling Language), FAML (FAME [Framework for Agent-Oriented Method Engineering] Language), SoaML (Service Oriented Architecture Modelling Language), and BMM (Business Motivation Model).MethodA qualitative questionnaire-based evaluation criteria has been developed based on the well-known and comprehensive The Open Group Architecture Framework (TOGAF). The evaluation criteria has been applied to evaluate the applicability and integration of the selected six modelling standards from the business, application, infrastructure and extension perspectives.ResultsEach modelling standard is different in scope. A single modelling standard usually does not provide the kind of support required by the agile enterprise architecture modelling. Based on the review results, a hybrid enterprise architecture modelling approach is proposed. This paper demonstrates the application of the proposed hybrid approach with the help of an agile enterprise architecture modelling case study.ConclusionIt is concluded that the ArchiMate does not replace the existing low-level modelling standards, rather it can be used in conjunction with low-level modelling standards. This calls for the adoption of hybrid and integrated approach for agile enterprise architecture modelling.     

The Alamo Execution Monitor Architecture

Future programming environments will incorporate a tighter coupling between language runtime systems and the monitoring tools that are used to debug, tune, visualize, and understand them. Many innovations that are developed first in higher level programming language environments will migrate into mainstream languages once their properties are understood and generalized.

The Alamo execution monitor architecture was developed to facilitate rapid development of execution monitors, especially visualization tools that are instrumental in understanding complex runtime system interactions in higher level languages. Alamo simplifies the development of such tools by solving the low-level access, control, and intrusion problems inherent in monitoring.

Alamo was implemented first for the very high-level imperative goal-directed language Icon. The architecture was then implemented for ANSI C in order to broaden the impact of the work. This paper describes the ANSI C implementation of Alamo and the monitoring services it provides.     

Parallel-architecture-directed program transformation

The widespread use of parallel machines has been hampered by the difficulty of mapping applications onto them effectively. The difficulty arises because current programming languages require the programmer to specify a problem to be solved at a low level of abstraction in an imperative form. Thus the programmer must immediately encode an architecture-specific algorithm detailing every communication and calculation. This process is prone to error and complicates the reuse of software.

An alternative approach is to specify the problem to be solved at a high-level in a functional language. Meaning-preserving program transformations can then be used to derive a parallel algorithm. Such algorithms can be run on parallel graph-reduction or dataflow machines which automatically exploit the implicit parallelism in a functional language program. Such automatic decomposition techniques, however, are not yet capable of fully yielding the extra performance offered by the parallel hardware.

We show how, by including an architecture specification with the problem specification, and extending the amount of transformation performed, it is possible to produce functional language code that explicity expresses the calculations and communications to be performed by the processors. This simplifies compilation, yields faster programs and enables parallel software to be developed for a wide variety of parallel computer architectures.

A goal-seeking transformation methodology has been developed which enables a high-level functional specification of the problem and a high-level functional abstraction of the target computer architecture to be systematically manipulated to produce an efficient parallel algorithm tailored to the target architecture. As the transformations start from very high-level specifications, the discovery of new algorithms is facilitated.

A case study is used to demonstrate the effectiveness of the technique. We show how a high level specification for sort can be transformed with a pipeline architecture specification to give a mergesort and how the same specification with a dynamic-message-passing architecture specification can be transformed to a novel parallel quicksort.     

Optimal solutions for semantic image decomposition

Bridging the gap between low-level and high-level image analysis has been a central challenge in computer vision throughout the last decades. In this article I will point out a number of recent developments in low-level image analysis which open up new possibilities to bring together concepts of high-level and low-level vision. The key observation is that numerous multi‐label optimization problems can nowadays be efficiently solved in a near-optimal manner, using either graph-theoretic algorithms or convex relaxation techniques. Moreover, higher-level semantic knowledge can be learned and imposed on the basis of such multi‐label formulations.     

User-defined schedulers for real-time concurrent objects

Scheduling concerns the allocation of processors to processes, and is traditionally associated with low-level tasks in operating systems and embedded devices. However, modern software applications with soft real-time requirements need to control application-level performance. High-level scheduling control at the application level may complement general purpose OS level scheduling to fine-tune performance of a specific application, by allowing the application to adapt to changes in client traffic on the one hand and to low-level scheduling on the other hand. This paper presents an approach to express and analyze application-specific scheduling decisions during the software design stage. For this purpose, we integrate support for application-level scheduling control in a high-level object-oriented modeling language, Real-Time ABS, in which executable specifications of method calls are given deadlines and real-time computational constraints. In Real-Time ABS, flexible application-specific schedulers may be specified by the user, i.e., developer, at the abstraction level of the high-level modeling language itself and associated with concurrent objects at creation time. Tool support for Real-Time ABS is based on an abstract interpreter that supports simulations and measurements of systems at the design stage.     

M-nets: An algebra of high-level Petri nets, with an application to the semantics of concurrent programming languages

This paper describes a high-level Petri net model called M-nets (for modular multilabelled nets). A distinctive feature of this model is that it allows both: unfolding, as do most other high-level net models; and composition – in particular, synchronisation – in a process algebraic style, turning the set of M-nets into an algebraic domain. It turns out that the composition operations of this domain have various algebraic properties. Moreover, the model is such that composition operations are coherent with unfolding, in the sense that the unfolding of a composite high-level net is the composition of the unfoldings of its components. One of the motivations for M-nets is that they be a vehicle for giving semantics of concurrent programming languages. To illustrate their capability for that, the compositional semantics of – a simple, expressive concurrent programming language – is given. An associated low-level net semantics is described, and the coherence of these high-level and low-level semantics is proved. Received: 20 November 1996 / 13 January 1998     

Orthogonal multiprocessor sharing memory with an enhanced mesh for integrated image understanding

This paper proposes a new parallel architecture, which has the potential to support low-level image processing as well as intermediate and high-level vision analysis tasks efficiently. The integrated architecture consists of an SIMD mesh of processors enhanced with multiple broadcast buses, and MIMD multiprocessor with orthogonal access buses, and a two-dimensional shared memory array. Low-level image processing is performed on the mesh processor, while intermediate and high-level vision analysis is performed on the orthogonal multiprocessor. The interaction between the two levels is supported by a common shared memory. Concurrent computations and I/O are made possible by partitioning the memory into disjoint spaces so that each processor system can access a different memory space. To illustrate the power of such a two-level system, we present efficient parallel algorithms for a variety of problems from low-level image processing to high-level vision. Representative problems include matrix based computations, histogramming and key counting operations, image component labeling, pyramid computations, Hough transform, pattern clustering, and scene labeling. Through computational complexity analysis, we show that the integrated architecture meets the processing requirements of most image understanding tasks.