A 2D compact model for lightly doped DG MOSFETs (P-DGFETs) including negative bias temperature instability (NBTI) and short channel effects (SCEs)

In this paper, a 2D compact model for potential and threshold voltage for lightly doped symmetrical double gate (DG) p-channel MOSFETs (PMOS) including negative bias temperature instability (NBTI) and short channel effects (SCEs) is presented. The model is dedicated to nano scale MOSFETs below 30 nm. In this model, both effects of interface state generation and hole-trapping are considered. Moreover, the effects of scaling down the oxide thickness and the channel thickness on NBTI are discussed. Our model is matched very well with numerical simulations obtained from COMSOL multi-physics at different drain voltages (V_d). A 4% shift in threshold voltage roll-off and 47% shift in drain induced barrier lowering (DIBL) is achieved at a gate length of 10 nm after 10 years of operation at a frequency of 1 GHz.     

Model based precise analysis of the injection currents in Al/ZrO2/Al2O3/ZrO2/SiO2/Si structures for use in charge trapping non-volatile memory devices

Metal/insulator/Silicon (MIS) capacitors containing multilayered ZrO₂/Al₂O₃/ZrO₂/SiO₂ dielectric were investigated in order to evaluate the possibility of their application in charge trapping non-volatile memory devices. The ZrO₂/Al₂O₃/ZrO₂ stacks were deposited by reactive rf magnetron sputtering on 2.4 nm thick SiO₂ thermally grown on p-type Si substrate. C–V characteristics at room temperature and I–V characteristics recorded at temperatures ranging from 297 K to 393 K were analyzed by a comprehensive model previously developed. It has been found that Poole-Frenkel conduction in ZrO₂ layers occurs via traps energetically located at 0.86 eV and 1.39 eV below the bottom of the conduction band. These levels are identified as the first two oxygen vacancies related levels in ZrO₂, closest to its conduction band edge, whose theoretical values reported in literature are: 0.80 eV, for fourfold, and 1.23 eV, for threefold coordinated oxygen vacancies.     

The optimum fin width in p-MuGFETs with the consideration of NBTI and hot carrier degradation

Generally it is known that NBTI degradation increases with decrease of a channel width in p-MOSFETs but hot carrier degradation decreases. In this work, a guideline for the optimum fin width in p-MuGFETs is suggested with consideration of NBTI and hot carrier degradation. Using the device lifetime defined as the stress time necessary to reach ΔV_TH = 10 mV, the optimum fin widths have been extracted for different stress voltages and temperatures. When a fin width is narrower than the optimum fin width, the device lifetime is governed by the NBTI degradation. However, when fin width is wider than the optimum fin width, the device lifetime is dominantly governed by hot carrier degradation. The optimum fin width decreases with the increase of the stress voltage but it increases with the increase of the stress temperature.     

Degradation of pMOSFETs due to hot electron induced punchthrough

This paper proposes a method which can separate the parasitic effect from the drain current I_d vs. gate voltage V_g curves of MOSFETs, then uses this method to analyze degradation of experimental pMOSFETs due to hot-electron-induced punchthrough (HEIP). An I_d vs. V_g curve of the parasitic MOSFET formed by a shallow trench isolation (STI) is obtained by extrapolating the line of I_d vs. channel width W at each V_g to W = 0 μm. The I_d vs. V_g curves of the parasitic MOSFET indicate that HEIP caused electron trapping at the interface between SiN and the sidewall oxide of STI, but the curves of the main MOSFET indicate that HEIP caused negative oxide charges and positive interface traps in the channel region. These charges and traps decreased the threshold voltage V_th of the parasitic MOSFET but increased V_th of the main MOSFET. These two opposite behaviors of V_th resulted in little HEIP-induced shift of V_th at W = 2.5 μm. | V_d | to secure ten-year HEIP lifetime of 10% shift of V_th was ≤ 2.2 V at W = 0.3 μm, ≤ 3.5 V at W = 1.0 μm, and ≤ 3.6 V at W = 10 μm; these changes indicate that degradation of parasitic MOSFET influences the HEIP lifetime of narrow pMOSFET significantly.     

Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI

In this study, we integrate and compare the electrical performances of metal/high-K embedded gates in 3D multi-channel CMOSFETs (MCFETs) on SOI. The electrical characteristics of embedded gates obtained by filling cavities with TiN/HfO₂, TiN/SiO₂ or N⁺ poly-Si/SiO₂ are compared to a planar reference. In particular, we investigate electron and hole mobility behaviours (300 K down to 20 K) in embedded and planar structures, the gate leakage current and the negative bias temperature instability (NBTI). Despite a lower mobility, TiN/HfO₂ gate stack demonstrates the best I_ON/I_OFF compromise and exhibits NBTI life time higher than 10 years up to 1.3 V.     

Operational frequency degradation induced trapping in scaled GaN HEMTs

Cut-off frequency increase from 12.1 GHz to 26.4 GHz, 52.1 GHz and 91.4 GHz is observed when the 1 μm gate length GaN HEMT is laterally scaled down to L_G = 0.5 μm, L_G = 0.25 μm and L_G = 0.125 μm, respectively. The study is based on accurately calibrated transfer characteristics (I_D-V_GS) of the 1 μm gate length device using Silvaco TCAD. If the scaling is also performed horizontally, proportionally to the lateral (full scaling), the maximum drain current is reduced by 38.2% when the gate-to-channel separation scales from 33 nm to 8.25 nm. Degradation of the RF performance of a GaN HEMT due to the electric field induced acceptor traps experienced under a high electrical stress is found to be about 8% for 1 μm gate length device. The degradation of scaled HEMTs reduces to 3.5% and 7.3% for the 0.25 μm and 0.125 gate length devices, respectively. The traps at energy level of E_T = E_V + 0.9 eV (carbon) with concentrations of N_IT = 5 × 10¹⁶cm^− 3, N_IT = 5 × 10¹⁷cm^− 3 and N_IT = 5 × 10¹⁸cm^− 3 are located in the drain access region where highest electrical field is expected. The effect of traps on the cut-off frequency is reduced for devices with shorter gate lengths down to 0.125 μm.     

Effect of interface traps for ultra-thin high-k gate dielectric based MIS devices on the capacitance-voltage characteristics

The impact of states at the Al₂O₃/Si interface on the capacitance-voltage C-V characteristics of a metal/insulator/semiconductor heterostructure (MIS) capacitor was studied by a numerical simulation, by solving Schrodinger-Poisson equations and taking the electron emission rate from the interface state into account. Efficient computation and accurate physics based capacitance model of MOS devices with advanced ultra-thin equivalent oxide thickness (EOT) (down to 2.5 nm clearly considered here) were introduced for the near future integrated circuit IC technology nodes. Due to the importance of the interface state density for a low dimension and very low oxide thickness, a high frequency C-V model has been developed to interpret the effect of interface state density traps which communicate with the Al₂O₃/Si and their influence on the C-V characteristics. We found that these states are manifested by jumping capacity in the inversion zone, for a density of interface, higher than 1 × 10¹¹ cm^− 2 eV^− 1 during a p-doping of 1 × 10¹⁸ cm^− 3. This behavior has been investigated with various doping, temperature, frequency and energy levels on the C-V curves, and compared with the MIS structure that contains a standard SiO₂ insulator.     

MISFET structures with barium titanate as a dielectric layer for application in memory cells

This work shows investigations of La₂O₃ containing BaTiO₃ thin films deposited on Si substrates by Radio Frequency Plasma Sputtering (RF PS) of sintered BaTiO₃ + La₂O₃ (2 wt.%) target. Round, aluminum (Al) electrodes were evaporated on top of the deposited layers. Thus, metal–insulator–semiconductor (MIS) structures were created with barium titanate thin films playing the role of an insulator. The MIS structures enabled a subsequent electrical characterization of the studied film by means of current–voltage (I–V) and capacitance–voltage (C–V) measurements. Several electronic parameters, i.e., ε_ri, ρ, V_FB, ΔV_H were extracted from the obtained characteristics. Moreover, the paper describes technology process of MISFETs fabrication and possibility of their application as memory cells. The influence of voltage stress on transfer and output I–V characteristics of the transistors are presented and discussed.     

Fabrication of the flexible pentacene thin-film transistors on 304 and 430 stainless steel (SS) substrate

Flexible organic thin-film transistors (OTFT) were fabricated on 304 and 430 stainless steel (SS) substrate with aluminum oxide as a gate insulator and pentacene as an organic semiconductor. Chemical mechanical polishing (CMP) process was used to study the effect of the SS roughens on the dielectric properties of the gate insulator and OTFT characteristics. The surface roughness was decreased from 33.8 nm for 304 SS and 19.5 nm for 430 SS down to ～2.5 nm. The leakage current of the metal–insulator–metal (MIM) structure (Au/Al₂O₃/SS) was reduced with polishing. Mobility and on/off ratio of pentacene TFT with bare SS showed a wide range of values between 0.005 and 0.36 cm²/Vs and between 10³ and 10⁵ depending on the location in the substrate. Pentacene TFTs on polished SS showed an improved performance with a mobility of 0.24–0.42 cm²/Vs regardless of the location in the substrate and on/off ratio of ～10⁵. With self assembled monolayer formation of octadecyltrichlorosilane (OTS) on insulator surface, mobility and on/off ratio of pentacene TFT on polished SS was improved up to 0.85cm²/Vs and ～10⁶. I–V characteristics of pentacene TFT with OTS treated Al₂O₃/304 SS was also obtained in the bent state with a bending diameter (D) of 24, 45 or 70 mm and it was confirmed that the device performed well both in the linear regime and the saturation regime.     

Interface states in polyfluorene-based metal–insulator–semiconductor devices

Hybrid metal–insulator–semiconductor structures based on ethyl-hexyl substituted polyfluorene (PF2/6) as the active polymer semiconductor were fabricated on a highly doped p-Si substrate with Al₂O₃ as the insulating oxide layer. We present detailed frequency-dependent capacitance–voltage (C–V) and conductance–voltage characteristics of the semiconductor/insulator interface. PF2/6 undergoes a transition to an ordered crystalline phase upon thermal cycling from its nematic-liquid crystalline phase, confirmed by our atomic force microscope images. Thermal cycling of the PF2/6 films significantly improves the quality of the (PF2/6)/Al₂O₃ interface, which is identified as a reduced hysteresis in the C–V curve and a decreased interface state density (D_it) from ∼3.9 × 10¹² eV⁻¹ cm⁻² to ∼3.3 × 10¹¹ eV⁻¹ cm⁻² at the flat-band voltage. Interface states give rise to energy levels that are confined to the polymer/insulator interface. A conductance loss peak, observed due to the capture and emission of carriers by the interface states, fits very well with a single time constant model from which the D_it values are inferred.     

Electrical characterization and TCAD simulations of multi-gate bulk nMOSFET

A multi-gate nMOSFET in bulk CMOS process has been fabricated by integration of polysilicon-filled trenches. We have simulated its electrical characteristics by using TCAD software and compared them with results obtained from electrical measurements. The threshold voltage and the subthreshold slope of the top gate have been extracted and we found a good accordance, for both parameters, between the measurements (V_TH=0.59 V, S=90 mV/dec) and simulations (V_TH=0.50 V, S=92 mV/dec). The surface channel effective mobility of this multi-gate MOSFET was extracted and evaluated with both effective length and surface. The studies revealed that mobility degraded towards smaller dimensions of the MOS channel. At last, the Si/SiO₂ interface quality studies were carried out. We noticed that the injected donor traps have a larger influence on the current–voltage characteristics than acceptor-like traps. With its good electrical performances, this low-cost multi-gate MOSFET technology presents interesting perspective in CMOS image sensors and more generally in analog application taking benefit of the multi-threshold for example.     

Effect of the work function of gate electrode on hysteresis characteristics of organic thin-film transistors with Ta2O5/polymer as gate insulator

Organic thin-film transistors (OTFTs) using high dielectric constant material tantalum pentoxide (Ta₂O₅) and benzocyclobutenone (BCBO) derivatives as double-layer insulator were fabricated. Three metals with different work function, including Al (4.3 eV), Cr (4.5 eV) and Au (5.1 eV), were employed as gate electrodes to study the correlation between work function of gate metals and hysteresis characteristics of OTFTs. The devices with low work function metal Al or Cr as gate electrode exhibited high hysteresis (about 2.5 V threshold voltage shift). However, low hysteresis (about 0.7 V threshold voltage shift) OTFTs were attained based on high work function metal Au as gate electrode. The hysteresis characteristics were studied by the repetitive gate voltage sweep of OTFTs, and capacitance–voltage (C–V) and trap loss-voltage (G_p/ω?V) measurements of metal–insulator–semiconductor (MIS) devices. It is proved that the hysteresis characteristics of OTFTs are relative to the electron injection from gate metal to Ta₂O₅ insulator. The electron barrier height between gate metal and Ta₂O₅ is enhanced by using Au as gate electrode, and then the electron injection from gate metal to Ta₂O₅ is reduced. Finally, low hysteresis OTFTs were fabricated using Au as gate electrode.     

Structural and electrical properties of Pr1−xSrxMnO3 (x=0.25, 0.3, 0.35 and 0.4) manganites

In this work, we have studied the structural features and electrical conductivity of the polycrystalline Pr_1−xSr_xMnO₃ (x=0.25, 0.3, 0.35, 0.4) manganites. All the compounds have orthorhombic structure with space group Pbnm. The electrical resistivity of all the samples exhibits metal–insulator transition T_MI for both H=0 T and H=8 T. At H=8 T, ρ (T) drops down considerably which indicates the existence of the CMR effect. The electron–phonon, electron–electron and electron–spin fluctuation interactions are effective to describe the resistivity behavior for temperature less than the metal–insulator transition (T_MI). For temperatures, T>T_MI, the insulating nature is discussed with a small polaron conduction (SPC) model. The resistivity of all the samples shows a field-dependent minimum at low temperature. The above is due to the Coulomb interaction between carriers strongly enhanced by disorder and Kondo-like spin dependent scattering.     

Fabrication of NbN/AlN/NbN junctions with Al embedding circuits on Si membrane for 1.5 THz SIS mixers

A process has been developed to fabricate NbN tunnel junctions and 1.5 THz SIS mixers with Al electrodes and Al/SiO₂/Al microstrip tuning circuits on thin Si membranes patterned on silicon on insulator wafers (SIMOX). High Josephson current density (J_c up to 2×10⁴ A/cm²) NbN/AlN/NbN and NbN/MgO/NbN SIS junctions have been fabricated with a reasonably good V_m quality factor and energy gap values close to 5 meV at 4.2 K on (100) oriented 3 inches SIMOX wafers covered by a thin (∼8 nm) MgO buffer layer. The sputtering conditions critically influence the dielectric quality of both AlN and MgO tunnel barriers as well as the surface losses of NbN electrodes. 0.6-μm Si/SiO₂ membranes are obtained after processing of a whole wafer and etching the individual chips in EDP. Such a technology is applied to the development of a waveguide/membrane SIS mixer for use around 1.5 THz.     

The effect of oxide layer thickness on the quantification of 1.5 MeV γ–radiation induced interface traps in the Ag/SiO2/Si MOS devices

This work presents the effect of varied thickness of oxide layer and radiation dose on electrical characteristics of Ag/SiO₂/Si MOS devices irradiated by 1.5 MeV γ–radiations of varied doses. SiO₂ layers of 50, 100, 150 and 200 nm thickness were grown on Si substrates using dry oxidation and exposed to radiation doses of 1, 10 and 100 kGy. The exposure to radiation resulted in generation of fixed charge centers and interface traps in the SiO₂ and at the Si/SiO₂ interface. Capacitance-conductance-voltage (C-G-V) and capacitance-conductance-frequency (C-G-f) measurements were performed at room temperature for all MOS devices to quantify the active traps and their lifetimes. It is shown that accumulation and minimum capacitances decreased as the thickness of SiO₂ layer increased. For the unexposed MOS devices, the flat band voltage V_FB decreased at a rate of −0.12 V/nm, density of active traps increased by 4.5 times and depletion capacitance C_DP, increased by 2.5 times with the increase of oxide layer thickness from 50 to 200 nm. The density of active traps showed strong dependence on the frequency of the applied signal and the thickness of the oxide layer. The MOS device with 200 nm thick oxide layer irradiated with 100 kGy showed density of active interface traps was high at 50 kHz and was 3.6×10¹⁰ eV⁻¹ cm⁻². The relaxation time of the interface traps also increased with the exposure of γ–radiation and reached to 9.8 µs at 32 kHz in 200 nm thick oxide MOS device exposed with a dose of 100 kGy. It was inferred that this was due to formation of continuum energy states within the band gap and activation of these defects depended on the thickness of oxide layer, applied reverse bias and the working frequency. The present study highlighted the role of thickness of oxide layer in radiation hard environments and that only at high frequency, radiation induced traps remain passivated due to long relaxation times.     

Organic thin film transistors with double insulator layers

We have investigated a double-layer structured gate dielectric for the organic thin films transistor (OTFT) with the purpose of improving the performance of the SiO₂ gate insulator. A 50 nm PMMA layer was coated on top of the SiO₂ gate insulator as organic insulator layer. The results demonstrated that using inorganic/organic compound insulator as the gate dielectric layers is an effective method to fabricate OTFTs with improved electric characteristics and decreased leakage current. Electrical parameters such as carrier mobility and on/off ratio by field effect measurement have been calculated. OTFT based on highly doped Si substrate with a field-effect mobility of 0.004 cm²/V s and on/off ratio of 10⁴ have been obtained.     

New insight on negative bias temperature instability degradation with drain bias of 28 nm High-K Metal Gate p-MOSFET devices

The degradation of negative bias temperature instability (NBTI) on 28 nm High-K Metal Gate (HKMG) p-MOSFET devices under non-uniform stress condition has been systematically studied. We found the asymmetry between forward and reverse Idsat shift under non-uniform stress condition is significant for long channel devices even under low drain bias stress (e.g., Vds = −0.1 V and gate channel length L = 1 μm), and seems to be dominated by a minimally required critical length (L = 0.2 μm derived from the experimental data). To the authors’ best knowledge, these are new phenomena reported. We attribute these anomalous NBTI characteristics with drain bias to the local self-heating (LSH) activated NBTI degradation mechanism. One semi-empirical analytical model, which fits well with our experimental data, is then proposed in this paper.     

Photo-electrochemical characterization of porous material Fe-FSM-16. Application for hydrogen production

We describe in the present work the photo-electrochemical characterization of iron/folded-sheets mesoporous materials (Fe-FSM-16, Si/Fe=60) synthesized by microwave-assisted hydrothermal (M-H) method and its application for the hydrogen evolution upon visible light. The mesoporous catalyst consists of small Fe₂O₃ particles (～2 nm) spread on SiO₂ with specific surface area of ～800 m² g^?1. The capacitance measurements reveal an iron deficiency and the oxide exhibit p type conductivity with activation energy of 0.07 eV. The optical gap of the hematite (α-Fe₂O₃) is evaluated at 3.24 eV from the diffuse reflectance spectrum. The flat band potential V_fb (?0.54 V_SCE) and the holes density N_D (9.56×10¹⁴ cm^?3) of the hematite are obtained respectively by extrapolating the linear part to C^?2=0 and the slope of the Mott Schottky plot. At pH=7, the conduction band (?0.47 V_SCE) is suitably positioned with respect to the H₂O/H₂ level (?0.59 V_SCE) leading to a spontaneous water reduction. The oxide is stabilized by hole consumption involving SO₃^2? and S₂O₃^2? species and spectacular improvement of the hydrogen evolution is reported with evolution rates of ～461 and 163 μ mol respectively.     

Low-voltage,high speed inkjet-printed flexible complementary polymer electronic circuits

We report the development of high-performance inkjet-printed organic field-effect transistors (OFETs) and complementary circuits using high-k polymer dielectric blends comprising poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) and poly(methyl methacrylate) (PMMA) for high-speed and low-voltage operation. Inkjet-printed p-type polymer semiconductors containing alkyl-substituted thienylenevinylene (TV) and dodecylthiophene (PC12TV12T) and n-type P(NDI2OD-T2) OFETs showed high field-effect mobilities of 0.1–0.4 cm² V^?1 s^?1 and low threshold voltages down to 5 V. These OFET properties were modified by changing the blend ratio of P(VDF-TrFE) and PMMA. The optimum blend – a 7:3 wt% mixture of P(VDF-TrFE) and PMMA – was successfully used to realize high-performance complementary inverters and ring oscillators (ROs). The complementary ROs operated at a supplied bias (V_DD) of 5 V and showed an oscillation frequency (f_osc) as high as ～80 kHz at V_DD = 30 V. Furthermore, the f_osc of the complementary ROs was significantly affected by a variety of fundamental parameters such as the electron and hole mobilities, channel width and length, capacitance of the gate dielectrics, V_DD, and the overlap capacitance in the circuit configuration.     

High-performance diketopyrrolopyrrole-based organic field-effect transistors for flexible gas sensors

We demonstrate high-performance flexible polymer OFETs with P-29-DPP-SVS in various geometries. The mobilities of TG/BC OFETs are approximately 3.48 ± 0.93 cm²/V s on a glass substrate and 2.98 ± 0.19 cm²/V s on a PEN substrate. The flexible P-29-DPP-SVS OFETs exhibit excellent ambient and mechanical stabilities under a continuous bending stress of 1200 times at an R = 8.3 mm. In particular, the variation of μ_FET, V_Th and leakage current was very negligible (below 10%) after continuous bending stress. The BG/TC P-29-DPP-SVS OFETs on a PEN substrate applies to flexible NH₃ gas sensors. As the concentration of NH₃ increased, the channel resistance of P-29-DPP-SVS OFETs increased approximately 100 times from ∼10⁷ to ∼10⁹ Ω at V_SD = −5 V and V_GS = −5 V.