Non-conductive film with Zn-nanoparticles (Zn-NCF) for 40 μm pitch Cu-pillar/Sn–Ag bump interconnection

Non-conductive film with Zn nano-particles (Zn-NCF) is an effective solution for fine-pitch Cu-pillar/Sn–Ag bump interconnection in terms of manufacturing process and interfacial reliability. In this study, NCFs with Zn nano-particles of different acidity, viscosity, and curing speed were formulated and diffused Zn contents in the Cu pillar/Sn–Ag bumps were measured after 3D TSV chip-stack bonding. Amount of Zn diffusion into the Cu pillar/Sn–Ag bumps increased as the acidity of resin increased, as the viscosity of resin decreased, as the curing speed of resin decreased, and as the bonding temperature increased. Diffusion of Zn nano-particles into the Cu pillar/Sn–Ag bumps are maximized when the resin viscosity became lowered and the solder oxide layer was removed. To analyze the effects of Zn-NCF on IMC reduction, IMC height depending on aging time was measured and corresponding activation energies for IMC growth were calculated. For the evaluation of joint reliabilities, test vehicles were bonded using NCFs with 0 wt%, 1 wt%, 5 wt%, and 10 wt% of Zn nano-particles and aged at 150 °C up to 500 h. NCF with 10 wt% Zn nano-particle showed remarkable suppression in Cu₆Sn₅ and (Cu,Ni)₆Sn₅ IMC compared to NCFs with 0 wt%, 1 wt%, and 5 wt% of Zn nano-particles. However, in terms of Cu₃Sn IMC suppression, which is the most critical goal of this experiment NCFs with 1 wt%, 5 wt%, and 10 wt% showed an equal amount of IMC suppression. As a result, it was successfully demonstrated that the suppression of Cu–Sn IMCs was achieved by the addition of Zn nano-particles in the NCFs resulting an enhanced reliability performance in the Cu/Sn–Ag bumps bonding in 3D TSV interconnection.     

High cycle fatigue behaviour and generalized fatigue model development of lead-free solder alloy based on local stress approach

This paper gives an insight into high cycle fatigue (HCF) behaviour of a Pb-free solder alloy in the region between 10⁴ up to 10⁹ fatigue cycles using fatigue specimen. By means of a local stress approach, the method can be translated into solder joint fatigue evaluation in an application. The effect of temperatures (35 °C, 80 °C, 125 °C) on the fatigue property of Pb-free solder alloy is considered in this work to understand the possible fracture mechanisms and micro structural changes in a solder alloy at elevated temperature. Experiments are performed for different interaction factors under mean stresses (R = 0, − 1, − 3), stress concentration (notched, un-notched) and surface roughness. SN (stress-life) diagrams presented in this work will compare the fatigue performance of Sn_3.8Ag_0.7Cu solder alloy for different conditions. Furthermore, mathematical fatigue model based on FKM guideline (in German “Fachkuratorium Maschinenbau) is extracted out of the experiments under all these external effects. The models can be exported later for lifetime evaluation purposes on applications. The paper thereby proposes the use of FKM guideline in the field of microelectronics.     

Effect of elevated temperature on PCB responses and solder interconnect reliability under vibration loading

In this paper, vibration tests are conducted to investigate the influence of temperature on PCB responses. A set of combined tests of temperature and vibration is designed to evaluate solder interconnect reliability at 25 °C, 65 °C and 105 °C. Results indicate that temperature significantly affects PCB responses, which leads to remarkable differences in vibration loading intensity. The PCB eigenfrequency shifts from 290 Hz to 276 Hz with an increase of test temperature from 25 °C to 105 °C, during which the peak strain amplitude is almost the same.Vibration reliability of solder interconnects is greatly improved with temperature rise from 25 °C to 105 °C. Mean time to failure (MTTF) of solder joint at 65 °C and 105 °C is increased by 70% and 174% respectively compared to that of solder joint at 25 °C. Temperature dominates crack propagation path of solder joint during vibration test. Crack propagation path is changed from the area between intermetallic compound (IMC) layer and Cu pad to the bulk solder with temperature increase.     

Investigation on thermal fatigue of SnAgCu,Sn100C,and SnPbAg solder joints in varying temperature environments

Thermal cycling tests have been performed for a range of electronic components intended for avionic applications, assembled with SAC305, SN100C and SnPbAg solder alloys. Two temperature profiles have been used, the first ranging between −20 °C and +80 °C (TC1), and the second between −55 °C and +125 °C (TC2). High level of detail is provided for the solder alloy composition and the component package dimensions, and statistical analysis, partially supported by FE modeling, is reported. The test results confirm the feasibility of SAC305 as a replacement for SnPbAg under relatively benign thermomechanical loads. Furthermore, the test results serve as a starting point for estimation of damage accumulation in a critical solder joint in field conditions, with increased accuracy by avoiding data reduction. A computationally efficient method that was earlier introduced by the authors and tested on relatively mild temperature environments has been significantly improved to become applicable on extended temperature range, and it has been applied to a PBGA256 component with SAC305 solder in TC1 conditions. The method, which utilizes interpolated response surfaces generated by finite element modeling, extends the range of techniques that can be employed in the design phase to predict thermal fatigue of solder joints under field temperature conditions.     

Flexible Chip-on-Flex (COF) and embedded Chip-in-Flex (CIF) packages by applying wafer level package (WLP) technology using anisotropic conductive films (ACFs)

Due to increasing demand for higher performance, greater flexibility, smaller size, and lighter weight in electronic devices, extensive studies on flexible electronic packages have been carried out. However, there has been little research on flexible packages by wafer level package (WLP) technology using anisotropic conductive films (ACFs) and flex substrates, an innovative packaging technology that requires fewer process steps and lower process temperature, and also provides flexible packages. This study demonstrated and evaluated the reliability of flexible packages that consisted of a flexible Chip-on-Flex (COF) assembly and embedded Chip-in-Flex (CIF) packages by applying a WLP process.The WLP process was successfully performed for the cases of void-free ACF lamination on a 50 μm thin wafer, wafer dicing without ACF delamination, and a flip-chip assembly which showed stable bump contact resistances. The fabricated COF assembly was more flexible than the conventional COF whose chip thickness is about 700 μm. To evaluate the flexibility of the COF assembly, a static bending test was performed under different bending radiuses: 35 mm, 30 mm, 25 mm, and 20 mm. Adopting optimized bonding processes of COF assembly and Flex-on-Flex (FOF) assembly, CIF packages were then successfully fabricated. The reliability of the CIF packages was evaluated via a high temperature/humidity test (85 °C/85% RH) and high temperature storage test (HTST). From the reliability test results, the CIF packages showed excellent 85 °C/85% RH reliability. Furthermore, guideline of ACF material property was suggested by Finite Element Analysis (FEA) for better HTST reliability.     

Vertical InGaN light-emitting diodes with Ag paste as bonding layer

Vertical InGaN-based light-emitting diodes (LEDs) were fabricated with a Si substrate using Ag paste as bonding layer. Vertical LEDs with Ag paste bonding layer were bonded with Si substrate at a low temperature of 140 °C. In addition to the low-temperature bonding process, the soft property of Ag paste could better alleviate thermal stress compared with conventional eutectic metal bonding layer such as Au–Sn. Under the same test conditions, these two LEDs showed similar optical and electrical properties and reliability. However, LEDs with Ag-paste bonding layer were fabricated through a low-temperature bonding process. The characteristic of soft solder enables a relatively wider process window, such as bonding pressure and temperature, and a higher yield as compared with the vertical LEDs with Au–Sn eutectic bonding layer.     

Fabrication of nano-sized resist patterns on flexible plastic film using thermal curing nano-imprint lithography

Due to polymer’s excellent flexibility, transparency, reliability and light weight, it is a good candidate material for substrate of devices including organic electronic devices, biomedical devices, and flexible displays (LCD and OLED). In order to build such devices on polymer, nano- to micron-sized patterning must be accomplished. Since polymer materials reacts with organic solvents or developer solutions which are inevitably used in photolithography and cannot bear high temperature (∼140 °C) process for photoresist baking, conventional photolithography cannot be used to polymer substrate. In this research, monomer based thermal curing imprinting lithography was used to make as small as 100 nm dense line and space patterns on flexible PET (polyethylene-terephthalate) film. Compared to hot embossing lithography, monomer based thermal curing imprint lithography uses monomer based imprint resin which consists of base monomer and thermal initiator. Since it is liquid phase at room temperature and polymerization can be initiated at 85 °C, which is much lower than glass temperature of polymer resin, the pattern transfer can be done at much lower temperature and pressure. Hence, patterns as small as 100 nm were successfully fabricated on flexible PET film substrate by monomer based thermal curing imprinting lithography at 85 °C and 5 atm without any noticeable degradation of PET substrate.     

Interfacial behaviors of Sn-Pb,Sn-Ag-Cu Pb-free and mixed Sn-Ag-Cu/Sn-Pb solder joints during electromigration

SnPb-SnAgCu mixed solder joints with Sn-Pb soldering Sn-Ag-Cu Pb-free components are inevitably occurred in the high reliability applications. In this study, the interfacial behaviors in Sn-37Pb and Sn-3.0Ag-0.5Cu mixed solder joints was addressed and compared with Sn-37Pb solder joints and Sn-3.0Ag-0.5Cu solder joints with the influence from isothermal aging and electromigration. Considering the difference on the melting point between Sn-3.0Ag-0.5Cu and Sn-37Pb solder, two mixed solder joints: partial mixing and full mixing between Sn-Pb and Sn-Ag-Cu solders were reached with the peak reflowing temperature of 190 and 250 °C, respectively. During isothermal aging, the intermetallic compound (IMC) layer increased with aging time and its growth was diffusion controlled. There was also no obvious affect from the solder composition on IMC growth. After electromigration with the current density of 2.0 × 10³ A/cm², Sn-37Pb solder joints showed the shortest lifetime with the cracks observed at the cathode for the stressing time < 250 h. In Sn-3.0Ag-0.5Cu Pb-free solder joints, current stressing promoted the growth of IMC layer at the interfaces, but the growing rate of IMC at the anode interface was far faster than that at the cathode interface. Therefore, there existed an obvious polarity effect on IMC growth in Sn-Ag-Cu Pb-free solder joints. After Sn-37Pb was mixed with Sn-3.0Ag-0.5Cu Pb-free solder, whether the partial mixing or the full mixing between Sn-Pb and Sn-Ag-Cu can obviously depress both the crack formation at the cathode side and the IMC growth at the anode.     

High temperature ageing of microelectronics assemblies with SAC solder joints

In some applications, electronic systems are expected to operate at high ambient temperature (e.g. 150 °C). In this paper, we investigate the failure mechanism and microstructure evolution of solder-free (SAC) solder joints at a maximum temperature of 175 °C. It is found that no new failure mechanisms are triggered, and that ageing tests for solder can be accelerated at 175 °C. In particular, the growth rate of the interfacial intermetallic compound (IMC) is found to be consistent with that observed at lower temperatures.     

Discrete phase method particle simulation of ultra-fine package assembly with SAC305-TiO2 nano-reinforced lead free solder at different weighted percentages

This paper presents a 3D numerical simulation of nano-reinforced lead (Pb)-free solder at the ultra-fine joint component for 01005 capacitor with dimension of 0.2 × 0.2 × 0.4 mm³. The nano-reinforced particles introduced in the Sn-3.0Ag-0.5Cu (SAC305) solder is titanium oxide (TiO₂) nanoparticles with approximate diameter of ≈ 20 nm at different weight percentages of 0.01, 0.05 and 0.15 wt% respectively. The 3D model developed is based on the reflow thermal profile of nano-reinforced Pb-free solder in the wetting zone temperature of 217 °C–239 °C. A two way interactions utilizing both volume of fluid method (VOF) and discrete phase method (DPM) are introduced in the current study. The study effectively shows the distribution of the nanoparticles as it is being doped in the molten solder after undergoing soldering process. Based on the findings, it was shown that good agreement can be seen between experimental data obtained using High Resolution Transmission Electron Microscope (HRTEM) system as compared to multiphase DPM based simulation. At weight percentage of SAC305 + 0.05% TiO₂ nanoparticles, the nanoparticles are well distributed. The fillet height of nano-reinforced solder also meets the minimum requirement for 01005 capacitor. Additionally, as the weight percentage of the doped nanoparticles increases, the time required for the formation of wetted solder also increases. In terms of the velocity and pressure distribution of the nano-reinforced lead (Pb)-free solder, higher weight percentage of doped nanoparticles have higher velocity distribution and lower pressure distributions.     

Studies on various chip-on-film (COF) packages using ultra fine pitch two-metal layer flexible printed circuits (two-metal layer FPCs)

Various fine pitch chip-on-film (COF) packages assembled by (1) anisotropic conductive film (ACF), (2) nonconductive film (NCF), and (3) AuSn metallurgical bonding methods using fine pitch flexible printed circuits (FPCs) with two-metal layers were investigated in terms of electrical characteristics, flip chip joint properties, peel adhesion strength, heat dissipation capability, and reliability. Two-metal layer FPCs and display driver IC (DDI) chips with 35 μm, 25 μm, and 20 μm pitch were prepared. All the COF packages using two-metal layer FPCs assembled by three bonding methods showed stable flip chip joint shapes, stable bump contact resistances below 5 mΩ, good adhesion strength of more than 600 gf/cm, and enhanced heat dissipation capability compared to a conventional COF package using one-metal layer FPCs. A high temperature/humidity test (85 °C/85% RH, 1000 h) and thermal cycling test (T/C test, ?40 °C to + 125 °C, 1000 cycles) were conducted to verify the reliability of the various COF packages using two-metal layer FPCs. All the COF packages showed excellent high temperature/humidity and T/C reliability, however, electrically shorted joints were observed during reliability tests only at the ACF joints with 20 μm pitch. Therefore, for less than 20 μm pitch COF packages, NCF adhesive bonding and AuSn metallurgical bonding methods are recommended, while all the ACF and NCF adhesives bonding and AuSn metallurgical bonding methods can be applied for over 25 μm pitch COF applications. Furthermore, we were also able to demonstrate double-side COF using two-metal layer FPCs.     

Evaluation of hybrid bonding technology of single-micron pitch with planar structure for 3D interconnection

In this paper, we describe hybrid bonding technology of single-micron pitch with planar structure for three-dimensional (3D) interconnection. Conventionally, underfill method utilizing capillary force was used after the bonding of microbump. However, the filling becomes insufficient in a gap less than 10 μm between chips or bumps. One promising technology is the hybrid bonding technology that microbumps and an adhesive can be simultaneously bonded. To realize a single-micron pitch hybrid bonding, we fabricated a planar structure that consists of 8 μm-pitch Cu/Sn microbumps and a non-conductive film (NCF) by a chemical mechanical polishing (CMP) of resin. After planarization, the Cu/Sn bumps and the NCF were simultaneously bonded at 250 °C for 60 s. Cross-sectional scanning electron microscope (SEM) images and energy dispersive X-ray spectroscopy (EDX) images show that the adhesive resin on the bump surface was successfully removed by the CMP. In addition, SEM images of the bonded sample show that the adhesive filled the 2.5-μm gap between the chip and substrate. The Cu/Sn bumps were properly bonded in a corner on the chip. The proposed bonding method is expected to enable single-micron pitch interconnection for ultra-high density 3D LSI of next generation.     

Comparative studies on microelectronic reliability issue of Sn whisker growth in Sn-0.3Ag-0.7Cu-1Pr solder under different environments

In this study, comparative studies on Sn whisker growth in Sn-0.3Ag-0.7Cu-1Pr solder under different environments were conducted to investigate factors like ambient temperature, oxygen level, and 3.5 wt% NaCl solution on whisker growth. The experimental results revealed that ambient temperature and oxygen level are two important factors that could determine the oxidation rate of PrSn₃ phase, thus indirectly affecting the growth rate of Sn whiskers. In addition, mechanisms of whisker growth under these three environments were established from the perspective of atom diffusion based on the “compressive stress-induced” theory. Although whiskers under different environments were all squeezed out from Pr oxides (hydroxides), the forms of their driving forces were different. For whiskers squeezed out in air whether at room temperature or 150 °C, the driving force is the compressive stress produced by lattice expansion due to the oxidation of PrSn₃ phase. The representative example was whiskers' growth at 150 °C, which could be simplified as three stages: (1) squeezing out, (2) cracking and (3) bursting out. For whisker growth in 3.5 wt% NaCl solution, the driving force for much fewer whiskers' growth was proposed to come from lateral stress provided by interfacial IMC layer growth. Moreover, Sn nanoparticles and their agglomerations were also found to form under the driving force of the potential difference between Sn atoms and Sn crystals. Their morphologies could also be affected by factors of ambient temperature, oxygen level and Cl⁻ ions in corrosive liquid.     

Consideration of temperature and current stress testing on flip chip solder interconnects

This work discusses the experimental set-up and data interpretation for high temperature and current stress tests of flip chip solder joints using the four-point Kelvin measurement technique. The single solder joint resistance responses are measured at four different four-point Kelvin structure locations in a flip chip package. Various temperatures (i.e., 125–165 °C) and electric current (i.e., 0.6–1.0 A) test conditions are applied to investigate the solder joint resistance degradation behavior and its failure processes. Failure criterion of 20% and 50% joint resistance increases, corresponding to solder and interfacial voiding, are employed to evaluate the solder joint electromigration reliability. The absolute resistance value is substantially affected by the geometrical layout of the metal lines in the four-point Kelvin structure, and this is confirmed by finite element simulation.Different current flow directions and strengths yielded different joint resistance responses. The anode joint, where electrons flow from the die to the substrate, usually measured an earlier resistance increase than the cathode joint, where electrons flow in the opposite direction. The change in measured joint resistances can be related to solder and interfacial voiding in the solder joint except for ±1 A current load, where resistance drop mainly attributed to the broken substrate Cu metallization as a result of “hot-spot” phenomenon. The solder joint temperature increases above the oven ambient temperature by ～25 °C, ～40 °C and ～65 °C for 0.6 A, 0.8 A and 1.0 A stress current, respectively. It is found that two-parameter log-normal distribution gives a better lifetime data fitting than the two-parameter Weibull distribution. Regardless of failure criterion used, the anode joint test cells usually calculated a shorter solder joint mean life with a lower standard variation of 0.3–0.6, as compared to the cathode joint test cells with a higher standard variation of 0.8–1.2. For a typical flip chip solder joint construction, electromigration reliability is mainly determined by the under bump metallization consumption and dissolution, with intermetallic compound formation near the die side of an anode joint.     

High-lead flip chip bump cracking on the thin organic substrate in a module package

Flip chip bump cracking was observed after Si die attach reflow on the organic substrate of a module package. High-lead bump and eutectic SnPb cladding were used on Si die and the substrate sides, respectively. The reflow peak temperature was 260 °C for compatibility with passive components attach using lead-free solder. Flip chip bump cracking occurred at high-lead solder close to the die side. The cracking was eliminated by lowering the reflow peak temperature down to 225 °C. Main cause of the cracking at 260 °C reflow was attributed to the extensive Sn diffusion into high lead bump. This decreased the melting point of the high-lead solder around the die side, which in turn worsened the adhesion between solder and die due to the coexistence of solid and liquid. Diffusion length estimation showed both of the liquid- and solid-state diffusions of Sn. Crack gap in the solder bump was consistent with thermal expansion mismatch between Si die and organic substrate. The bump cracking was mitigated by use of 225 °C reflow, limiting Sn diffusion and providing a good integrity of high lead bumps on die side.     

Development of reliable low temperature wafer level hermetic bonding using composite seal joint

A reliable composite metal seal comprising both intermetallic compounds (IMC) and solder joints, which are formed by transient liquid phase bonding and soldering respectively, is proposed and demonstrated in wafer level bonding experiments. Hermetic sealing is demonstrated on 8-in. wafers using low volume Cu/Sn materials at process temperatures as low as 280 °C. It is shown that the composite seal is stable when subjected to temperatures of 250 °C, and that it provides better hermeticity and reliability than an IMC seal alone.     

Development of chip-on-flex bonding using Sn-based bumps and non-conductive adhesive

We developed a reliable and low cost chip-on-flex (COF) bonding technique using Sn-based bumps and a non-conductive adhesive (NCA). Two types of bump materials were used for the bonding process: Sn bumps and Sn–Ag bumps. The bonding process was performed at 180 °C for 10 s using a thermo-compression bonder after dispensing the NCA. Sn-based bumps were easily deformed to contact Cu pads during the bonding process. A thin layer of Cu₆Sn₅ intermetallic compound was observed at the interface between Sn-based bumps and Cu pads. After bonding, electrical measurements showed that all COF joints had very low contact resistance, and there were no failed joints. To evaluate the reliability of COF joints, high temperature storage tests (150 °C, 1000 h), thermal cycling tests (−25 °C/+125 °C, 1000 cycles) and temperature and humidity tests (85 °C/85% RH, 1000 h) were performed. Although contact resistance was slightly increased after the reliability test, all COF joints passed failure criteria. Therefore, the metallurgical bond resulted in good contact and improved the reliability of the joints.     

Sn addition on the tensile properties of high temperature Zn–4Al–3Mg solder alloys

The Zn–4Al–3Mg based solder alloy is a promising candidate to replace the conventional Pb–5Sn alloy in high-temperature electronic packaging. In this study, the tensile properties of Zn–4Al–3Mg–xSn alloys (x = 0, 6.8 and 13.2 wt.%) at high temperatures (e.g., 100 °C, and 200 °C) were investigated. It was found that the uniaxial tensile strength (UTS) of Zn–4Al–3Mg–xSn solder alloys all decrease monotonously with the increment of temperature. The elongation ratio at 100 °C is superior to that at room temperature whereas follows a significant drop at 200 °C. The microstructure observations show that a typical brittle fracture of Zn–4Al–3Mg alloy occurs at room temperature and 200 °C under normal tension, whereas a ductile fracture is found at 100 °C. The 6.8 wt.% Sn addition in Zn–4Al–3Mg alloy causes a dramatic decrease of yield strength, and a slight deterioration of the ductility.     

Effect of trace platinum additions on the interfacial morphology of Sn–3.8Ag–0.7Cu alloy aged for long hours

While the Sn–Ag–Cu (SAC) family of solders are considered good candidate as lead-free solder replacement materials, their relatively short processing history and application result in a host of materials as well as reliability problems. For good metallurgical bonding and electrical connection, a thin, even layer of intermetallic compound (IMC) is required but excessive growth of the IMC layer will cause various reliability problems. This is especially critical for miniaturized solder pitches in very large scale integration circuits. This work adopts the composite approach of adding 0.15 and 0.30 wt.% of Pt into Sn–3.8Ag–0.7Cu alloy to study the effect of these additions to the IMC layer thickness between the solder and substrate. Alloys were isothermally aged at 150 °C for up to 1000 h to observe contribution of Pt in suppressing excessive IMC growth. It was found that when more Pt was added to the alloy, the IMC layer became more even and continuous. Voids and IMC layer thickness were reduced. This is attributed to the role of Pt in replacing Cu in the solder and thus impeding excessive diffusion.     

Study of solder jet bumping process using high-speed digital camera

With the development of solder jet technology in the electronic packaging industry, the bumping process of a molten metal droplet, which determines the shape of the solder bump and is crucial for the performance of the device, has attracted great interests. The solder bumping process of a single molten micro-droplet by a solder jet was recorded using a high-speed digital camera with a frame rate of 100,000 frames per second. It was found that the surface ripples on the solder bump was caused by the interaction of the fluid flow and the heat transfer/solidification processes in the bumping process of a micro-droplet. A droplet was observed to rebound on a copper pad coated with a layer of organic solderability preservatives, which was suspected to decrease the interfacial heat transfer coefficient between the droplet and the pad lower than a minimal value, 4.07×10⁴ W/m² K, making the recoiling droplet rebound away.