SCR ESD protection with reduced trigger voltage

A novel silicon controlled rectifier (SCR) electrostatic discharge (ESD) protection compatible with the advanced deep submicron triple well CMOS technologies is presented. By forward biasing the p-well/cathode junction, while keeping the n-well floating during ESD, the SCR trigger and holding voltages coincide at /spl sim/1 V. This value can be increased by a composite SCR/diode string circuit.     

ESD protection solutions for high voltage technologies

There is a trend to revive mature technologies while including high voltage options. ESD protection in those technologies is challenging due to narrow ESD design windows, NMOS degradation problems and the creation of unexpectedly weak parasitic devices. Different case studies are presented for ESD protection based on latch-up immune SCR devices.     

Investigation on LDMOS-SCR with high holding current for high voltage ESD protection

We investigate a novel lateral diffused metal-oxide semiconductor (LDMOS) device embedded in silicon controlled rectifier (SCR) and resistance-capacitance circuit (LDMOS-SCR-RC). The internal RC-coupling effect helps to increase the holding current (I_h), resulting in the enhanced latch-up immunity of electrostatic discharge (ESD) protection device in high voltage integrated circuits (HV ICs). Transmission line pulse testing results show that the proposed LDMOS-SCR-RC has the largest I_h and smallest trigger voltage (V_t1), comparing to the conventional LDMOS-SCR and LDMOS-SCR embedded a resistance. When key parameters such as the gate-length and resistance are optimized, the I_h increases further from 1.1 A to 1.5 A, while the V_t1 changes insignificantly. The detailed internal mechanism of LDMOS-SCR-RC with regard to key parameters is analyzed numerically by the SENTAURUS simulation. Results confirm that the increased I_h is mainly due to the enhanced RC-coupling effect. Finally, DC measurements conducted with a semiconductor curve tracer also confirm that the LDMOS-SCR-RC with small device area is effective for avoiding latch-up risks. The optimized LDMOS-SCR-RC provides a useful latch-up immune ESD protection solution for HV ICs input/output ports.     

Design of fabrication of ESD protection circuit with high holding voltage for power IC

In this paper, A newly Silicon Controlled Rectifier (SCR)-based Electric Static Discharge (ESD) protection circuit is proposed. The proposed circuit has the latch-up immunity in normal operating conditions with the high holding voltage by inserting the floating regions. To verify the electrical characteristics, a Technology Computer Aided Design (TCAD) simulation is performed by setting each of variables: D1, D2, D3, and D4. The results of the simulation show that the proposed protection circuit has the holding voltage 5 V higher than the conventional circuits and has the same level of robustness properties as the existing SCR. In addition, the proposed circuit is fabricated through a 0.18 μm Bipolar-CMOS-DMOS process. The electrical characteristics are confirmed by measuring Transmission Line Pulse, and the robustness properties are measured through Human Body Model (HBM) and Machine Model (MM). The holding voltage is about 20 V, which has the increases above 18 V or more compared to the conventional SCR. Therefore, the proposed circuit is proved to have the better ESD protection performance than HBM 8 kV and MM 800 V higher than HBM 2 kV and MM 200 V, the commercial standard.     

An investigation on capacitance-trigger ESD protection devices for high voltage integrated circuits

A novel cascaded complementary dual-directional silicon controlled rectifier (CCDSCR) structure has been proposed and implemented in a 0.5 μm 20 V Bipolar/CMOS/DMOS process as an ESD (electrostatic discharge) protection device. The ESD characteristics of the capacitance-trigger CCDSCR has been investigated by transmission line pulse (TLP) testing. Compared with the substrate-trigger insulated gate bipolar transistor with the enhanced substrate parasitic capacitance, the gate-driven trigger insulated gate bipolar transistor with the gate coupling capacitance and the normal dual-directional silicon controlled rectifier, the CCDSCR has the highest holding voltage of about 25.4 V and the best current conduction uniformity. In addition, it has the best figure of merit (FOM) with the value of about 0.64 mA/μm². The good current conduction uniformity in CCDSCR due to the enhanced substrate parasitic capacitance-trigger effect is finally confirmed by Sentaurus simulations.     

Compact MOS-triggered SCR with faster turn-on speed for ESD protection

The merged and compact MOS-triggered SCR devices have been compared and investigated in a 0.13 μm CMOS process. From experimental results, the turn-on time of compact MOS-triggered SCR has been improved from ～7.2 ns of merged MOS-triggered SCR to ～4 ns. Compared to merged MOS-triggered SCR devices, the compact MOS-triggered SCR devices can achieve a lower trigger voltage, a faster turn-on speed, a lower on-resistance, a lower clamping voltage and a higher failure current.     

Optimization of on-chip ESD protection structures for minimal parasitic capacitance

Diodes are key components in on-chip electrostatic discharge (ESD) protection design. As the operating frequency of the microchip being protected against the ESD continues to increase, the parasitic capacitance associated with the diodes in the ESD structure starts to impose problems for RF operation. This paper presents a systematic approach to optimize the diode structure for minimal parasitic capacitance based on the requirements of breakdown voltage and heat dissipation. Device simulator Atlas with mix-mode simulation capability is calibrated against measurement data and used to carry out the optimization. An optimized diode structure with a parasitic capacitance of less than 30 fF at an operating frequency of 10 GHz and ESD charging voltage of 1 kV has been suggested. Furthermore, a case study to implement and optimize the ESD protection structure based on an existing 0.13-μm CMOS technology has been presented and verified.     

SCR device fabricated with dummy-gate structure to improve turn-on speed for effective ESD protection in CMOS technology

Turn-on speed is the main concern for an on-chip electrostatic discharge (ESD) protection device, especially in the nanoscale CMOS processes with ultrathin gate oxide. A novel dummy-gate-blocking silicon-controlled rectifier (SCR) device employing a substrate-triggered technique is proposed to improve the turn-on speed of an SCR device for using in an on-chip ESD protection circuit to effectively protect the much thinner gate oxide. The fabrication of the proposed SCR device with dummy-gate structure is fully process-compatible with general CMOS process, without using an extra mask layer or adding process steps. From the experimental results in a 0.25-/spl mu/m CMOS process with a gate-oxide thickness of /spl sim/50 /spl Aring/, the switching voltage, turn-on speed, turn-on resistance, and charged-device-model ESD levels of the SCR device with dummy-gate structure have been greatly improved, as compared to the normal SCR with shallow trench isolation structure.     

一种用于提高ESD保护器件开启速度的新型变化横向基区 掺杂结构双触发晶闸管

The turn-on speed of electrostatic discharge （ESD） protection devices is very important for the protection of the ultrathin gate oxide. A double trigger silicon controlled rectifier device （DTSCR） can be used effectively for ESD protection because it can turn on relatively quickly. The turn-on process of the DTSCR is first studied, and a formula for calculating the turn-on time of the DTSCR is derived. It is found that the turn-on time of the DTSCR is determined mainly by the base transit time of the parasitic p-n-p and n-p-n transistors. Using the variation lateral base doping （VLBD） structure can reduce the base transit time, and a novel DTSCR device with a VLBD structure （VLBD_DTSCR） is proposed for ESD protection applications. The static-state and turn-on characteristics of the VLBD DTSCR device are simulated. The simulation results show that the VLBD structure can introduce a built-in electric field in the base region of the parasitic n-p-n and p--n-p bipolar transistors to accelerate the transport of free-carriers through the base region. In the same process and layout area, the turn-on time of the VLBD DTSCR device is at least 27% less than that of the DTSCR device with the traditional uniform base doping under the same value of the trigger current.     

ESD protection structure qualification – a new approach for release for automotive applications

To protect semiconductor products against damages due to electrostatic discharges separate protection structures are necessary. These structures are part of the device pad circuitry and designed for a dedicated wafer technology and ESD (Electrostatic Discharge) withstanding voltage.All present automotive qualification standards AEC-Q100/101 (Automotive Electronic Council) [1,2] do not cover a qualification and release of ESD protection structures related to their designed ESD strength.The paper will introduce a new qualification strategy for ESD protection structures depending on the designed ESD target. On dedicated ESD diodes drifts of several parameters versus time were analyzed. The results will be presented and discussed. Release targets for automotive applications will be defined.     

一个LVTSCR并联PMOS的高维持电压ESD防护器件

为了在5 V片上输入输出端进行静电放电(ESD)防护,提出了一种新型的LVTSCR结构。使用Silvaco 2D TCAD软件对此器件进行包含电学及热学特性的仿真。此新型器件交换了LVTSCR中N-Well的N+、P+掺杂区并引入了一个类PMOS结构用来在LVTSCR工作前释放ESD电流。器件仿真结果显示,与LVTSCR相比,该器件获得了更高的维持电压(10.51 V),以及更高的开启速度(1.05×10-10 s),同时触发电压仅仅从12.45 V增加到15.35 V。并且,如果加入的PMOS结构选择与NMOS相同的沟道长度,器件不会引起热失效问题。     

An on-chip ESD protection circuit with low trigger voltage inBiCMOS technology

A novel low-trigger dual-direction on-chip electrostatic discharge (ESD) protection circuit is designed to protect integrated circuits (ICs) against ESD surges in two opposite directions. The compact ESD protection circuit features low triggering voltage (~7.5 V), short response time (0.18-0.4 ns), symmetric deep-snap-back I-V characteristics, and low on-resistance (~Ω). It passed the 14-kV human body model (HBM) ESD test and is very area efficient (~80 V/μm width). The new ESD protection design is particularly suitable for low-voltage or multiple-power-supply IC chips     

ESD protection techniques for high frequency integrated circuits

The high frequency performance characteristics of integrated circuits (ICs) can be severely degraded by the addition of electrostatic discharge (ESD) protection networks on input or output pins. However, without protection networks ICs can be extremely sensitive to ESD. This paper will present a review of a number of techniques that have been used to protect ICs without significantly degrading their AC operating performance. Experimental results showing improved ESD performance are included for some of these techniques. Although the emphasis of the paper will be on silicon based circuits, III-V compounds will also be addressed.     

Improved inductive-system-level IEC ESD performance for automotive applications using mutual ballasted ESD protection technique

A new ESD failure mode under inductive IEC stress of automotive Controller Area Network (CAN) bus is identified. Inductor saturation causes increase of the rise-time from 1 ns to ~ 20 ns, leading to non-uniform conduction in the bidirectional ESD protection circuit. A novel mutual ballasting layout technique is introduced to recover the system level ESD performance.     

一种用于输出引脚的新型静电防护结构

Electro-static discharge(ESD)is always a serious threat to integrated circuits.To achieve higher robustness and a smaller die area at the same time,a novel protection structure for the output pad is proposed.The complementary SCR devices in this structure can protect not only the output under positive or negative stresses versus VDD or VSS,respectively,but also the power rails at the cost of almost no extra area.The robustness of the proposed structure is about three times higher than the conventional four-finger GGNMOS/GDPMOS structure in the same area condition.     

Circular under-pad multiple-mode ESD protection structure for ICs

A novel circular pad-oriented low-parasitic all-mode electrostatic discharge (ESD) protection structure is designed in BiCMOS for RF and mixed-signal (MS) ICs, featuring tunable triggering, low voltage clamping (~2 V), low discharge impedance (~Ω) and low leakage current (~pA). It consumes limited silicon and achieves 14 kV ESD protection     

Novel ESD strategy for high voltage non-volatile programming pin application

This paper presents a novel ESD strategy for non-volatile memory (NVM) programming pin in a 0.13um/30V technology. Suggested scheme can provide not only a major current discharge path to protect the internal circuit from ESD damage but also a voltage clamping function to prevent the soft error of programmed data during the ESD event. It has been validated by TLP experiments and TCAD simulation.     

A novel NLDMOS with a high ballast resistance for ESD protection

To prevent the non-uniform conduction phenomenon caused by the Kirk effect in an NLDMOS under ESD stress, a novel NLDMOS structure is proposed. High electron injection current is the base of Kirk effect. Higher electron injection can makes the Kirk effect more serious and lead easily to the non-uniform conduction phenomenon. By splitting the drain N＋ with the field oxide in the proposed structure, the crowded current can lead to a higher voltage drop on the ballast resistance. Therefore, the non-uniform conduction is suppressed, and its failure current is much improved.     

Design of novel DDSCR with embedded PNP structure for ESD protection* Xiuwen Bi (毕秀文), Hailian Liang (梁海莲), Xiaofeng Gu (顾晓峰)?, Long Huang (黄龙)

通过在常规双向可控硅器件(DDSCR)内部嵌入一个PNP结构,提出了一种新型的静电防护(ESD)器件DDSCR-PNP,以提高器件的维持电压(Vh),降低闩锁风险。首先,分析了DDSCR-PNP器件的工作机理,理论分析表明,内嵌PNP结构(PNP_2)使器件具有很好的电压箝位能力。然后,基于0.35 μm Bipolar-CMOS-DMOS工艺制造了实验器件,并利用Barth 4002传输线脉冲测试系统进行了分析。测试结果证明了DDSCR-PNP的Vh比传统DDSCR高得多,而且通过调节P阱宽度可进一步增加Vh。然而,当P阱宽度超过12 μm时,DDSCR-PNP的漏电流(IL)出现明显波动。最后,利用Sentaurus仿真分析了影响Vh和IL的原因。结果表明,横向PNP_2有助于提高Vh并降低IL,但其作用随着P阱宽度的增大而减弱,导致IL随之增大。这种新型的DDSCR-PNP器件为高压集成电路的ESD防护提供了一种有效的解决方案。