Prediction of deformation during manufacturing processes of silicon interposer package with TSVs

The purpose of this paper is to analyze and predict the thermal deformation of the through silicon via (TSV) interposer package during the manufacturing process and to perform a parametric study to minimize the warpage and thermal stress. Samples were selected during different stages of the assembly to observe the thermal behavior change. The Digital Image Correlation (DIC) technique was employed to measure the real-time deformation of the samples under thermal loading. To make a finite element analysis (FEA) model, material properties were characterized by DIC and Dynamic Mechanical Analysis (DMA). Based on the material properties and deformation data determined by experiments, a validated FEA model was established. To reduce the modeling complexity and the computing time in the simulation, the C4/underfill layer, micro bump/underfill layer, and TSV interposer were assumed to be isotropic. The most effective material properties for the isotropic layers were calculated by the composite theory. Also, the simulation followed the sequential manufacturing processes to investigate the thermal deformation change of each step and to obtain a more accurate prediction result. The thermal behavior from simulation showed a good agreement with the experimental result and this verified simulation model was implemented for the parametric study. A series of simulations were carried out to minimize the package warpage. To avoid any delamination failures, the stresses at the interface between the interposer and underfill were also evaluated. The effect of the interposer underfill material property, substrate material property, substrate thickness, and TSV density (Cu volume fraction) in the interposer were studied. It has been shown that low modulus, low coefficient of thermal expansion (CTE), and high glass transition temperature (T_g) underfill, as well as a low modulus and low CTE substrate can mitigate the package warpage and stress development at the interface between interposer and underfill. Also, a larger Cu volume TSV interposer and thick substrate can lessen the warpage of the package and stress at the interface.     

Novel Bumping and Underfill Technologies for 3D IC Integration

In previous work, novel maskless bumping and no‐flow underfill technologies for three‐dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low‐volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no‐flow underfill material named “fluxing underfill” is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two‐tier stacked TSV chips are sucessfully stacked.     

Design and Fabrication of a Flip-Chip-on-Chip 3-D Packaging Structure With a Through-Silicon Via for Underfill Dispensing

This paper presents a new package design for multichip modules. The developed package has a flip-chip-on-chip structure. Four chips [simulating dynamic random access memory (DRAM) chips for demonstration purpose] are assembled on a silicon chip carrier with eutectic solder joints. The I/Os of the four chips are fanned-in on the silicon chip carrier to form an area array with larger solder balls. A through-silicon via (TSV) hole is made at the center of the silicon chip carrier for optional underfill dispensing. The whole multichip module is mounted on the printed circuit board by the standard surface mount reflow process. After the board level assembly and X-ray inspection, the underfill process is applied to some selected specimens for comparative study purpose. The underfill material is dispensed through the center TSV hole on the silicon chip carrier to encapsulate the solder joints and the four smaller chips. Subsequently, scanning acoustic microscopy (SAM) is performed to inspect the quality of underfill. After the board-level assembly, all specimens are subject to the accelerated temperature cycling (ATC) test. During the ATC test, the electrical resistance of all specimens is monitored. The experimental results show that the packages without underfill encapsulation may fail in less than 100 thermal cycles while those with underfill can last for more than 1200 cycles. From the dye ink analysis and the cross-section inspection, it is identified that the packages without underfill have failure in the silicon chip carrier, instead of solder joints. The features and merits of the present package design are discussed in details in this paper.     

Reliability study of 3D IC packaging based on through-silicon interposer (TSI) and silicon-less interconnection technology (SLIT) using finite element analysis

Three-dimensional (3D) integration using the through-silicon via (TSV) approach becomes one promising technology in 3D packaging. 2.5D through-silicon interposer (TSI) is one of the applications of TSV technology, which provides a platform for realizing heterogeneous integration on the TSI interposer. However, TSV manufacturing faces several challenges including high cost. Si-less interconnection technology (SLIT) could overcome such challenges and provide the similar function and benefits as TSI interposer. In SLIT technology, TSVs and silicon substrate are eliminated and the back-end-of-line (BEOL) structures are the same as that in the TSI interposer. Thermo-mechanical reliability is still one important concern under process condition and thermal cycling (TC) test condition for both packaging technologies. In this study, solder joint reliability has been investigated and compared for both packaging technologies through finite element analysis (FEA). Reflow process induced low-k stress and package warpage have also been simulated and compared between packages with TSI and SLIT technologies. The simulation results show that SLIT-based package has comparable micro bump TC reliability as TSI-based package, but SLIT-based package has better C4 joint TC reliability than TSI-based package. SLIT-based package also has lower reflow-induced package warpage and low-k stress than TSI-based package. FEA simulation results verify that SLIT-based packaging is one of promising packaging technologies with good thermo-mechanical performance and cost efficiency.     

The Thermal Stress Analysis for IC Integrations with TSV Interposer by Complement Sector Models

The thermal stress of typical integrated circuit (IC) integration with the interposer of through silicon via (TSV) was investigated in this study. To overcome the huge computational costs due to meshing the large amount of TSVs’ microstructures, a simplified method, i.e. the complement sector model, was proposed and verified by the symmetric 1/8th full model. Using the sector model, the parametric studies were carried out to reveal the critical locations of TSV and the crucial parameters. Furthermore, statistical methods were invoked to clarify the impact of the major parameters, such as the modulus and coefficient of thermal expansion of underfill materials, the pitch and diameter of TSV, etc. Upon the analysis results, the design of minimized stress in TSV for the IC integration with TSV interposer was achieved.     

Effects of dimension parameters and defect on TSV thermal behavior for 3D IC packaging

Through Silicon Via (TSV) technology is a promising and preferred way to realize the reliable interconnection for 3D IC integration. The temperature changed in the processes of TSV manufacturing and chip using, due to the mismatch in the Coefficient of Thermal Expansion (CTE) of the materials used in TSV structure, significant thermal stress will be induced under the thermal load. These stresses may lead to various reliability issues. Dimension parameters and defects are the two factors affecting the thermal behavior of TSV. In order to optimize TSV design and the quality of via filling, a numerical model of Cu-filled TSV was established to simulate and analyze the effect of diameter, aspect ratio (AR) and defects on TSV thermal stress and deformation in this paper. Simulation results show that the equivalent stress and total deformation of TSV increases as the increase of the diameter of TSV. The effect of aspect ratio on equivalent stress is very little; however, it has a great impact on total deformation, especially for the large diameter of the TSV. Additionally, the effects of shape, size and location of defect on thermal stress were also investigated.     

The development of effective model for thermal conduction analysis for 2.5D packaging using TSV interposer

The effective model for the orthotropic TSV (Through Silicon Via) interposer in heat conduction for 2.5D IC integration was proposed in this study. The simple parallel model was used in out-of-plane direction to predict the effective thermal conductivity for the TSV interposer. The in-plane effective thermal conductivity for the interposer was derived on basis of heat balances. By introducing the effective orthotropic thermal parameters, the TSV structures can be ignored in the present effective model. The computations using the effective model for TSV interposer and the 2.5D package with interposer were carried out. The results showed that the accuracy of the effective model was above 95% comparing with the real model including TSV structures when the volume ratio of the electroplating copper and the silicon interposer is smaller than 10%. Using the effective model, the parametric studies on the interposer sizes and the thermal conductivities of different materials in the 2.5D package were conducted with higher efficiency. The results showed that the performance and sizes of EMC (Epoxy Molding Compound) and the package substrate are more important than that of internal underfills in heat dissipation of the package with TSV interposer.     

Thermomechanical reliability of underfilled BGA packages

The effect of underfill on various thermomechanical reliability issues in super ball grid array (SBGA) packages is studied in this paper. Nonlinear finite element models with underfill and no underfill are developed taking into consideration the process-induced residual stresses. In this study, the solder is modeled as time and temperature-dependent, while other materials are modeled temperature and direction-dependent, as appropriate. The stress/strain variations in the package due to thermal cycling are analyzed. The effect of underfill is studied with respect to magnitude and location of time-independent plastic strain, time-dependent creep strain and total inelastic strain in solder balls. The effect of copper core on the solder ball strains is presented. The possibility of delamination at the interposer-underfill interface as well as substrate-underfill interface is studied with the help of qualitative interfacial stress analysis. Results on SBGA packages indicate that the underfill does not always enhance BGA reliability, and that the properties of the underfill have a significant role in the overall reliability of the BGA packages. The predicted number of thermal cycles to solder joint fatigue are compared with the existing experimental data on similar nonunderfilled BGA packages.     

2.5D封装结构回流焊过程热应力分析

对一种典型2.5D封装结构在回流焊工艺过程的热应力进行仿真。通过对比分析传统热力学仿真方法与基于生死单元技术的热力学仿真方法,研究了计算方法对热应力计算结果的影响。在相同参考温度下,由不同计算方法得到的硅通孔(TSV)转接板应力结果相差不大,从焊球应力结果可推测出,基于生死单元技术的热力学仿真方法考虑了残余应力的累积模拟更适合于回流焊过程的热应力仿真。研究了2.5D封装回流焊过程中参考温度的选择对计算结果的影响,选用最高参考温度作为各个组件的参考温度,通常得到TSV转接板的应力值偏大,模拟的结果会更加偏于激进。通过对2.5D封装结构回流焊过程进行热应力分析,对比分析了计算模拟方法和参考温度的选择对最终计算结果的影响。该方法同样可用于指导其他同类2.5D封装结构应力的计算和分析。     

The effects of underfill and its material models onthermomechanical behaviors of a flip chip package

In this paper, the effects of underfill on thermomechanical behavior of two types of flip chip packages with different bumping size and stand-off height were investigated under thermal cycling both experimentally and two-dimensional (2-D) finite element simulation. The materials inelasticity, i.e., viscoelasticity of underfill U8437-3 and viscoplasticity of 60 Sn40 Pb solder, were considered in the simulations. The results show that the use of underfill encapsulant increases tremendously (~20 times) the thermal fatigue lifetime of SnPb solder joint, weakens the effects of stand-off height on the reliability, and changes the deformation mode of the package. It was found that the thermal fatigue crack occurs in the region with maximum plastic strain range, and the Coffin-Manson type equation could then be used for both packages with and without underfill. Solder joint crack initiation occurred before delamination when using underfill with good adhesion (75 MPa) and the underfill delamination may not be a dominant failure mode in the present study. The interfacial stresses at the underfill/chip interface were calculated to analyze delamination sites, which agree with the results from acoustic image. Moreover, the effects of material models of underfill, i.e., constant elasticity (EC) and temperature dependent elasticity (ET) as well as the viscoelasticity (VE), on the thermomechanical behaviors of flip chip package were also studied in the simulation. The VE model gives comparatively large plastic strain range and large displacements in the shear direction, as well as decreased solders joint lifetime. The ET model gives similar results as the VE model and could be used instead of VE in simulations for the purpose of simplicity     

Reliability issues of low-cost overmolded flip-chip packages

A significant need exists for the determination of critical stress characteristics within the low-cost overmolded flip-chip (OM-FC) packages. A systematic stress analysis is reported to investigate the OM-FC package for the optimal design of package geometries, materials combinations during the attachment, and thermal testing processes. A parametric study is conducted seeking the best package performance during the identified most stringent process which causes the largest stress within the low-cost substrate. High-stress location is predicted by finite-element analysis, and it was found that mold compound (MC) curing is the most stringent process for the reliability of substrate; higher underfill fillet, thicker die, larger die size without causing edge effect, solder mask defined structure resulted in smaller stresses in substrate. MC with lower coefficient of thermal expansion is a preferable and compliant substance that is good for using as molding and underfill material     

Thermal expansion behavior of through-silicon-via structures in three-dimensional microelectronic packaging

Thermo-mechanical reliability is an important issue for the development and deployment of the through-silicon-via (TSV) technology in three-dimensional (3D) microelectronic packaging. The mismatch in coefficient of thermal expansion (CTE) between the array of copper (Cu) lines and the surrounding silicon (Si), upon temperature variation, affects the overall thermal expansion behavior of the whole TSV structure itself and generates an internal stress state. In this work we use the finite element method to numerically study the effective in-plane CTE of the Si/Cu composite structure. A 3D unit-cell approach is undertaken, which takes into account uniformly distributed TSVs in the Si chip. Results of the temperature-dependent effective CTE can be used as model input for simulating larger-scale 3D packages where the Si/Cu TSV structure is treated as a homogeneous material. We also examine the evolution of stress and deformation fields, and identify potential reliability concerns associated with the thermal loading.     

Package design and materials selection optimization for overmolded flip chip packaging

In overmolded flip chip (OM-FC) packaging, interface delamination-particularly at the die/underfill interface-is often expected to be a main type of failure mode. In this paper, a systematic stress analysis is performed by means of numerical simulations for the optimal design of package geometries and materials combinations. The behavior of the interfacial stresses at the die/underfill and die/mold-compound (MC) during the molding process is investigated, followed by a parametric study to examine the effects of the package geometries and materials parameters including the underfill fillet size, die thickness, die size, die standoff height, solder mask design pattern, MC used as underfill material, MC properties, etc., on the interfacial stresses. The results demonstrate that a proper selection of these parameters can mitigate the interfacial stresses, and thus is important for the reliability of the low-cost OM-FC packages.     

Recent advances in flip-chip underfill: materials, process, and reliability

In order to enhance the reliability of a flip-chip on organic board package, underfill is usually used to redistribute the thermomechanical stress created by the coefficient of thermal expansion (CTE) mismatch between the silicon chip and organic substrate. However, the conventional underfill relies on the capillary flow of the underfill resin and has many disadvantages. In order to overcome these disadvantages, many variations have been invented to improve the flip-chip underfill process. This paper reviews the recent advances in the material design, process development, and reliability issues of flip-chip underfill, especially in no-flow underfill, molded underfill, and wafer-level underfill. The relationship between the materials, process, and reliability in these packages is discussed.     

Effects of Phase Change of Pb-Free Flip-Chip Solders During Board-Level Interconnect Reflow

The impact of phase change (from solid to liquid) on the reliability of Pb-free flip-chip solders during board-level interconnect reflow is investigated. Most of the current candidates for Pb-free solder are tin-based with similar melting temperatures near 230 degC. Thus, Pb-free flip-chip solders melt again during the subsequent board-level interconnect reflow cycle. Solder volume expands more than 4% during the phase change from solid to liquid. The volumetric expansion of solder in a volume constrained by chip, substrate, and underfill creates serious reliability issues. The issues include underfill fracture and delamination from chip or substrate. Besides decreasing flip-chip interconnect reliability in fatigue, bridging through underfill cracks or delamination between neighboring flip-chip interconnects by the interjected solder leads to failures. In this paper, the volume expansion ratio of tin is experimentally measured, and a Pb-free flip-chip chip-scale package (FC-CSP) is used to observe delamination and solder bridging after solder reflow. It is demonstrated that the presence of molten solder and the interfacial failure of underfill can occur during solder reflow. Accordingly, Pb-free flip-chip packages have an additional reliability issue that has not been a concern for Pb solder packages. To quantify the effect of phase change, a flip-chip chip-scale plastic ball grid array package is modeled for nonlinear finite-element analysis. A unit-cell model is used to quantify the elongation strain of underfill and stresses at the interfaces between underfill and chip or underfill and substrate generated by volume expansion of solder. In addition, the strain energy release rate of interfacial crack between chip and underfill is also calculated     

An improved methodology for determining temperature dependentmoduli of underfill encapsulants

Finite element analyses (FEAs) have been widely used to preventively predict the reliability issues of flip-chip (FC) packages. The validity of the simulation results strongly depends on the inputs of the involved material properties. For FC packages Young's modulus-temperature relationship is a critical material property in predicting of the package reliability during -55°C to 125°C thermal cycling. Traditional tensile tests can obtain the modulus at selected temperatures, but are tedious, expensive, and unable to accurately predict the Young's modulus-temperature relationship within a wide temperature range. Thus, this paper is targeted to provide a simple but relatively accurate methodology to obtain the Young's modulus-temperature relationship. In this paper, three commercial silica filled underfill materials were studied. A simple specimen (based on ASTM D638M) preparation method was established using a Teflon mold. A dynamic-mechanical analyzer (DMA) was used to obtain the stress-strain relationship under controlled force mode, storage and loss modulus under multi-frequency mode, and stress relaxation under stress relaxation mode. A simple viscoelastic model was used and an empirical methodology for obtaining Young's modulus-temperature relationship was established     

硅通孔尺寸与材料对热应力的影响

通过有限元分析研究了单个硅通孔及两片芯片堆叠模型的热应力。采用单个硅通孔模型证实了应力分布受填充材料(铜,钨)的影响,提出钨在热应力方面的优越性,确定了硅通孔尺寸(通孔直径、深宽比等因素)与热应力大小间的对应关系。为寻找拥有最佳热应力的材料组合,采用两片芯片堆叠的二维模型,对常用材料的组合进行了仿真分析,发现以二氧化硅为隔离层,钨为填充金属,锡为键合层的模型具有最理想的热应力特性,此外,铜、ABF以及锡的组合也表现出良好的热应力特性。     

Heat dissipation assessment of through silicon via (TSV)-based 3D IC packaging for CMOS image sensing

The study aims at evaluation of the steady-state heat dissipation capability of a high-density through silicon via (TSV)-based three-dimensional (3D) IC packaging technology (briefly termed 3D TSV IC packaging) designed for CMOS image sensing under natural convection through finite element analysis (FEA) and thermal experiments. To enhance modeling and computational efficiency, an effective approach based on FEA incorporating a 3D unit-cell model is proposed for macroscopically and thermally simulating the heterogeneous TSV chips. The developed effective thermal conductivities are compared against those obtained from a rule-of-mixture technique. In addition, the proposed numerical models are validated by comparison with two experiments. Besides, the uncertainties in the input chip power from the specific power supply and in the measured chip junction temperature by the thermal test die are evaluated. Finally, a design guideline for improved thermal performance is provided through parametric thermal study.     

Finite volume based CFD simulation of pressurized flip-chip underfill encapsulation process

This paper presents the simulation of pressurized underfill encapsulation process for high I/O flip chip package. 3D model of flip chip packages is built using GAMBIT and simulated using FLUENT software. Injection methods such as central point, one line, L-type and U-type are studied. Cross-viscosity model and volume of fluid (VOF) technique are applied for melt front tracking of the encapsulant. The melt front profiles and pressure field for all injection types are analyzed and presented. The pressure distribution within the flip-chip, fill volume versus filling time and viscosity versus shear rate are also plotted. The U-type injection is found to be faster in filling. The numerical results are compared with the previous experimental results and found in good conformity. The strength of CFD software in handling underfill encapsulation problems is proved to be excellent.