基于SRAM型FPGA单粒子效应的故障传播模型

SRAM型FPGA在辐射环境中易受到单粒子翻转的影响,造成电路功能失效.本文基于图论和元胞自动机模型,提出了一种针对SRAM型FPGA单粒子效应的电路故障传播模型.本文将单粒子翻转分为单位翻转和多位翻转来研究,因为多位翻转模型还涉及到了冲突处理的问题.本文主要改进了耦合度的计算方式,通过计算FPGA布局布线中的相关配置位,从而使得仿真的电路故障传播模型更接近于实际电路码点翻转的结果,与以往只计算LUT相关配置位的方法比较,平均优化程度为19.89%.最后阐述了本模型在故障防御方面的一些应用,如找出最易导致故障扩散的元胞.     

浮栅器件的单粒子翻转效应

基于中国原子能科学研究院的HI-13加速器,利用不同线性能量传输(LET)值的重离子束流对4款来自不同厂家的90 nm特征尺寸NOR型Flash存储器进行了重离子单粒子效应试验研究,对这些器件的单粒子翻转(SEU)效应进行了评估。试验中分别对这些器件进行了静态和动态测试,得到了它们在不同LET值下的SEU截面。结果表明高容量器件的SEU截面略大于低容量的器件;是否加偏置对器件的翻转截面几乎无影响;两款国产替代器件的SEU截面比国外商用器件高。国产替代器件SEU效应的LET阈值在12.9 MeV·cm²/mg附近,而国外商用器件SEU效应的LET阈值处于12.9~32.5 MeV·cm²/mg之间。此外,针对单粒子和总剂量效应对试验器件的协同作用也开展了试验研究,试验结果表明总剂量累积会增加Flash存储器的SEU效应敏感性,分析认为总剂量效应产生的电离作用导致了浮栅上结构中的电子丢失和晶体管阈值电压的漂移,在总剂量效应作用的基础上SEU更容易发生。     

基于码流的软件控制FPGA故障注入系统

基于静态随机存储器的现场可编程逻辑门阵列应用于航天电子系统时,易受到单粒子翻转效应的影响,存储数据会发生损坏。为评估器件和电路在单粒子翻转效应下的可靠性,提出一种基于TCL脚本控制的故障注入系统,可在配置码流层面模拟单粒子翻转效应。介绍了该故障注入系统的实现机制和控制算法,并将该软件控制方法与传统硬件控制方法进行对比分析。设计了一种关键位故障模型,从设计网表中提取关键位的位置信息,缩小了故障注入的码流范围。在Virtex-5开发板XUPV5-LX110T上的故障注入实验表明,该故障注入系统能有效模拟单粒子翻转效应,与传统随机位故障注入相比,关键位故障注入的故障率提高了近5倍。     

Estimating the Single-Event Upset sensitivity of a memory array using simulation

This paper proposes a straightforward methodology to estimate by simulation the Single-Event Upset (SEU) sensitivity of a memory array using open source and commercial codes. It is based on a four-step process including the calculation of the deposited energy distribution in sensitive volumes, the determination of a criterion for SEU triggering, the count of SEUs, and finally the SEU cross-section calculation. The approach is validated with neutron irradiation experiments performed on a 65 nm Static Random Access Memory (SRAM).     

面向航空环境的多时钟单粒子翻转故障注入方法

随着新型电子器件越来越多地被机载航电设备所采用,单粒子翻转(Single Event Upset, SEU)故障已经成为影响航空飞行安全的重大隐患。首先,针对由于单粒子翻转故障的随机性,该文对不同时刻发生的单粒子翻转故障引入了多时钟控制,构建了SEU故障注入测试系统。然后模拟真实情况下单粒子效应引发的多时间点故障,研究了单粒子效应对基于FPGA构成的时序电路的影响,并在线统计了被测模块的失效数据和失效率。实验结果表明,对于基于FPGA构建容错电路,采用多时钟沿三模冗余(Triple Modular Redundancy, TMR) 加固技术可比传统TMR技术提高约1.86倍的抗SEU性能;该多时钟SEU故障注入测试系统可以快速、准确、低成本地实现单粒子翻转故障测试,从而验证了SEU加固技术的有效性。     

基于三模冗余架构的集成电路加固设计

随着科技的发展,人类对太空领域的研究会越来越多,对于航天器件的要求也会越来越高,其中可靠性是航天器件一个重要的指标.空间辐射环境中的高能粒子引发的单粒子翻转事件严重影响星载电子系统的可靠性.现有的抗辐照设计多集中在工艺库和版图的加固上,但是要完全的抑制单粒子故障的产生是不现实的.克服了现有技术中存在的不足,提供了一种基于三模冗余的电路架构,利用冗路架构去屏蔽已发生故障对整个电路的影响,使得整个电路的抗辐照性能得到极大地提升.     

纳米器件质子在轨单粒子翻转率预计方法

研究了纳米器件在空间轨道中质子引起单粒子翻转(SEU)率的预计方法。以65 nm SRAM为样品,利用加速器进行了质子和重离子单粒子翻转试验,分别基于质子试验数据和重离子试验数据,预计了空间轨道中质子引起的单粒子翻转率。结果表明,用重离子试验数据预计的质子单粒子翻转率比用质子试验数据预计的低1.5个数量级。研究认为,为了评估纳米器件单粒子翻转敏感性,需进行质子单粒子翻转试验,并基于质子试验数据进行在轨质子翻转率预计。     

An Extensible Code for Correcting Multiple Cell Upset in Memory Arrays

As the microelectronics technology continuously advances to deep submicron scales, the occurrence of Multiple Cell Upset (MCU) induced by radiation in memory devices becomes more likely to happen. The implementation of a robust Error Correction Code (ECC) is a suitable solution. However, the more complex an ECC, the more delay, area usage and energy consumption. An ECC with an appropriate balance between error coverage and computational cost is essential for applications where fault tolerance is heavily needed, and the energy resources are scarce. This paper describes the conception, implementation, and evaluation of Column-Line-Code (CLC), a novel algorithm for the detection and correction of MCU in memory devices, which combines extended Hamming code and parity bits. Besides, this paper evaluates the variation of the 2D CLC schemes and proposes an additional operation to correct more MCU patterns called extended mode. We compared the implementation cost, reliability level, detection/correction rate and the mean time to failure among the CLC versions and other correction codes, proving the CLCs have high MCU correction efficacy with reduced area, power and delay costs.     

真实FPGA器件下单粒子软错误评估工具设计

FPGA器件在航天领域应用广泛,然而在空间环境下,基于SRAM工艺的FPGA器件极易受到单粒子翻转(Single Event Upsets,SEU)影响而导致电路发生软错误。针对具有代表性的Xilinx Virtex系列器件进行了SEU评估方法的研究,设计并开发了一款面向Virtex器件的SEU效应评估工具,并与FPGA标准设计流程进行了有效融合。实验结果表明,提出的评估方法和工具对Virtex器件的SEU效应可以进行准确的评估,从而为FPGA结构设计和应用开发提供先于硬件实现的软件验证环境,对高可靠性FPGA芯片的研究、开发和设计都具有重要意义。     

北京正负电子对撞机次级束质子单粒子翻转计算和试验研究

北京正负电子对撞机(BEPC)电子直线加速器试验束打靶产生的次级束中包含质子,其中能量约为50MeV~100MeV的质子占有很大比例,这弥补了国内高能质子源的空白。本工作计算得到次级束中的质子能谱,建立质子单粒子翻转截面计算方法,在北京正负电子对撞机次级束质子辐射环境中,计算静态随机存取存储器的质子单粒子翻转截面,设计了SRAM质子单粒子翻转截面测试试验,发现SRAM单粒子翻转和注量有良好的线性,这是SRAM发生单粒子翻转的证据。统计得到不同特征尺寸下SRAM单粒子翻转截面,试验数据与计算结果相符,计算和试验结果表明随着器件特征尺寸的减小器件位单粒子翻转截面减小,但器件容量的增大,翻转截面依然增大,BEPC次级束中的质子束可以开展中高能质子单粒子效应测试。     

设计和表征一个65nm抗辐射标准单元库

提出了一个基于商用65nm工艺在晶体管级设计抗辐射数字标准单元库的方法。因为当C单元的两个输入是不同的逻辑值时输出会进入高阻模式,并保持输出逻辑电平不变,而当输入端有相同的逻辑值时,C单元的功能就像一个反相器的特性。因此它有把因为辐射粒子引起的单粒子翻转（SEU）效应或单粒子传输（SET）效应所产生的毛刺滤除掉的能力。在这个标准单元库中包含了在晶体管级使用C单元设计了抗辐射的触发器,以便于芯片设计者可以使用这个库来设计具有更高抗辐射能力和减小面积、功耗和延迟的芯片。在最后为了能表征标准单元在硅片上的延迟特性,一个基于环形振荡器的芯片结构用来测量每个单元的延迟,以及验证抗辐射能力。延迟测量结果跟版图后仿真结果偏差在10％以内。     

Two effective methods to mitigate soft error effects in SRAM-based FPGAs

This paper proposes an effective architecture that can mitigate Single Event Upset (SEU) effects in SRAM-based FPGAs. The architecture employs two different methods in both logic and interconnection resources. The logic resources utilize a new function generator that can tolerate 100% of single faults in its configuration memory while it can generate all the k-input Boolean functions. In the interconnection resources, a kind of formation redundancy that can detect 94% of single faults in its configuration memory is applied. Both methods are based on an interesting relation in Boolean functions, identified as mapping. By this concept, a Boolean function is generated by modifying the inputs of other Boolean functions. The effectiveness of the proposed architecture is procured by a standard fault injection tool; moreover, different parameters such as required area, power, and delay are achieved by using synopsis® synthesis tool. The results show that the area, power, and delay overheads are respectively 179%, 94%, and 60% in comparison with the simple architecture.     

A new approach for Total Ionizing Dose effect analysis on Flash-based FPGA

With the high flexibility, increasing computing power and lower power consumption, FPGA devices have gained a lot interest in space and avionic applications. Among different types of FPGA devices, Flash-based FPGA is becoming increasingly attractive since their configuration memory is almost immune to Single Event Upset (SEU) induced by energetic particles. However, when applied in such applications, especially long term space missions, the FPGA devices are subject to cumulative ionizing damage, as known as Total Ionizing Dose (TID). The TID may affect the FPGA causing performance degradation and possible eventual permanent damage leading to functional failure. In this paper, we propose a new workflow for analyzing the TID effect on Flash-based FPGA considering the different distributions of TID over the chip and the different impact factors when the configurable logic is programmed to implement different logics in the design. The experimental results show the feasibility of such workflow to be used as assessment tool at early stage of design development.     

Radiation Hardened by Design Latches — A Review and SEU Fault Simulations

There are many Radiation Hardened by Design (RHBD) architectures presented in the literature to mitigate Single Event Upset (SEU) in a storage element, a latch. Nevertheless, the design of a SEU hardened latch is being continuously improved with respect to reliability, performance, power consumption and area overhead. SEU mitigating techniques by design focus on reducing criticality of sensitive nodes in a latch. Sensitive node(s) in a latch could be an active and/or a high impedance node(s). In this paper, we have classified previously presented SEU hardened by design latch architectures and reviewed SEU mechanisms in selected RHBD latch architectures on Complementary Metal Oxide Semiconductor (CMOS) technology models. Simulation studies using latest fault simulation model have been carried out. Simulation results have revealed some interesting observations described in this paper. Our findings, based on analyses, will provide valuable design inputs for futuristic RHBD latches with advanced technology nodes.     

Hybrid time and hardware redundancy to mitigate SEU effects on SRAM-FPGAs: Case study over the MicroLAN protocol

SRAM-based field programmable gate arrays (FPGAs) are particularly sensitive to single event upsets caused by high-energy space radiation. Single Event Upset (In order to successfully deploy the SRAM-FPGA based designs in aerospace applications, designers need to adopt suitable hardening techniques. In this paper, we describe novel hybrid time and hardware redundancy (HT&HR) structures to mitigate SEU effects on FPGA, especially digital circuits that are designed with bidirectional ports. The proposed structures that combine time and hardware redundancy decrease the SEU propagation mechanisms among the redundant hard units. Analysis results and fault injection experiments on some standard ISCAS benchmarks and MicroLAN protocol, as a case study over the bidirectional ports, show that the capability of tolerating SEU effects in HT&HR technique increases up to 70 times with respect to solely hardware redundant versions. On average, the proposed method provides 39.2 times improvement against single upset faults and 14.9 times for double upset faults; however it imposes about 14.7% area overhead. Also, for the considered benchmarks, HT&HR circuits become 8.8% faster on the average than their TMR versions.     

CMOS SRAM单粒子翻转效应的解析分析

分析了影响ＣＭＯＳＳＲＡＭ单粒子翻转效应的时间因素,指出不能仅根据临界电荷来判断发生单粒子翻转效应与否,必须考虑器件的恢复时间、反馈时间和电荷收集过程．给出了恢复时间和反馈时间的计算方法,提出了器件抗单粒子翻转的加固措施．对电荷收集过程中截止管漏极电位的变化进行了分析,提出了临界电荷新定义,并给出了判断带电粒子入射能否导致器件发生单粒子翻转效应的方法     

Effect of topological placement of memory cells in memory chips on multiplicity of cell upsets from heavy charged particles

An analysis of factors influencing operational reliability of memory chips has been performed. Different topological configurations of 6-transistors memory cells have been considered. Two configurations of cells most sensitive to the influence of multiple cell upsets (MCUs) have been identified.     

用SOI技术提高CMOS SRAM的抗单粒子翻转能力

提高静态随机存储器（SRAM）的抗单粒子能力是当前电子元器件抗辐射加固领域的研究重点之一。体硅CMOS SRAM不作电路设计加固则难以达到较好抗单粒子能力,作电路设计加固则要在芯片面积和功耗方面做出很大牺牲。为了研究绝缘体上硅（SOI）基SRAM芯片的抗单粒子翻转能力,突破了SOI CMOS加固工艺和128kb SRAM电路设计等关键技术,研制成功国产128kb SOI SRAM芯片。对电路样品的抗单粒子摸底实验表明,其抗单粒子翻转线性传输能量阈值大于61．8MeV／（mg／cm^2）,优于未做加固设计的体硅CMOS SRAM。结论表明,基于SOI技术,仅需进行器件结构和存储单元的适当考虑,即可达到较好的抗单粒子翻转能力。     

基于VMM验证方法学的MCU验证环境

随着SystemVerilog成为IEEE的P1800规范,越来越多的项目开始采用基于SystemVerilog的验证方法学来获得更多的重用扩展性、更全面的功能覆盖率,以及更合理的层次化验证结构。本文主要提出了一种基于SystemVerilog的VMM验证方法学的验证环境。在这个验证环境中,验证了一个8位的MCU,这个MCU主要应用在数据卡项目中,主要特点是时钟周期与指令周期相等,并且相对于标准MUC指令需要时钟周期较少。通常验证MCU都会应用以前的16进制代码读入ROM中,通过仿真观察波形以及输出来确认功能正确,每次只能根据实际应用程序测试对应的一部分MCU功能,缺少一个量化的指标,而且每次改动MCU,需要重新检查结果,效率比较低,而且验证质量无法保证。这里实现了用SystemVerilog来搭建一个基于VMM验证方法学的可移植、重用、扩展、完全自动检查、具有层次化结构的MCU验证平台。这里运用了VMM方法学,设计了一个层次化的验证结构,可以较简单地移植并验证其他类型的MCU,抽象了MCU指令,并且通过约束产生随机指令激励,可以实现遍历所有指令以及地址,另外功能覆盖率模型帮助能够收集并监测覆盖率。     

Analysis of 6 T SRAM cell in sub-45 nm CMOS and FinFET technologies

The semiconductor industry is exploring technology scaling to pursuit the Moore's Law. The actual processors operation frequency grows the need for fast memories. Nowadays, SRAM cells occupy a considerable area in VLSI designs. Several challenges follow this performance improvement achieved at each new technology node. The Process, Voltage, and Temperature (PVT) variability, aging effects due to BTI influence and radiation-induced Single-Event Upset (SEU) are three relevant issues on the SRAM nanometer design. The main contribution of this work is to present a panorama of these effects on SRAM as technology scaling. The most frequently used SRAM cell, the 6 T, is evaluated from 45 nm to 7 nm bulk CMOS and FinFET technologies. Results observed the effects on delay, power, and noise margins, showing that process variability can introduce up to 100% of power deviation. Read Static Noise Margin (RSNM) presents about 20% of deviation under process variability and the cell noise robustness is reduced dramatically in worst cases. FinFET technology and high-performance models show more robustness against radiation. SRAM cells with low-power devices demonstrated more sensitive to delay degradation due to aging effects.