Multi-bits error detection and fast recovery in RISC cores

The particles-induced soft errors are a major threat to the reliability of microprocessors. Even worse, multi-bits upsets (MBUs) are ever-increased due to the rapidly shrinking feature size of the IC on a chip. Several architecture-level mechanisms have been proposed to protect microprocessors from soft errors, such as dual and triple modular redundancies (DMR and TMR). However, most of them are inefficient to combat the growing multi-bits errors or cannot well balance the critical paths delay, area and power penalty. This paper proposes a novel architecture, self-recovery dual-pipeline (SRDP), to effectively provide soft error detection and recovery with low cost for general RISC structures. We focus on the following three aspects. First, an advanced DMR pipeline is devised to detect soft error, especially MBU. Second, SEU/MBU errors can be located by enhancing self-checking logic into pipelines stage registers. Third, a recovery scheme is proposed with a recovery cost of 1 or 5 clock cycles. Our evaluation of a prototype implementation exhibits that the SRDP can successfully detect particle-induced soft errors up to 100% and recovery is nearly 95%, the other 5% will inter a specific trap.     

Selective SWIFT-R

Commercial off-the-shelf microprocessors are the core of low-cost embedded systems due to their programmability and cost-effectiveness. Recent advances in electronic technologies have allowed remarkable improvements in their performance. However, they have also made microprocessors more susceptible to transient faults induced by radiation. These non-destructive events (soft errors), may cause a microprocessor to produce a wrong computation result or lose control of a system with catastrophic consequences. Therefore, soft error mitigation has become a compulsory requirement for an increasing number of applications, which operate from the space to the ground level. In this context, this paper uses the concept of selective hardening, which is aimed to design reduced-overhead and flexible mitigation techniques. Following this concept, a novel flexible version of the software-based fault recovery technique known as SWIFT-R is proposed. Our approach makes possible to select different registers subsets from the microprocessor register file to be protected on software. Thus, design space is enriched with a wide spectrum of new partially protected versions, which offer more flexibility to designers. This permits to find the best trade-offs between performance, code size, and fault coverage. Three case studies have been developed to show the applicability and flexibility of the proposal.     

软硬件协同设计的SEU故障注入技术研究

针对现有容错计算机故障注入方法缺乏对空间环境中频发的单粒子故障模型的支持,本文提出了一种利用背板技术的软硬件协同仿真与故障注入技术,分别针对寄存器部件和存储器部件的特性,设计了多位错误的单粒子故障模型,在寄存器传输级实现了通过软件生成故障并注入到硬件设计中的软硬件协同故障注入方案,避免了在硬件设计中修改代码生成故障破坏系统完整性的问题.基于Leon2内核的故障注入实验表明,本文设计的平台为处理器容错设计提供了一个自动化、非侵入、低开销的故障注入和可靠性评估方案.     

用于低开销容错设计的存储部件可靠性评估研究

低开销容错技术是当前软错误研究领域的热点。为了对微处理器进行低开销容错保护,首先就需要对微处理器可靠性(即体系结构弱点因子AVF (Architectural Vulnerability Factor))进行准确评估。然而,现有的AVF评估工具的精确性和适用范围都受到不同程度的限制。该文以微处理器上的核心部件(即存储部件)作为研究对象,对AVF评估方法进行改进,提出了一种访存操作分析和指令分析相结合的AVF评估策略HAES (Hybrid AVF Evaluation Strategy)。该文将HAES融入到通用的模拟器中,实现了更精确和更通用的AVF评估框架。实验结果表明相比其它AVF评估工具,利用该文提出的评估框架得到的AVF平均降低22.6%。基于该评估框架计算得到的AVF更加精确地反映了不同应用程序运行时存储部件的可靠性,对设计人员对微处理器进行低开销的容错设计具有重要指导意义。     

A New Time Independent Asynchronous Protocol and Its Applications

Communications to, or between, low-end microprocessors within a product always comes at a cost. This paper develops a new, economic solution that will be useful in a variety of cost-sensitive applications. This paper starts by identifying the properties of an inter-microprocessor communications system that adds minimal cost to a product and enables the use of lower price microprocessors. This leads us to introduce a new category of communications called time independent asynchronous (TIA) communications. An economic 2-wire TIA communications protocol is developed and described using timing diagrams. The protocol is modeled using signal transition graphs (STGs), which are found to have some limitations, and so a modification is developed called STG for threads (STG-FT). Two-wire TIA is simulated to confirm livelock and deadlock properties. An implementation is created that verifies the simulation results, and the performance is reported. Finally, a novel application of 2-wire TIA is discussed.     

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process

We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches in a 90-nm dual-V/sub T/ CMOS process. Accelerated measurements with a neutron beam at Los Alamos National Laboratory demonstrated 10/spl times/ better reliability of the SER-tolerant latch over the standard latch at no speed degradation. The worst case energy and area penalties were 39% and 44%, respectively. Both the energy and area penalties are negligible for standard-latch transistor sizes at least double the minimum width. We analyzed the effects of the recovery time, threshold voltage assignment, and leakage on the SER robustness. The proposed latch can improve reliability of critical sequential logic elements in microprocessors and other circuits.     

A fault-tolerant cache architecture based on binary set partitioning

Caches, which are comprised much of a CPU chip area and transistor counts, are reasonable targets for transient single and multiple faults induced from energetic particles. This paper presents: (1) a new fault detection scheme for tag arrays of cache memories and (2) an architectural cache to improve performance as well as dependability. In this architecture, cache space is divided into sets of different sizes and different tag lengths. Using the proposed fault detection scheme, i.e., GParity, when single and multiple errors are detected in a word, the word is rewritten by its correct data from memory and its GParity code is recomputed. The error detection scheme and the cache architecture have been evaluated using a trace driven simulation with soft error injection and SPEC 2000 applications. Moreover, reliability and mean-time-to-failure (MTTF) equations are derived and estimated. The results of GParity code are compared with those of other protection codes and memory systems without redundancies and with single parity codes. The results show that error detection improvement varies between 66% and 96% as compared with the already available single parity in microprocessors.     

Microarchitectural innovations: boosting microprocessor performancebeyond semiconductor technology scaling

Semiconductor technology scaling provides faster and more plentiful transistors to build microprocessors, and applications continue to drive the demand for more powerful microprocessors. Weaving the "raw" semiconductor material into a microprocessor that offers the performance needed by modern and future applications is the role of computer architecture. This paper overviews some of the microarchitectural techniques that empower modem high-performance microprocessors. The techniques are classified into: 1) techniques meant to increase the concurrency in instruction processing, while maintaining the appearance of sequential processing and 2) techniques that exploit program behavior. The first category includes pipelining, superscalar execution, out-of-order execution, register renaming, and techniques to overlap memory-accessing instructions. The second category includes memory hierarchies, branch predictors, trace caches, and memory-dependence predictors. The paper also discusses microarchitectural techniques likely to be used in future microprocessors, including data value speculation and instruction reuse, microarchitectures with multiple sequencers and thread-level speculation, and microarchitectural techniques for tackling the problems of power consumption and reliability     

一种针对软错误的程序可靠性定量分析方法

 宇宙射线辐射所导致的软错误是航天计算面临的最主要挑战之一.而随着集成电路制造工艺的持续进步,现代处理器的计算可信性日益面临着软错误的严重威胁.当前,很少有研究从软件角度分析软错误对系统可靠性的影响.在程序汇编代码的基础上,提出一种针对软错误的程序可靠性定量分析方法PRASE,并且提出基本块分析法和3条运算定律以改进其分析效率.实验表明软错误对程序可靠性的影响与程序自身结构密切相关,同时分析结果还指出在软错误影响下程序的关键脆弱点,对实现针对软错误的高效容错算法有参考意义.     

High-performance microprocessor architectures

Over the past few years, microprocessor designs have undergone an evolution process shaped largely by improvements in LSI circuit technology and experiences gained from the very large user community. By and large, most microprocessors have internal architectures that are patterned after classical CPU structures. This trend is changing rapidly. High-performance LSI microprocessors are emerging at a slow but steady pace, with architectural features borrowed from larger and more powerful computers. This paper examines aspects of pipelined concurrency and microprogramming as applied to LSI microprocessors, for the purpose of enhancing performance.     

Compiler technology for future microprocessors

Advances in hardware technology have made it possible for microprocessors to execute a large number of instructions concurrently (i.e., in parallel). These microprocessors take advantage of the opportunity to execute instructions in parallel to increase the execution speed of a program. As in other forms of parallel processing, the performance of these microprocessors can vary greatly depending on the qualify of the software. In particular the quality of compilers can make an order of magnitude difference in performance. This paper presents a new generation of compiler technology that has emerged to deliver the large amount of instruction-level-parallelism that is already required by some current state-of-the-art microprocessors and will be required by more future microprocessors. We introduce critical components of the technology which deal with difficult problems that are encountered when compiling programs for a high degree of instruction-level-parallelism. We present examples to illustrate the functional requirements of these components. To provide more insight into the challenges involved, we present in-depth case studies on predicated compilation and maintenance of dependence information, two of the components that are largely missing from most current commercial compilers     

A soft-output decoding algorithm for concatenated systems

In order to fully utilize the SDD (soft-decision decoding) capacity of the outer codes in a concatenated system, reliability information on the inner decoder outputs (called soft outputs) needs to be provided to the outer decoder. This paper shows that a modified MAP algorithm can be effectively and accurately used to generate such information. In the course of the presentation, a metric based on the reliability information is proposed for the outer decoder. This metric has the Euclidean metric on AWGN channels as its special case, which leads to the concept of generalized SDD (GSDD). Several practical concerns regarding the proposed soft-output decoder are addressed through theoretical analysis and simulation: the effect of finite decoding depth, computational complexity, range overflow, and scaling. Comparisons to previous work on soft-output decoders are made     

Substream-based soft handoff in CDMA cellular networks

We present a new soft handoff scheme that enhances the reliability during soft handoff by increasing the signal distance (Euclidean and/or Hamming) in forward link code division multiple access cellular networks. Each base station participating in soft handoff sends a disjoint subset of the main data stream (called sub-stream) and the mobile receiver reassembles the sub-streams and restores the main data stream. This approach can reduce the data rate per base station by a factor of the number of participating base stations and thereby can increase the signal distance as opposed to the diversity gain. It is shown that the proposed soft handoff scheme is promising for high data rate applications which are the major interests in the next generation cellular networks.     

基于一种交织码的多位翻转容错技术研究

随着技术的发展和核心电压的降低,存储器更易受瞬时错误（软错误）影响,成为影响航天器件可靠性的主要原因。错误检测与纠正（EDAC）码（也称错误纠正码）常用来对SRAM型存储器中的瞬时错误进行纠正,由单个高能粒子引起的多位翻转错误（SEMU）是普通纠一检二（SEC-DED）编码所无法处理的。提出了一种交织度为2的(26,16)交织码,该码由两个能纠正一位随机错误、二位突发错误的(13,8)系统码组成,(26,16)交织码能够纠正单个码字中小于二位的随机错误和小于四位突发错误（DEC-QAEC）。通过理论分析和硬件平台实验表明,该交织码在存储资源占用率、实时性相当情况下可靠性优于同等长度的SEC DED码,能有效提高SRAM型存储器抗多位翻转错误的能力。      

The Development of a Bubble Memory Controller for Low-Cost FiIe Use

The bubble memory has several features such as low-cost low-power consumption, small physical size, high reliability, and non-volatility, which make it suitable for low-cost microcomputer files. The microcomputer interface and bubble control logics are integrated into a single chip which we call the bubble memory controller (BMC), making it possible to install a complete 1 Mbit bubble memory system on a 15 cm X 18 cm board. This paper describes in detail the BMC development and considers important matters in the design of large-scale logic LSI's which are represented by the microprocessors.     

超深亚微米IC的宇宙射线辐射软失效研究

辐射引起的软失效一直是影响半导体可靠性的一个重大问题.特别是宇宙射线引起的在地球表面的高能中子,由于其特有的高穿透性很难有效屏蔽防护.介绍了其造成半导体器件软失效的失效机理,并利用加速软失效测试模型分别对90,65和45nm工艺的随机静态存储器的软失效率进行了分析,研究了该类中子造成的软失效率的影响因素及相关规律.据此预测了更高工艺技术产品的中子软失效率,在为芯片设计和制造阶段就对中子辐射可靠性的防护提供了一定的参考和依据.     

Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits

Recent radiation ground testing campaigns of digital designs have demonstrated that the probability for Single Event Transient (SET) propagation is increasing in advanced technologies. This paper presents a hierarchical reliability-aware synthesis framework to design combinational circuits at gate level with minimal area overhead. This framework starts by estimating the vulnerability of the circuit to SETs. This is done by modeling the SET propagation as a Satisfiability problem by utilizing Satisfiability Modulo Theories (SMTs). An all-solution SMT solver is adapted to estimate the soft error rate due to SETs. Different strategies to mitigate SETs are integrated in the proposed framework to selectively harden vulnerable nodes in the design. Both logical and temporal masking factors of the target circuit are improved to harden sensitive paths or sub-circuits, whose SET propagation probability is relatively high. This process is repeated until the desired soft error rate is achieved or a given area overhead constraint is met. The proposed framework was implemented on different combinational designs. The reliability of a circuit can be improved by 64% with less than 20% area overhead.     

系统级芯片设计语言和验证语言的发展

由于微电子技术的迅速发展和系统芯片的出现,包含微处理器和存储器甚至模拟电路和射频电路在内的系统芯片的规模日益庞大,复杂度日益增加。人们用传统的模拟方法难以完成设计验证工作,出现了所谓“验证危机”。为了适应这种形势,电子设计和验证工具正在发生迅速而深刻的变革。现在基于RTL级的设计和验证方法必须向系统级的设计和验证方法过渡,导致了验证语言的出现和标准化,本文将对当前出现的系统级设计和验证语言进行全面综述,并论述验证语言标准化的情况。分析他们的优缺点和发展趋势。最后简单评述当前的验证方法,说明基于断言的验证是结合形式化验证和传统模拟验证可行的途径。     

A novel radiation hardened by design latch

Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-event-upset (SEU) immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the presented latch are evaluated by detailed SPICE simulations. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented latch is more area efficient, delay and power efficient. Fault injection simulations also demonstrate the robustness of the presented latch even under high energy particle strikes.     

一种新型的抗辐射加固锁存器

Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-eventupset （SEU） immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the presented latch are evaluated by detailed SPICE simulations. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented latch is more area efficient, delay and power efficient. Fault injection simulations also demonstrate the robustness of the presented latch even under high energy particle strikes.