Evidence for causality between GaN RF HEMT degradation and the EC-0.57 eV trap in GaN

The degradation of industry-supplied GaN high electron mobility transistors (HEMTs) subjected to accelerated life testing (ALT) is directly related to increases in concentrations of two defects with trap energies of E_C-0.57 and E_C-0.75 eV. Pulsed I-V measurements and constant drain current deep level transient spectroscopy were employed to evaluate the quantitative impact of each trap. The trap concentration increases were only observed in devices that showed a 1 dB drop in output power and not the result of the ALT itself indicating that these traps and primarily the E_C-0.57 eV trap are responsible for the output power degradation. Increases from the E_C-0.57 eV level were responsible for 80% of the increased knee walkout while the E_C-0.75 eV contributed only 20%. These traps are located in the drain access region, likely in the GaN buffer, and cause increased knee walkout after the application of drain voltage.     

Microwave performance of field-plate 0.13-μm MOS transistors with varying field-plate extension

Si-based field-plate 0.13 μm gate length metal-oxide-semiconductor field effect transistor (Si MOSFET) with field-plate (FP) lengths of 0.1 μm, 0.2 μm, and 0.3 μm have been fabricated and investigated. The field-plate metals were connected to gate electrode in this study to improve device gate resistance (R_g) resulting in the better microwave performance. By increasing the length of field-plate metal extension (L_FPE), the off-state drain-to-source surface leakage current can be suppressed. Besides, low surface traps in FP NMOS also leads to a higher drain-to-source current (I_ds) especially at high current regime compared to standard device. The power added efficiency (PAE) was 56.3% for L_FPE of 0.3 μm device, and these values where 54.7% and 53.8% for L_FPE of 0.2 μm and 0.1 μm devices, respectively. Wider field-plate metal extension exhibits highly potential for low noise amplifier and high efficiency power amplifier applications.     

Identification of an RF degradation mechanism in GaN based HEMTs triggered by midgap traps

Quantitative defect spectroscopy was performed on low gate leakage operational S-band GaN HEMTs before and after RF accelerated life testing (ALT) to investigate and quantify potential connections between the evolution of observed traps and RF output power loss in these HEMTs after stressing. Constant drain current deep level transient spectroscopy and deep level optical spectroscopy (CI_D-DLTS and CI_D-DLOS, respectively) were used to interrogate thermally-emitting traps (CI_D-DLTS) and deeper optically-stimulated traps (CI_D-DLOS) so that the entire bandgap can be probed systematically before and after ALT. Using drain-controlled CI_D-DLTS/DLOS, with which traps in the drain access region are resolved, it is found that an increase in the concentration of a broad range of deep states between E_C–1.6 to 3.0 eV, detected by CI_D-DLOS, causes a persistent increase in on-resistance of ~ 0.22 Ω-mm, which is a likely source for the 1.2 dB reduction in RF output power that was observed after stressing. In contrast, the combined effect of the upper bandgap states at E_C–0.57 and E_C–0.72 eV, observed by CI_D-DLTS, is responsible for only ~ 10% of the on-resistance increase. These results demonstrate the importance of discriminating between traps throughout the entire bandgap with regard to the relative roles of individual traps on degradation of GaN HEMTs after ALT.     

Analysis of traps effect on AlGaN/GaN HEMT by luminescence techniques

The study is carried out on AlGaN/GaN HEMTs presenting current collapse effect at V_ds lower than 6 V. This effect is completely recovered by illuminating the component with light of 710 nm wavelength (1.75 eV). The spectral analysis of the light emission in the visible near infrared spectrum shows a bell-shape with superimposed distinct emission peaks. These features suggest that the electroluminescence (EL) signal is due to the direct intraband of electrons and inelastic intraband transition of electrons due to scattering by charged centres. Photoionisation experiments have been conducted to determine the light wavelengths/energies that separately change the drain current and the gate leakage current.     

Investigation of deep level defects in copper irradiated bipolar junction transistor

Commercial bipolar junction transistor (2N 2219A, npn) irradiated with 150 MeV Cu¹¹⁺-ions with fluence of the order 10¹² ions cm^?2, is studied for radiation induced gain degradation and deep level defects. I–V measurements are made to study the gain degradation as a function of ion fluence. The properties such as activation energy, trap concentration and capture cross-section of deep levels are studied by deep level transient spectroscopy (DLTS). Minority carrier trap levels with energies ranging from E_C ? 0.164 eV to E_C ? 0.695 eV are observed in the base–collector junction of the transistor. Majority carrier trap levels are also observed with energies ranging from E_V + 0.203 eV to E_V + 0.526 eV. The irradiated transistor is subjected to isothermal and isochronal annealing. The defects are seen to anneal above 350 °C. The defects generated in the base region of the transistor by displacement damage appear to be responsible for transistor gain degradation.     

HCS degradation of 5 nm oxide high-voltage PLDMOS

Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5 nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (V_GS) and high drain voltage (V_DS), reduction of the ON-resistance (R_ON) is observed. At stress times at which R_ON almost reaches its constant level, an increase of the drain leakage in OFF state (V_DS = −60 V, V_GS = 0 V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25 nm gate oxide thickness, the threshold voltage of 5 nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS.     

Influence of processing and annealing steps on electrical properties of InAlN/GaN high electron mobility transistor with Al2O3 gate insulation and passivation

We report on preparation and electrical characterization of InAlN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors (MOS HEMTs) with Al₂O₃ gate insulation and surface passivation. About 12 nm thin high-κ dielectric film was deposited by MOCVD. Before and after the dielectric deposition, the samples were treated by different processing steps. We monitored and analyzed the steps by sequential device testing. It was found that both intentional (ex situ) and unintentional (in situ before Al₂O₃ growth) InAlN surface oxidation increases the channel sheet resistance and causes a current collapse. Post deposition annealing decreases the sheet resistance of the MOS HEMT devices and effectively suppresses the current collapse. Transistors dimensions were source-to-drain distance 8 μm and gate width 2 μm. A maximum transconductance of 110 mS/mm, a drain current of ～0.6 A/mm (V_GS = 1 V) and a gate leakage current reduction from 4 to 6 orders of magnitude compared to Schottky barrier (SB) HEMTs was achieved for MOS HEMT with 1 h annealing at 700 °C in forming gas ambient. Moreover, InAlN/GaN MOS HEMTs with deposited Al₂O₃ dielectric film were found highly thermally stable by resisting 5 h 700 °C annealing.     

Strain sensitivity of gate leakage in strained-SOI nMOSFETs: A benefit for the performance trade-off and a novel way to extract the strain-induced band offset

The impact of biaxial stress on gate leakage is investigated on fully-depleted silicon-on-insulator (FD-SOI) nMOS transistors, integrating either a standard gate stack or an advanced high-κ/metal gate stack. It is demonstrated that strained devices exhibit significantly reduced leakage currents (up to ?90% at E_ox = 11 MV/cm for σ_tensile = 2.5 GPa). This specific effect is used to extract the conduction band offset ΔEc induced by strain and is shown to be accurate enough to monitor stress in MOSFETs. This new technique is much less sensitive to gate oxide defects than the method based on the threshold voltage shift ΔV_T. This accurate experimental extraction allowed us to pick out realistic values for the deformation potentials in silicon (Ξ_u = 8.5 eV and Ξ_d = ?5.2 eV), among the published values.     

Operational frequency degradation induced trapping in scaled GaN HEMTs

Cut-off frequency increase from 12.1 GHz to 26.4 GHz, 52.1 GHz and 91.4 GHz is observed when the 1 μm gate length GaN HEMT is laterally scaled down to L_G = 0.5 μm, L_G = 0.25 μm and L_G = 0.125 μm, respectively. The study is based on accurately calibrated transfer characteristics (I_D-V_GS) of the 1 μm gate length device using Silvaco TCAD. If the scaling is also performed horizontally, proportionally to the lateral (full scaling), the maximum drain current is reduced by 38.2% when the gate-to-channel separation scales from 33 nm to 8.25 nm. Degradation of the RF performance of a GaN HEMT due to the electric field induced acceptor traps experienced under a high electrical stress is found to be about 8% for 1 μm gate length device. The degradation of scaled HEMTs reduces to 3.5% and 7.3% for the 0.25 μm and 0.125 gate length devices, respectively. The traps at energy level of E_T = E_V + 0.9 eV (carbon) with concentrations of N_IT = 5 × 10¹⁶cm^− 3, N_IT = 5 × 10¹⁷cm^− 3 and N_IT = 5 × 10¹⁸cm^− 3 are located in the drain access region where highest electrical field is expected. The effect of traps on the cut-off frequency is reduced for devices with shorter gate lengths down to 0.125 μm.     

Investigation of deep level defects in electron irradiated indium arsenide quantum dots embedded in a gallium arsenide matrix

Gallium arsenide diodes with and without indium arsenide quantum dots were electron irradiated to investigate radiation induced defects. Baseline and quantum dot gallium arsenide pn-junction diodes were characterized by capacitance–voltage measurements, and deep level transient spectroscopy. Carrier accumulation was observed in the gallium arsenide quantum dot sample at the designed depth for the quantum dots via capacitance–voltage measurements. Prior to irradiation, a defect 0.84 eV below the conduction band (E_C – 0.84 eV) was observed in the baseline sample which is consistent with the native EL2 defect seen in gallium arsenide. After 1 MeV electron irradiation three new defects were observed in the baseline sample, labeled as E3 (E_C – 0.25 eV), E4 (E_C – 0.55 eV), and E5 (E_C – 0.76 eV), consistent with literature reports of electron irradiated gallium arsenide. Prior to irradiation, the addition of quantum dots appeared to have introduced defect levels at E_C – 0.21, E_C – 0.38, and E_C – 0.75 eV denoted as QD–DX1, QD–DX2, and QD–EL2 respectively. In the quantum dot sample after 1 MeV electron irradiation, QD–E3 (E_C – 0.28 eV), QD–E4 (E_C – 0.49 eV), and QD–EL2 (E_C – 0.72 eV) defects, similar to the baseline sample, were observed, although the trap density was dissimilar to that of the baseline sample. The quantum dot sample showed a higher density of the QD–E4 defect and a lower density of QD–E3, while the QD–EL2 defect seemed to be unaffected by electron irradiation. These findings suggest that the quantum dot sample may be more radiation tolerant to the E3 defect as compared to the baseline sample.     

Drivability improvement in Schottky barrier source/drain MOSFETs with strained-Si channel by Schottky barrier height reduction

Due to an extra barrier between source and channel, the drivability of Schottky barrier source/drain MOSFETs (SBMOSFETs) is smaller than that of conventional transistors. To reach the drivability comparable to the conventional MOSFET, the Schottky barrier height (SBH) should be lower than a critical value. It is expected that SBH can be effectively reduced by a bi-axially strain on Si. In this letter, p-channel MOSFETs with PtSi Schottky barrier source/drain, HfAlO gate dielectric, HfN/TaN metal gate and strained-Si channel are demonstrated for the first time using a simplified low temperature process. Devices with the channel length of 4 μm have the drain current of 9.5 μA/μm and the transconductance of 14 μS/μm at V_gs − V_th = V_ds = −1 V. Compared to the cubic Si counterpart, the drain current and the transconductance are improved up to 2.7 and 3.1 times respectively. The improvement is believed to arising from the reduced barrier height of the PtSi/strained-Si contact and the enhanced hole mobility in the strained-Si channel.     

Source/drain metallization effects on the specific contact resistance of indium tin zinc oxide thin film transistors

We report on the specific contact resistance of interfaces between thin amorphous semiconductor Indium Tin Zinc Oxide (ITZO) channel layers and different source/drain (S/D) electrodes (Al, ITO, and Ni) in amorphous oxide thin film transistors (TFTs) at different channel lengths using a transmission line model. All the contacts showed linear current–voltage characteristics. The effects of different channel lengths (200–800 μm, step 200 μm) and the contact resistance on the performance of TFT devices are discussed in this work. The Al/ITZO TFT samples with the channel length of 200 μm showed metallic behavior with a linear drain current-gate voltage (I_D–V_G) curve due to the formation of a conducting channel layer. The specific contact resistance (ρ_C) at the source or drain contact decreases as the gate voltage is increased from 0 to 10 V. The devices fabricated with Ni S/D electrodes show the best TFT characteristics such as highest field effect mobility (16.09 cm²/V·s), ON/OFF current ratio (3.27×10⁶), lowest sub-threshold slope (0.10 V/dec) and specific contact resistance (8.62 Ω·cm² at V_G=0 V). This is found that the interfacial reaction between Al and a-ITZO semiconducting layer lead to the negative shift of threshold voltage. There is a trend that the specific contact resistance decreases with increasing the work function of S/D electrode. This result can be partially ascribed to better band alignment in the Ni/ITZO interface due to the work function of Ni (5.04–5.35 eV) and ITZO (5.00–6.10 eV) being somewhat similar.     

N2O treatment enhancement-mode InAlN/GaN HEMTs with HfZrO2 High-k insulator

A normally-off InAlN/GaN MIS-HEMT with HfZrO₂ gate insulator was realized and investigated. By using N₂O plasma treatment beneath the gate region, 13 nm InAlN Schottky layer was oxidized to AlON_x + 4 nm InAlN Schottky layer. The strong polarization induced carriers in traditional InAlN/GaN 2 DEG quantum well was reduced for enhancement-mode operation. High-k thin film HfZrO₂ was used for gate insulator of E-mode device to further suppress gate leakage current and enhance device gate operation range. The maximum drain current of E-mode InAlN/GaN MIS-HEMT was 498 mA/mm and this value was higher than previous published InAlN/GaN E-mode devices. The measurement results of low-frequency noise also concluded that the low frequency noise is attributed to the mobility fluctuation of the channel and N₂O plasma treatment did not increase fluctuation center of gate electrode.     

Compositional dependence of work function and Fermi level position of the HfNx/SiO2 system

In situ Kelvin Probe (KP) measurements performed on HfN_x showed an increase of the vacuum work function as a function of N content from a value of 3.9 eV (silicon conduction band edge) for pure Hf to a value of 5 eV (silicon valence band edge) for x ～ 2. In contrast, capacitance–voltage (C–V) measurements showed that the effective work function increased only until x < 1 and saturated around a value of 4.6 eV (silicon midgap). This behavior is attributed to Fermi level pinning, which is probably due to oxidation of the HfN_x during the reactive sputtering deposition step.     

Blue/green luminescence based on Zn(S)Se/GaAs heterostructures

Substantial advances have been realized in the aim to achieve blue–green light emitting devices based on Zn(S)Se wide band gap II–VI semi-conductor materials. Two light emitting diodes p on n and n on p heterostructures were grown on GaAs substrate by molecular beam epitaxy. The active layer was a single ZnCdSe quantum well, with ZnSSe guiding layers and ZnSe cladding layers. p-GaInP, p-AlGaAs and p-CdZnSe buffer layers were deposited at the p-ZnSe/GaAs interface to reduce the valence band offset in the case of n on p heterostructures. Electrical and optical properties were investigated using current voltage, capacitance voltage, electroluminescence, photoluminescence and photocurrent measurements at room temperature. Blue–green luminescence centered at 516.7 nm is observed. The highest luminescence intensity is observed under 7 V forward bias. Photoluminescence spectrum shows two wide peaks at 2.2 and 1.9 eV energies. These energies are attributed to the transitions between ZnSe and GaAs conduction bands and the deep level at E_v−0.6 eV. Absorption process from ZnSe and ZnSSe conduction bands to the shallow nitrogen acceptor level (2.6 and 2.8 eV, respectively) have been observed using photocurrent measurements. From these results we present a band alignment diagram which confirms the presence of the two levels at 0.1 and 0.6 eV from the valence band of ZnSe.     

Self-aligned inversion n-channel In0.2Ga0.8As/GaAs metal–oxide–semiconductor field-effect-transistors with TiN gate and Ga2O3(Gd2O3) dielectric

A self-aligned process for fabricating inversion n-channel metal–oxide–semiconductor field-effect-transistors (MOSFET’s) of strained In_0.2Ga_0.8As on GaAs using TiN as gate metal and Ga₂O₃(Gd₂O₃) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at V_g = 4 V and V_d = 2 V, a low gate leakage of <10^?7 A/cm² at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at V_g = 3 V, V_d = 2 V, and an on/off ratio of ～10⁵ in drain current. For comparison, a TiN/Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10^?8–10^?9 A/cm², well-behaved capacitance–voltage (C–V) characteristics giving a high dielectric constant of ～16 and a low interfacial density of state of ～(2～6) × 10¹¹ cm^?2 eV^?1, and an atomically sharp smooth Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As interface.     

A detailed comparative study on the main electrical parameters of Au/n-Si and Au/PVA:Zn/n-Si Schottky barrier diodes

We have fabricated Au/n-Si and Au/PVA:Zn/n-Si Schottky barrier diodes (SBDs) to investigate the effect of organic interfacial layer on the main electrical characteristics. Zn doped poly(vinyl alcohol) (PVA:Zn) was successfully deposited on n-Si substrate by using the electrospinning system and surface morphology of PVA:Zn was presented by SEM images. The current–voltage (I–V) characteristics of these SBDs have been investigated at room temperature. The experimental results show that interfacial layer enhances the device performance in terms of ideality factor (n), zero-bias barrier height (Φ_B0), series resistance (R_s), and shunt resistance (R_sh) with values of 1.38, 0.75 eV, 97.64 Ω, and 203 MΩ whereas those of Au/n-Si SBD are found as 1.65, 0.62 eV, 164.15 Ω and 0.597 MΩ, respectively. Also, this interfacial layer at metal/semiconductor (M/S) interface leads to a decrease in the magnitude of leakage current and density of interface states (N_ss). The values of N_ss range from 1.36×10¹² at E_c—0.569 eV to 1.35×10¹³ eV^?1 cm^?2 at E_c—0.387 eV for Au/PVA:Zn/n-Si SBD and 3.34×10¹² at E_c—0.560 eV to 1.35×10¹³ eV^?1 cm^?2 at E_c—0.424 eV for Au/n-Si SBD. The analysis of experimental results reveals that the existence of PVA:Zn interfacial layer improves the performance of such devices.     

Low-voltage,high speed inkjet-printed flexible complementary polymer electronic circuits

We report the development of high-performance inkjet-printed organic field-effect transistors (OFETs) and complementary circuits using high-k polymer dielectric blends comprising poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) and poly(methyl methacrylate) (PMMA) for high-speed and low-voltage operation. Inkjet-printed p-type polymer semiconductors containing alkyl-substituted thienylenevinylene (TV) and dodecylthiophene (PC12TV12T) and n-type P(NDI2OD-T2) OFETs showed high field-effect mobilities of 0.1–0.4 cm² V^?1 s^?1 and low threshold voltages down to 5 V. These OFET properties were modified by changing the blend ratio of P(VDF-TrFE) and PMMA. The optimum blend – a 7:3 wt% mixture of P(VDF-TrFE) and PMMA – was successfully used to realize high-performance complementary inverters and ring oscillators (ROs). The complementary ROs operated at a supplied bias (V_DD) of 5 V and showed an oscillation frequency (f_osc) as high as ～80 kHz at V_DD = 30 V. Furthermore, the f_osc of the complementary ROs was significantly affected by a variety of fundamental parameters such as the electron and hole mobilities, channel width and length, capacitance of the gate dielectrics, V_DD, and the overlap capacitance in the circuit configuration.     

A high-yield vacuum-evaporation-based R2R-compatible fabrication route for organic electronic circuits

Advances are described in a vacuum-evaporation-based approach for the roll-to-roll (R2R) production of organic thin film transistors (TFTs) and circuits. Results from 90-transistor arrays formed directly onto a plasma-polymerised diacrylate gate dielectric are compared with those formed on polystyrene-buffered diacrylate. The latter approach resulted in stable, reproducible transistors with yields in excess of 90%. The resulting TFTs had low turn-on voltage, on–off ratios ∼10⁶ and mobility ∼1 cm²/V s in the linear regime, as expected for dinaphtho[2,3-b:2′,3′-f] thieno[3,2-b]thiophene the air stable small molecule used as the active semiconductor. We show that when device design is constrained by the generally poor registration ability of R2R processes, parasitic source–drain currents can lead to a >50% increase in the mobility extracted from the resulting TFTs, the increases being especially marked in low channel width devices. Batches of 27 saturated-load inverters were fabricated with 100% yield and their behaviour successfully reproduced using TFT parameters extracted with Silvaco’s UOTFT Model. 5- and 7-stage ring oscillator (RO) outputs ranged from ∼120 Hz to >2 kHz with rail voltages, V_DD, increasing from −15 V to −90 V. From simulations an order of magnitude increase in frequency could be expected by reducing parasitic gate capacitances. During 8 h of continuous operation at V_DD = −60 V, the frequency of a 7-stage RO remained almost constant at ∼1.4 kHz albeit that the output signal amplitude decreased from ∼22 V to ∼10 V. Over the next 30 days of intermittent operation further degradation in performance occurred although an unused RO showed no deterioration over the same period.     

Gain improvement and microwave operation of 4H–SiC MESFET with a new recessed metal ring structure

A new multi-recessed 4H-SiC MESFET with recessed metal ring for RF embedded circuits is proposed (MR2-MESFET). The key idea in the proposed structure is based on the elimination of the spaces adjacent to gate and stopped the depletion region extending towards drain and source and the reduction of the channel thickness between gate and drain to increase breakdown voltage (V_BR); meanwhile the elimination of the gate depletion layer extension to source/drain to decrease gate-source capacitance (C_gs). The influence of multi-recessed drift region and recessed metal ring structures on the characteristics of the MR2-MESFET is studied by numerical simulation. The optimized results show that the V_BR of the MR2-MESFET is 119% larger than that of the conventional 4H–SiC MESFET (C-MESFET); meanwhile maintain 85% higher saturation drain current. Therefore, the maximum output power density of the MR2-MESFET is 23.1 W/mm compared to 5.5 W/mm of the C-MESFET. Also, the cut-off frequency (f_T) and the maximum oscillation frequency (f_max) of 24.9 and 91.7 GHz are obtained for the MR2-MESFET compared to 11 and 40 GHz of the C-MESFET structure, respectively. The proposed MR2-MESFET shows a maximum stable gain (MSG) exceeding 23.6 dB at 3.1 GHz which is the highest gain yet reported for SiC MESFETs, showing the potential of this device for high power RF applications.