GaN-based HEMTs tested under high temperature storage test

In this work, the impact of 1000 h thermal storage test at 325 °C on the performance of gallium nitride high electron mobility transistors grown on Si substrates (GaN-on-Si HEMTs) is investigated. The extensive DC- and pulse-characterization performed before, during and after the stress did not reveal degradation on the channel conduction properties as well as formation of additional trapping states. The failure investigation has shown that only the gate and drain leakage currents were strongly affected by the high temperature storage test. The physical failure analysis revealed a Au inter-diffusion phenomenon with Ni at the gate level, resulting in a worsening of the gate–AlGaN interface. It is speculated that this phenomenon is at the origin of the gate and drain leakage current increasing.     

Operational frequency degradation induced trapping in scaled GaN HEMTs

Cut-off frequency increase from 12.1 GHz to 26.4 GHz, 52.1 GHz and 91.4 GHz is observed when the 1 μm gate length GaN HEMT is laterally scaled down to L_G = 0.5 μm, L_G = 0.25 μm and L_G = 0.125 μm, respectively. The study is based on accurately calibrated transfer characteristics (I_D-V_GS) of the 1 μm gate length device using Silvaco TCAD. If the scaling is also performed horizontally, proportionally to the lateral (full scaling), the maximum drain current is reduced by 38.2% when the gate-to-channel separation scales from 33 nm to 8.25 nm. Degradation of the RF performance of a GaN HEMT due to the electric field induced acceptor traps experienced under a high electrical stress is found to be about 8% for 1 μm gate length device. The degradation of scaled HEMTs reduces to 3.5% and 7.3% for the 0.25 μm and 0.125 gate length devices, respectively. The traps at energy level of E_T = E_V + 0.9 eV (carbon) with concentrations of N_IT = 5 × 10¹⁶cm^− 3, N_IT = 5 × 10¹⁷cm^− 3 and N_IT = 5 × 10¹⁸cm^− 3 are located in the drain access region where highest electrical field is expected. The effect of traps on the cut-off frequency is reduced for devices with shorter gate lengths down to 0.125 μm.     

Field- and current-driven degradation of GaN-based power HEMTs with p-GaN gate: Dependence on Mg-doping level

Within this paper we investigate the degradation of GaN-HEMTs with p-GaN gate submitted to stress at forward gate bias. We studied the effect of both constant-voltage stress and short-pulse stress (induced by TLP, Transmission Line Pulser); devices having three different Mg-doping levels (ranging from 2.1 · 10¹⁹/cm³ to 2.9 · 10¹⁹/cm³) were used for the study.We demonstrated the existence of two different degradation mechanisms, depending on the stress conditions: (i) when submitted to TLP stress (100 ns pulses with increasing amplitude), the failure occurs through a field-driven process, i.e. the breakdown of the metal/p-GaN Schottky junction, which is reversely biased when the gate is at positive voltage. Failure voltage decreases with increasing Mg doping, since higher acceptor levels result in a higher electric field. (ii) Conversely, during constant-voltage stress, the long-term stability is undermined by a current-driven process, namely the accumulation of positive charges at the p-GaN/AlGaN interface, which promotes an increase of the leakage current, first gradual and then catastrophic. Increasing Mg-concentration in the p-GaN results in a reduction of the gate leakage at high forward gate bias. As a consequence, devices with higher Mg doping have long TTF (more than two orders of magnitude with respect to the samples with lower Mg doping).     

New degradation mechanism observed for AlGaN/GaN HEMTs with sub 100 nm scale unpassivated regions around the gate periphery

AlGaN/GaN HEMTs with low gate leakage current in the μA/mm range have been fabricated with a small-unpassivated region close to the gate foot. They showed considerably higher critical voltage values (average VCR = 60 V) if subjected to step stress testing at OFF-state conditions and room temperature as compared to standard devices with conventional gate technology. This is due to the fact that electrons injected from the gate can be accumulated at the unpassivated region and thus builds up negative charge. The lower gate leakage is due to virtual gate formation, which is reducing local electric field in the vicinity of the gate. In contrast to devices with standard gate technology, degradation during step stressing is not associated with a simultaneous gate leakage and drain leakage current increase but with a strong increase of drain current at OFF-state conditions while the gate leakage is practically not affected. Then a relatively higher critical voltage of around 60 V is achieved. An abrupt increase of subthreshold drain current implies the formation of a conductive channel bypassing the gate region without influencing gate leakage. It is believed that hopping conductivity via point defects formed during device stressing creates this channel. Once this degradation mode takes place, the drain current of affected devices significantly drops. This can be explained by negative trap formation in the channel region affecting the total charge balance in 2DEG region. Electroluminescence measurements on both fresh and degraded devices showed no hot spots at OFF-state conditions. However, there is additional emission at ON-state bias, which suggests additional energetic states that lead to radiative electron transition effects in the degraded devices, most possibly defect states in the buffer.     

HCS degradation of 5 nm oxide high-voltage PLDMOS

Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5 nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (V_GS) and high drain voltage (V_DS), reduction of the ON-resistance (R_ON) is observed. At stress times at which R_ON almost reaches its constant level, an increase of the drain leakage in OFF state (V_DS = −60 V, V_GS = 0 V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25 nm gate oxide thickness, the threshold voltage of 5 nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS.     

NBTI degradation effect on advanced-process 45 nm high-k PMOSFETs with geometric and process variations

Negative bias temperature instability (NBTI) has become an important reliability concern for nano-scaled complementary metal oxide (CMOS) devices. This paper presents the effect of NBTI for a 45 nm advanced-process high-k dielectric with metal gate PMOS transistor. The device had incorporated advanced-process flow steps such as stress engineering and laser annealing in order to achieve high on-state drain current drive performance. To explore NBTI effects on an advanced-process sub-micron device, the 45 nm high-k PMOS transistor was simulated extensively with a wide range of geometric and process variations. The device was simulated at varying thicknesses in the dielectric layer, oxide interfacial layer, metal gate and polysilicon layer. In order to observe the NBTI effect on process variation, the NBTI degradation of the 45 nm advanced-process PMOS is compared with a 45 nm PMOS device which does not employ process-induced stress and incorporates the conventional rapid thermal annealing (RTA) as compared to the laser annealing process which is integrated in the advanced-process device flow. The simulation results show increasing degradation trend in terms of the drain current and threshold voltage shift when the thicknesses of the dielectric layer, oxide layer as well as the metal gate are increased.     

Charge trapping related channel modulation instability in P-GaN gate HEMTs

In this paper, a study of the channel modulation instability of commercial p-GaN gate HEMTs is presented. During the gate-voltage stress test, substantial R_DS(ON) variations up to 78 mΩ (93.8%) were observed. It is found that the p-GaN/AlGaN/GaN gate structure enables the injection of holes and electrons, which can be captured by the donor/acceptor-like traps located in the AlGaN layer. Therefore, the trapped holes and electrons concurrently modulate the channel conductivity, resulting in R_DS(ON) variations. Device simulation was performed to help explain the mechanism from the perspective of energy band. In addition, results reveal that with the recommended working gate-voltage stress V_GS = 7 V, the on-state resistance, the threshold voltage and the off-state drain to source leakage current vary up to 8 mΩ (16.3%), 0.2 V (14.8%) and 12.8 μA (42.66%) within 1 h, respectively, which could raise reliability issues for the power electronics applications of p-GaN gate HEMTs.     

Study of the breakdown failure mechanisms for power AlGaN/GaN HEMTs implemented using a RF compatible process

The breakdown failure mechanisms for a family of power AlGaN/GaN HEMTs were studied. These devices were fabricated using a commercially available MMIC/RF technology with a semi-insulating SiC substrate. After a 10 min thermal annealing at 425 K, the transistors were subjected to temperature dependent electrical characteristics measurement. Breakdown degradation with a negative temperature coefficient of ?0.113 V/K for the devices without field plate was found. The breakdown voltage is also found to be a decreasing function of the gate length. Gate current increases simultaneously with the drain current during the drain-voltage stress test. This suggests that the probability of a direct leakage current path from gate to the 2-DEG region. The leakage current is attributed by a combination of native and generated traps/defects dominated gate tunneling, and hot electrons injected from the gate to channel. Devices with field plate show an improvement in breakdown voltage from ～40 V (with no field plate) to 138 V and with lower negative temperature coefficient. A temperature coefficient of ?0.065 V/K was observed for devices with a field plate length of 1.6 μm.     

Electrical characterization and reliability of submicron SOI CMOS technology in the extended temperature range (to 300 °C)

I-V characteristics and reliability parameters for the set of hardened SOI MOSFET's with special layouts and tungsten metallization to provide additional thermal tolerance for high-temperature SOI CMOS IC's are investigated in the temperature range up to 300 °C. The reliability aspects under test for MOSFET's are threshold voltage shift, subthreshold slope and mobility degradation, gate leakage current rise; for tungsten metallization (contacts, conductor lines and vias) I-T and R-T characteristics, failure time. The SOI MOSFET standard compact SPICE model BSIMSOI with traditional temperature limit of 150 °C is modified to be used for CMOS IC simulation in the extended temperature range up to 300 °C. The results indicate that the 0.5–0.18 μm SOI MOSFET's with tungsten metallization have stable electrical behavior that makes them possible to be used during implementation of HT CMOS IC's (to 300 °C).     

Positive bias temperature instabilities on sub-nanometer EOT FinFETs

PBTI degradation on FinFETs with HfO₂/TiN gate stack (EOT < 1 nm) is studied. Thinner TiN layer decreases interfacial oxide thickness, and reduces PBTI lifetime. This behavior is consistent with the results in planar devices. Corner rounding effect on PBTI is also analyzed. Finally, charge pumping measurements on devices with several fin widths devices apparently show a higher density of defects in the top-wall high-κ oxide than in the sidewall of the fin. This could explain more severe PBTI degradation.     

Improved reliability of AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) with high density silicon nitride passivation

We have systematically studied the effects of Si_xN_1 − x passivation density on the reliability of AlGaN/GaN high electron mobility transistors. Upon stressing, devices degrade in two stages, fast-mode degradation and followed by slow-mode degradation. Both degradations can be explained as different stages of pit formation at the gate-edge. Fast-mode degradation is caused by pre-existing oxygen at the Si_xN_1 − x/AlGaN interface. It is not significantly affected by the Si_xN_1 − x density. On the other hand, slow-mode degradation is associated with Si_xN_1 − x degradation. Si_xN_1 − x degrades through electric-field induced oxidation in discrete locations along the gate-edges. The size of these degraded locations ranged from 100 to 300 nm from the gate edge. There are about 16 degraded locations per 100 μm gate-width. In each degraded location, low density nano-globes are formed within the Si_xN_1 − x. Because of the low density of the degraded locations, oxygen can diffuse through these areas and oxidize the AlGaN/GaN to form pits. This slow-mode degradation can be minimized by using high density (ρ = 2.48 g/cm³) Si₃₆N₆₄ as the passivation layer. For slow-mode degradation, the median time to failure of devices with high density passivation is found to increase up to 2× as compared to the low density (ρ = 2.25 g/cm³) Si₄₃N₅₇ passivation. A model based on Johnson-Mehl-Avrami theory is proposed to explain the kinetics of pit formation.     

Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET

Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide (SiO₂) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt to characterize the analog and RF performance of the high-k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2-D device simulation. The results demonstrates the impact of high-k oxide layer as single and gate stack (GS). The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performance exhibited by the device. The major figures of merit (FOMs) studied in this paper are transconductance (g_m), output conductance (g_d), transconductance generation factor (g_m/I_D), early voltage (V_EA), intrinsic gain (A_V), cut off frequency (f_T), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). The effects of downscaling of channel length (L) on analog performance of the proposed devices have also been presented. It has been observed that the performance enhancement of GS configurations (k=7.5 i.e device D5 in the study) is encouraging as far as the nanoscale DG-MOSFET is concerned. Also it significantly reduces the short channel effects (SCEs). Parameters like DC gain of (91.257 dB, 43.436 dB), nearly ideal values (39.765 V⁻¹, 39.589 V⁻¹) of TGF, an early voltage of (2.73 V, 16.897 V), cutoff frequency (294 GHz, 515.5 GHz) and GTFP of (5.14×10⁵ GHz/V, 1.72×10⁵ GHz/V) for two different values of V_DS=0.1 V and 0.5 V respectively are found to be close to ideal values. Analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper i.e. device D5.     

New insight on negative bias temperature instability degradation with drain bias of 28 nm High-K Metal Gate p-MOSFET devices

The degradation of negative bias temperature instability (NBTI) on 28 nm High-K Metal Gate (HKMG) p-MOSFET devices under non-uniform stress condition has been systematically studied. We found the asymmetry between forward and reverse Idsat shift under non-uniform stress condition is significant for long channel devices even under low drain bias stress (e.g., Vds = −0.1 V and gate channel length L = 1 μm), and seems to be dominated by a minimally required critical length (L = 0.2 μm derived from the experimental data). To the authors’ best knowledge, these are new phenomena reported. We attribute these anomalous NBTI characteristics with drain bias to the local self-heating (LSH) activated NBTI degradation mechanism. One semi-empirical analytical model, which fits well with our experimental data, is then proposed in this paper.     

Effect of gate length in InAs/AlSb HEMTs biased for low power or high gain

The effect of gate-length variation on DC and RF performance of InAs/AlSb HEMTs, biased for low DC power consumption or high gain, is reported. Simultaneously fabricated devices, with gate lengths between 225 nm and 335 nm, have been compared. DC measurements revealed higher output conductance g_ds and slightly increased impact ionization with reduced gate length. When reducing the gate length from 335 nm to 225 nm, the DC power consumption was reduced by approximately 80% at an f_T of 120 GHz. Furthermore, a 225 nm gate-length HEMT biased for high gain exhibited an extrinsic f_T of 165 GHz and an extrinsic f_max of 115 GHz, at a DC power consumption of 100 mW/mm. When biased for low DC power consumption of 20 mW/mm the same HEMT exhibited an extrinsic f_T and f_max of 120 GHz and 110 GHz, respectively.     

Investigation on the thermal behavior of 0.15 μm gate-length In0.4Al0.6As/In0.4Ga0.6As MHEMT

In this study, we have successfully investigated the electrical performances of In_0.4Al_0.6As/In_0.4Ga_0.6As metamorphic high-electron-mobility transistor (MHEMT) at temperatures range from 275 K to 500 K comprehensively. By extracting the device S-parameters, the temperature dependent small signal model has been established. At room temperature, 0.15 μm T-gate device with double δ-doping design exhibits f_T and f_MAX values of 103 GHz and 204 GHz at V_ds = 1 V, an extrinsic transconductance of 678 mS/mm, and a current density of 578 mA/mm associated with a high breakdown voltage of ?13 V. Power measurements were evaluated at 40 GHz and the measured output power, linear power gain, and maximum power-added efficiency, were 7.12 dBm, 10.15 dB, and 23.1%, respectively. The activation energy (E_a) extracted from Arrhenius plots is = 0.34 eV at 150 ≦ T ≦ 350 K. The proposed device is promisingly suitable for millimeter-wave power application.     

Field and hot electron-induced degradation in GaN-based power MIS-HEMTs

We investigate the degradation of AlGaN/GaN MIS-HEMTs submitted to gate step-stress experiments, and demonstrate the existence of field- and hot-electron induced processes. When the devices are submitted to gate-step stress with high V_DS > 50 V, four different regimes are identified: (i) for V_GS < − 10 V, no significant degradation is observed, since the devices are in the off-state; (ii) for − 10 V < V_GS < 0 V, hot electrons flow through the channel, as demonstrated by the (measurable) electroluminescence signal. These hot electrons can be trapped within device structure, inducing an increase in the threshold voltage. (iii) for V_GS > 0 V, the density of hot electrons is significantly reduced, due to the increased interface scattering and device temperature. As a consequence, EL signal drops to zero, and the electrons trapped during phase (ii) are de-trapped back to the channel, where they are attracted by the high 2DEG potential. (iv) Finally, for V_GS > 5 V, a significant increase in threshold voltage is detected. This effect is observed only for high positive voltages, i.e. when a significant leakage current flows through the gate. Such gradual degradation is ascribed to the injection of electrons from the 2DEG to the gate insulator, which is a field-driven effect. These results were obtained by combined electrical and optical characterization carried out at different voltages during the step stress.     

Fabrication of high-speed InP/InGaAs/InP DHBT with a new self-aligned metallization technique for reduced base resistance

A new self-aligned emitter–base metallization (SAEBM) technique with wet etch is developed for high-speed heterojunction bipolar transistors (HBTs) by reducing extrinsic base resistance. After mesa etch of the base layer using a photo-resist mask, the base and emitter metals are evaporated simultaneously to reduce the emitter–base gap (S_EB) and base gap resistance (R_GAP). The InP/InGaAs/InP double heterojunction bipolar transistor (DHBT) fabricated using the technique has a reduced R_GAP, from 16.48 Ω to 4.62 Ω comparing with the DHBT fabricated by conventional self-aligned base metallization (SABM) process. Furthermore, we adopt a novel collector undercut technique using selective etching nature of InP and InGaAs to reduce collector–base capacitance (C_CB). Due to the reduced R_GAP, the maximum oscillation frequency (f_max) for a 0.5 μm-emitter HBT is improved from 205 GHz to 295 GHz, while the cutoff frequency (f_T) is maintained at around 300 GHz.     

Source/drain metallization effects on the specific contact resistance of indium tin zinc oxide thin film transistors

We report on the specific contact resistance of interfaces between thin amorphous semiconductor Indium Tin Zinc Oxide (ITZO) channel layers and different source/drain (S/D) electrodes (Al, ITO, and Ni) in amorphous oxide thin film transistors (TFTs) at different channel lengths using a transmission line model. All the contacts showed linear current–voltage characteristics. The effects of different channel lengths (200–800 μm, step 200 μm) and the contact resistance on the performance of TFT devices are discussed in this work. The Al/ITZO TFT samples with the channel length of 200 μm showed metallic behavior with a linear drain current-gate voltage (I_D–V_G) curve due to the formation of a conducting channel layer. The specific contact resistance (ρ_C) at the source or drain contact decreases as the gate voltage is increased from 0 to 10 V. The devices fabricated with Ni S/D electrodes show the best TFT characteristics such as highest field effect mobility (16.09 cm²/V·s), ON/OFF current ratio (3.27×10⁶), lowest sub-threshold slope (0.10 V/dec) and specific contact resistance (8.62 Ω·cm² at V_G=0 V). This is found that the interfacial reaction between Al and a-ITZO semiconducting layer lead to the negative shift of threshold voltage. There is a trend that the specific contact resistance decreases with increasing the work function of S/D electrode. This result can be partially ascribed to better band alignment in the Ni/ITZO interface due to the work function of Ni (5.04–5.35 eV) and ITZO (5.00–6.10 eV) being somewhat similar.     

Lithography scaling issues associated with III–V MOSFETs

In this work we investigate fabrication issues associated with scaling down the gate length and source drain contact separation of a III–V MOSFET. We used high resolution electron-beam lithography and lift-off for gate and ohmic contact patterning to fabricate gate-last lithographically-aligned MOSFETs. This work considers the effect of variations in resist thickness on gate lengths and also the fabrication of long narrow gaps using electron-beam lithography. The study showed that the effect of resist thickness variation on metal linewidth is insignificant. A difference of around 2–3 nm was found between PtAu linewidths fabricated using 150 and 280 nm thick resist. A VB6 lithography tool was found to be useful for linewidth measurements. We showed that the choice of resist is critical to gap formation, and that PMMA is not well suited to this task.