Impact of strain and source/drain engineering on the low frequency noise behaviour in n-channel tri-gate FinFETs

The impact of strain-engineering on the low frequency of n-channel tri-gate FinFETs fabricated on silicon on insulator (SOI) substrates noise is reported. The work is first focused on the study of nFinFETs with a standard structure and with strain-engineered channel structures, using either global or local straining techniques, or a combination of both. A carrier number fluctuation dominant flicker noise has been observed for all devices. Whereas no clear correlation between the applied strain techniques and the 1/f noise level has been found, an unusual noise spectral density was observed for the devices with selective epitaxial grown (SEG) source and drain regions. This unusual noise behaviour has been investigated for different fin widths (0.15 μm up to 3 μm) and different temperature conditions (150 K up to 300 K). An empirical model is proposed in order to explain this unusual noise behaviour. Moreover, two Lorentzians attributed to defects in the depletion region of the silicon fin were observed, and energy level and cross-section of these defects were estimated.     

Study of microwave damage effect on HEMT low noise amplifier under different drain voltage bias

The microwave damage effect on high electron mobility transistor (HEMT) low noise amplifier (LNA) under different drain voltage bias is studied using TCAD simulation and experiments. Simulation and experimental results suggest that the damage power thresholds and damage locations of single stage LNA under different drain voltage bias are almost the same. Nevertheless, the output power under zero drain bias is about 5.6 dB higher than it under normal (3 V) drain bias with the injection of large power microwave pulses. In Addition, the output power relative to it under normal drain bias decreases linearly with the increase of drain bias, following the function of P_dB = − 1.85V_ds + 5.7. For multi-stage LNA, the observation using optical microscope reveals that the first and second stage HEMT of LNA under zero drain bias are both damaged while only first stage HEMT of LNA under normal bias is damaged with the injection of same large power microwave pulses, which is consistent with simulated output characteristics results.     

Analysis of origin of measured 1/f noise in high-power semiconductor laser diodes far below threshold current

The 1/f noise is measured under the bias one tenth the threshold current of the InGaAs quantum well high-power semiconductor laser diodes (LDs). The noise origin is analyzed using the current and voltage 1/f noise and dynamic resistance characteristics. Then the relationship between the noise and the internal defect is analyzed according to the differences of LDs in the noise intensity and the fluctuation near the initial electrical derivative peak. The result shows that with currents 0.13 mA–1 mA, the dynamic resistance of the LDs is in the magnitude of hundreds of ohms, when the changing rates of both the noise intensity and the resistance reflect the typical features of the active region, while with currents 8 mA–32 mA, the dynamic resistance drops under 10 Ω and its changing rate slows down, when the 1/f noise intensity trend shows the features of the contact resistance. Moreover, the electrical derivative of LDs with weaker noise fluctuates milder and has more conspicuous initial peaks, while the electrical derivative of other LDs fluctuates acuter and hardly shows distinct initial peaks. The results indicate that the 1/f noise from the active region can be measured under bias currents far lower than the threshold currents of the LDs, and it can indicate the defects in the active region and further the reliability of the device.     

N2O treatment enhancement-mode InAlN/GaN HEMTs with HfZrO2 High-k insulator

A normally-off InAlN/GaN MIS-HEMT with HfZrO₂ gate insulator was realized and investigated. By using N₂O plasma treatment beneath the gate region, 13 nm InAlN Schottky layer was oxidized to AlON_x + 4 nm InAlN Schottky layer. The strong polarization induced carriers in traditional InAlN/GaN 2 DEG quantum well was reduced for enhancement-mode operation. High-k thin film HfZrO₂ was used for gate insulator of E-mode device to further suppress gate leakage current and enhance device gate operation range. The maximum drain current of E-mode InAlN/GaN MIS-HEMT was 498 mA/mm and this value was higher than previous published InAlN/GaN E-mode devices. The measurement results of low-frequency noise also concluded that the low frequency noise is attributed to the mobility fluctuation of the channel and N₂O plasma treatment did not increase fluctuation center of gate electrode.     

Comparative study of low-frequency noise in 0.18 μm and 0.35 μm gate-length nMOSFETs with gate area of 1.1 μm2

We analyzed the noise characteristics of 0.18 μm and 0.35 μm nMOSFETs with a gate area of 1.1 μm² in the frequency range of 1 Hz to 100 kHz. Both two- and four-finger devices were investigated and analyzed. The experimental results show that the noise of 0.35 μm gate-length nMOSFET possesses lower 1/f component than the 0.18 μm one, whereas the four-finger devices reveal less 1/f noise than those of with two-finger ones. Furthermore, we used time domain measurement of drain current and also the statistical analysis of wafer level on the random telegraph signals (RTS) tests, and the results showed that RTS noise is higher in devices with a 0.35 μm gate-length, and devices with a smaller gate finger width produce more RTS noise than devices with a larger gate finger width.     

Gain improvement and microwave operation of 4H–SiC MESFET with a new recessed metal ring structure

A new multi-recessed 4H-SiC MESFET with recessed metal ring for RF embedded circuits is proposed (MR2-MESFET). The key idea in the proposed structure is based on the elimination of the spaces adjacent to gate and stopped the depletion region extending towards drain and source and the reduction of the channel thickness between gate and drain to increase breakdown voltage (V_BR); meanwhile the elimination of the gate depletion layer extension to source/drain to decrease gate-source capacitance (C_gs). The influence of multi-recessed drift region and recessed metal ring structures on the characteristics of the MR2-MESFET is studied by numerical simulation. The optimized results show that the V_BR of the MR2-MESFET is 119% larger than that of the conventional 4H–SiC MESFET (C-MESFET); meanwhile maintain 85% higher saturation drain current. Therefore, the maximum output power density of the MR2-MESFET is 23.1 W/mm compared to 5.5 W/mm of the C-MESFET. Also, the cut-off frequency (f_T) and the maximum oscillation frequency (f_max) of 24.9 and 91.7 GHz are obtained for the MR2-MESFET compared to 11 and 40 GHz of the C-MESFET structure, respectively. The proposed MR2-MESFET shows a maximum stable gain (MSG) exceeding 23.6 dB at 3.1 GHz which is the highest gain yet reported for SiC MESFETs, showing the potential of this device for high power RF applications.     

Scaling behaviors of transient noise current in organic field-effect transistors

Top-contact and bottom-gate organic field-effect transistors (OFETs) based on poly(3-hexylthiophene), P3HT polymer has been fabricated with thermal treatment condition. Transient noise currents of the OFETs are measured at various source–drain voltages ranging from 0 V to ?60 V with respect to a fixed gate voltage of ?60 V. The results from conventional power spectral density method are compared with the more robust Detrended Fluctuation Analysis. The latter has been proven to be reliable for fractal signals particularly in the presence of nonstationary effects. Interesting transitions between multiscaling and monoscaling behaviors are observed in the power spectral density as well as the Detrended Fluctuation Analysis plots for different applied source–drain voltage V_ds. Uncorrelated white noise characteristics are observed for noise current measured at low V_ds, meanwhile 1/f noise-like scaling behaviors are observed at intermediate V_ds. At higher V_ds, the noise characteristics appeared to be close to Brownian-like power-law behavior. The scaling characteristics of the transient noise current can be related to the charge carrier dynamics. It is also found that large numbers of trap centers are induced when the device is stressed at high applied V_ds. The existence of these trap centers would disperse charge carriers, leading to 1/f type noise that could diminish the presence of Brownian noise in a very short time.     

Low frequency noise spectroscopy in InAs/GaAs resonant tunneling quantum dot infrared photodetectors

We have studied the temperature dependence of low-frequency noise in InAs–GaAs resonant tunneling quantum dot infrared photodetectors (T-QDIPs). The noise in these devices has been investigated in the temperature range of 78–300 K. The noise spectrum showed a weak Lorentzian component superimposed upon the 1/f^γ spectrum. The change in the cut-off frequency of the Lorentzian was analyzed as a function of temperature. The activation energy of the trap associated with this Lorentzian was obtained as 0.155 eV, which is in good agreement with the energy of the lowest energy state in the quantum dot.     

Drivability improvement in Schottky barrier source/drain MOSFETs with strained-Si channel by Schottky barrier height reduction

Due to an extra barrier between source and channel, the drivability of Schottky barrier source/drain MOSFETs (SBMOSFETs) is smaller than that of conventional transistors. To reach the drivability comparable to the conventional MOSFET, the Schottky barrier height (SBH) should be lower than a critical value. It is expected that SBH can be effectively reduced by a bi-axially strain on Si. In this letter, p-channel MOSFETs with PtSi Schottky barrier source/drain, HfAlO gate dielectric, HfN/TaN metal gate and strained-Si channel are demonstrated for the first time using a simplified low temperature process. Devices with the channel length of 4 μm have the drain current of 9.5 μA/μm and the transconductance of 14 μS/μm at V_gs − V_th = V_ds = −1 V. Compared to the cubic Si counterpart, the drain current and the transconductance are improved up to 2.7 and 3.1 times respectively. The improvement is believed to arising from the reduced barrier height of the PtSi/strained-Si contact and the enhanced hole mobility in the strained-Si channel.     

Improvement in negative differential conductance characteristics of hole resonant-tunneling diodes with high Ge fraction Si/strained Si1−xGex/Si(1 0 0) heterostructure

Hole resonant-tunneling diodes (RTD) with Si/strained Si_1?xGe_x heterostructures epitaxially grown on Si(1 0 0) have been fabricated and improvement in negative differential conductance (NDC) characteristics for high Ge fraction such as x = 0.5 was investigated. It is clearly shown that SiH₄ exposure at low temperatures of 400–450 °C just after Si_1?xGe_x epitaxial growth is effective to suppress surface roughness in atomic order. In the case of the RTD with x = 0.48, NDC characteristics for 1.4-nm thick Si barriers were observed at higher temperatures around 270 K than that for 2.4-nm thick Si barriers. By increasing the Ge fraction to x = 0.58, NDC characteristics were also observed at higher temperatures around 290 K than that with x = 0.48.     

New insight on negative bias temperature instability degradation with drain bias of 28 nm High-K Metal Gate p-MOSFET devices

The degradation of negative bias temperature instability (NBTI) on 28 nm High-K Metal Gate (HKMG) p-MOSFET devices under non-uniform stress condition has been systematically studied. We found the asymmetry between forward and reverse Idsat shift under non-uniform stress condition is significant for long channel devices even under low drain bias stress (e.g., Vds = −0.1 V and gate channel length L = 1 μm), and seems to be dominated by a minimally required critical length (L = 0.2 μm derived from the experimental data). To the authors’ best knowledge, these are new phenomena reported. We attribute these anomalous NBTI characteristics with drain bias to the local self-heating (LSH) activated NBTI degradation mechanism. One semi-empirical analytical model, which fits well with our experimental data, is then proposed in this paper.     

Reduced contact resistance and highly stable operation in polymer thin-film transistor with aqueous MoOx solution contact treatment

We report on a newly developed solution process using MoO₃ for reducing source and drain (S/D) electrodes in organic thin-film transistor (TFT). By taking advantage of the difference in surface wettability between the gate dielectric layer and the S/D electrodes, the electrode treatment using the MoO_x solution was applied to polymer TFT with short channel lengths less than 10 μm. The contact resistance was noticeably reduced at the interface of the S/D electrodes in a polymer TFT using a pBTTT-C16. Furthermore, the field effect mobility for this TFT was enhanced from 0.03 to 0.1 cm²/V s. Most notably, the threshold voltage (V_th) shift under gated bias stress was less than 0.2 V after 10⁵ s, which is comparable to that of conventional poly crystalline Si TFT.     

Effective mobility in amorphous organic transistors: Influence of the width of the density of states

The temperature dependence of poly(3-hexylthiophene-2,5-diyl) (P3HT)/polystyrene (PS) blend organic transistor current/voltage (I–V) characteristics has been experimentally and theoretically studied. The planar transistors, realized by drop casting the P3HT/PS ink, exhibit high mobilities (over 5 × 10⁻³ cm² V⁻¹ s⁻¹) and good overall characteristics. A transistor model accounting for transport mechanisms in disordered organic materials was used to fit the measured characteristics. Using a single set of parameters, the measured effective mobility versus gate bias, either increasing or decreasing with the gate bias depending on temperature, is well reproduced over a wide temperature range (130–343 K). A Gaussian density of states width of 0.045 eV was determined for this P3HT/PS blend. The transistor I–V characteristics are very well described considering disordered material properties within a self-consistent transistor model.     

Determination of contact parameters of Ni/n-GaP Schottky contacts

The electrical analysis of Ni/n-GaP structure has been investigated by means of current–voltage (I–V), capacitance–voltage (C–V) and capacitance–frequency (C–f) measurements in the temperature range of 120–320 K in dark conditions. The forward bias I–V characteristics have been analyzed on the basis of standard thermionic emission (TE) theory and the characteristic parameters of the Schottky contacts (SCs) such as Schottky barrier height (SBH), ideality factor (n) and series resistance (R_s) have been determined from the I–V measurements. The experimental values of SBH and n for the device ranged from 1.01 eV and 1.27 (at 320 K) to 0.38 eV and 5.93 (at 120 K) for Ni/n-GaP diode, respectively. The interface states in the semiconductor bandgap and their relaxation time have been determined from the C–f characteristics. The interface state density N_ss has ranged from 2.08 × 10¹⁵ (eV^?1 m^?2) at 120 K to 2.7 × 10¹⁵ (eV^?1 m^?2) at 320 K. C_ss has increased with increasing temperature. The relaxation time has ranged from 4.7 × 10^?7 s at 120 K to 5.15 × 10^?7 s at 320 K.     

STI-to-gate distance effects on flicker noise characteristics in 0.13 μm CMOS

The geometry effect on the flicker noise characteristics and the variations in 0.13 μm CMOS transistors were studied. By symmetrically extending the distance between the shallow-trench-isolation (STI) to the gate, both NMOS and PMOS presented obvious improvement on the noise characteristics. As the distance increased from 0.6 μm to 10 μm, the average noise level reduced by more than one order of magnitude (NMOS) and the standard deviations σ_dB improved from 5.95 dB to 1.79 dB for NMOS and from 3.93 dB to 2.17 dB for PMOS, respectively. To further identify the noise mechanism, the devices with asymmetrical STI-to-gate distances were also investigated. It was found that the distance in the source side (SA) has a much higher impact on the observed noise characteristics. The results suggested that the noise characteristics were dominated by the STI stress induced traps for both NMOS and PMOS studied here. In addition, the carrier number fluctuation model with the correlated mobility scattering could be more suitable to describe the noise characteristics in these devices.     

A high current gain gate-controlled lateral bipolar junction transistor with 90 nm CMOS technology for future RF SoC applications

A CMOS-compatible gate-controlled lateral BJT (GC-LBJT) was prepared with a conventional 90 nm CMOS technology for radio frequency system-on-chip (RF SoC) applications. The emitter injection efficiency and the doping profile in P-well were optimized by properly controlling source, drain, and well implants. Consequently, the GC-LBJT with a gate length of 0.15 μm can achieve a current gain over 2000 and 17/19 GHz for the f_T/f_max, respectively, which are 1000%, 200%, and 60% improvements in current gain, f_T and f_max, respectively as compared to the LBJT reported previously.     

Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI

In this study, we integrate and compare the electrical performances of metal/high-K embedded gates in 3D multi-channel CMOSFETs (MCFETs) on SOI. The electrical characteristics of embedded gates obtained by filling cavities with TiN/HfO₂, TiN/SiO₂ or N⁺ poly-Si/SiO₂ are compared to a planar reference. In particular, we investigate electron and hole mobility behaviours (300 K down to 20 K) in embedded and planar structures, the gate leakage current and the negative bias temperature instability (NBTI). Despite a lower mobility, TiN/HfO₂ gate stack demonstrates the best I_ON/I_OFF compromise and exhibits NBTI life time higher than 10 years up to 1.3 V.     

Optimizing the fabrication process for high performance graphene field effect transistors

As an emerging material, graphene has attracted vast interest in solid-state physics, materials science, nanoelectronics and bioscience. Graphene has zero bandgap with its valence and conduction bands are cone-shaped and meet at the K points of the Brillouin zone. Due to its high intrinsic carrier mobility, large saturation velocity, and high on state current density, graphene is also considered as a promising candidate for high-frequency devices. To improve the reliability of graphene FETs, which include shifting the Dirac point voltage toward zero, increasing the channel mobility and decreasing the source/drain contact resistance, we optimized the device fabrication process. For CVD grown graphene, the film transfer and the device fabrication processes may produce interfacial states between graphene and the substrate and make graphene p or n-type, which shift the fermi level far away from the Dirac point. We have found that after graphene film transfer, an annealing process at 400 °C under N₂ ambient will shift Dirac point toward zero gate voltage. Ti/Au, Ni, and Ti/Pd/Au source/drain structures have been studied to minimize the contact resistance. According to the measured data, Ti/Pd/Au structure gives the lowest contact resistance (～500 ohm μm). By controlling the process of graphene growth, transfer and device fabrication, we have achieved graphene FETs with a field effective mobility of 16,000 cm²/V s after subtraction of contact resistance. The contact resistivity was estimated in the range of 1.1 × 10^?6 Ω cm² to 8.8 × 10^?6 Ω cm², which is close to state of the art III–V technology. The maximum transconductance was found to be 280 mS/mm at V_D = 0.5 V, which is the highest value among CVD graphene FETs published to date.     

A 24-dB Ku-band low-power linearized 90-nm amplifier with a built-in output buffer

In this paper, we present a 90-nm high gain (24 dB) linearized CMOS amplifier suitable for applications requiring high degree of port isolation in the K_u-band (13.2–15.4 GHz). The two-stage design is composed of a low-noise common-gate stage and a gain-boosting cascode block with an integrated output buffer for measurement. Optimization of input stage and load-port buffer parameters improves the front-end's linear coverage, port return-loss, and overall gain without burdening its power demand and noise contribution. With low gate bias voltages (0.65–1.2 V) and an active current source, <?10 dB port reflection loss and 3.25–3.41 dB NF are achieved over the bandwidth. The input reflection loss of the overall amplifier lies between ?35 and ?10 dB and the circuit demonstrates a peak forward gain of 24 dB at 14.2 GHz. The output buffer improves the amplifier's forward gain by ～9 dB and pushes down the minimum output return loss to ?22.5 dB while raising the front-end NF by only 0.05 dB. The effect of layout parasites is considered in detail in the 90-nm process models for accurate RF analysis. Monte Carlo simulation predicts 9% and 8% variation in gain and noise figures resulting from a 10% mismatch in process. The K_u-band amplifier including the buffer block consumes 7.69 mA from a 1.2-V supply. The proposed circuit techniques achieve superior small signal gain, GHz-per-milliwatt, and range of linearity when compared with simulated results of reported microwave amplifiers.     

The effect of gate overlap lightly doped drains on low temperature poly-Si thin film transistors

Low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have a high carrier mobility that enables the design of small devices that offer large currents and fast switching speeds. However, the electrical characteristics of the conventional self-aligned polycrystalline silicon (poly-Si) TFTs are known to present several undesired effects, such as large leakage currents, the kink effect, and the hot-carrier effect. For this paper, LTPS TFTs were fabricated, and the SiN_x/SiO₂ gate dielectrics and the effect of the gate-overlap lightly doped drain (GOLDD) were analyzed in order to minimize these undesired effects. GOLDD lengths of 1, 1.5 and 2 μm were used, while the thickness of the gate dielectrics (SiN_x/SiO₂) was fixed at 65 nm (40 nm/25 nm). The electrical characteristics show that the kink effect is reduced in the LTPS TFTs using a more than 1.5 μm of GOLDD length. The TFTs with the GOLDD structure have more stable characteristics than the TFTs without the GOLDD structure under bias stress. The degradation from the hot-carrier effect was also decreased by increasing the GOLDD length. After applying the hot-carrier stress test, the threshold voltage variation (ΔV_TH) was decreased from 0.2 V to 0.06 V by the increase of the GOLDD length. The results indicate that the TFTs with the GOLDD structure were protected from the degradation of the device due to the decreased drain field. From these results it can be seen that the TFTs with the GOLDD structure can be applied to achieve high stability and high performance in driving circuit applications for flat-panel displays.