CSAM: A clock skew-aware aging mitigation technique

In this work, we propose a clock skew-aware aging mitigation (CSAM) technique which considers the effect of asymmetric aging both on logic path and clock tree together. Simultaneous consideration of both parts in the design optimization problem enables us to reduce the area overhead while increasing the lifetime. For the aging mitigation of the logic path, we make use of both internal node control (INC) and input vector control (IVC) techniques while, for the clock tree circuits, a proper choice between NAND or NOR based integrated clock gating (ICG) cell is made. The optimization may be performed based on two objective functions of maximizing lifetime or minimizing the area overhead for a predetermined clock frequency and lifetime. To assess the efficacy of the proposed technique, we compared the lifetimes and area overheads for a set of circuits from ISCAS89 and ITC99 benchmark suites when CSAM and conventional techniques are used. The results, obtained using SPICE simulations for the circuits in a 45-nm technology, reveals that an average lifetime improvement of 34% and an average area overhead reduction of 25.7% for the two objective functions, respectively.     

Lifetime prediction for submicrometer LSI circuits and programmable logic: An overview

An overview is given of the experience gained in lifetime prediction for submicrometer LSI circuits and programmable logic, as reported by leading manufacturers including Siemens AG, Analog Devices, Atmel, Xilinx, Altera, QuickLogic, and Actel. The main conclusions are as follows: (i) The Arrhenius equation remains a major tool for describing the temperature dependence of circuit lifetime. (ii) The lifetime of LSI circuits continues to display a bimodal pattern. (iii) Bias-temperature stressing constitutes a generally useful technique for identifying failure mechanisms. (iv) The chi-squared distribution should be employed in predicting useful-life failure rate.Translated from Mikroelektronika, Vol. 34, No. 2, 2005, pp. 138–158.Original Russian Text Copyright © 2005 by Strogonov.     

Reliability optimization of analog integrated circuits considering the trade-off between lifetime and area

The reliability of analog integrated circuits becomes a major concern for the semiconductor industry as technology continuously scales. Among the many contributing factors, manufacturing process induced parameter variations and lifetime operational-condition-dependent transistor aging are two major hurdles limiting the reliability of analog circuits. Process variations mainly influence the parametric yield value of the fresh circuits, while transistor aging due to physical effects, such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), will cause another yield loss during circuit lifetime. In the past decades, the two issues were mainly studied separately by various communities, but analog designers nowadays need an accurate yet efficient method to analyze and optimize their circuits during the design phase, to ensure a more robust design tolerant of such joint effects.This paper proposes an efficient method for sizing of analog circuits for reliability. It is based on the analysis and optimization of the fresh worst-case distance value for each circuit performance, which can be used to characterize the robustness of circuits considering process variations and aging effects in terms of x-sigma. The fresh and aged sizing rules as well as the maximum area constraints are checked during the optimization. The trade-off between the circuit lifetime and the price we pay in terms of layout area is studied in detail. According to the result of this trade-off analysis, a longer circuit lifetime requires more total area to be spent in layout, and designers can ensure the circuit robustness with certain layout area consumption.     

A survey on fault injection methods of digital integrated circuits

One of the most popular methods for reliability assessment of digital circuits is Fault Injection (FI) in which the behavior of the circuit is simulated in presence of faults. In this paper, we present a survey of FI techniques as well as classifying these techniques considering different aspects and criteria to bring out their similarities and differences. The goal of this paper is to help the researchers and reliable circuit designers in gaining insights into the state-of-art in FI techniques and motivate them to further improve these techniques for more efficient reliability evaluation of digital circuit designs of tomorrow.     

薄栅氧化层斜坡电压TDDB寿命评价

随着超大规模集成电路的不断发展，薄栅氧化层的质量对器件和电路可靠性的作用越来越重要。经时绝缘击穿（TDDB）是评价薄栅氧化层质量的重要方法。文章着重于薄栅氧化层TD-DB可靠性评价的斜坡电压试验方法的研究，基于斜坡电压实验，提取模型参数，分别利用线性场模型和定量物理模型，外推出工作电压下栅氧化层的寿命。通过分析斜坡电压实验时氧化层的击穿过程，提出斜坡电压实验时利用统一模型外推栅氧化层的寿命比较合适。     

Workload and temperature dependent evaluation of BTI-induced lifetime degradation in digital circuits

In this work, we investigate the co-dependency of die temperature and bias temperature instability (BTI) and their combined effect on the lifetime of VLSI circuits. The investigation considers the impact of die temperature in increasing the effect of the BTI as well as changes in the die temperature due to the BTI-induced threshold voltage alterations. In addition, the impact of workloads on the degree of the BTI-induced degradation in VLSI circuits is studied. This impact accounts for the direct influence of the signal probability of the internal nodes under the given workload as well as its indirect influence due to power consumption and temperature changes of the circuits. The study is performed by using a simulation framework that captures dynamic changes in the operating temperature and application workload. Simultaneous consideration of the dynamic workload and operating temperature enables one to accurately predict the circuit lifetime. To assess the accuracy of the proposed approach, the estimated delay degradations caused by the Negative BTI (NBTI) for some large circuits from ISCAS'89 and ITC'99 benchmark suites when circuits are simulated under dynamic (both temperature and workload are updated periodically), semi-static (either temperature or workload is updated periodically), and static (no updating is performed) scenarios are compared. Simulation results obtained in a 45 nm CMOS technology, reveal that the predicted timing degradation in the case of the dynamic scenario is significantly different than those of the other scenarios. The differences ranged from − 135% to + 98% for the considered circuits in this work. The large differences demonstrate that for accurate estimation of the circuit lifetime under the BTI effect, the dynamic scenario should be adopted as part of the standard design flows.     

Recombination level selection criteria for lifetime reduction in integrated circuits

In the past, lifetime control in integrated circuits has been done on an empirical basis. This paper introduces selection criteria for recombination centers which are to be used for reducing minority carrier lifetime in integrated circuits. It is shown that the recombination level should have a large lifetime ratio (τ_SC/τ_LL) in order to obtain minority carrier lifetime reduction with minimal increase in the leakage current, and should possess large capture cross section values in order to minimize compensation effects. Using these criteria, preferred locations for the recombination center have been defined for both p and n type silicon, and the trade-off between reduction of lifetime and increase in leakage current has been shown to degrade with increase in resistivity and ambient temperature. These criteria have also allowed a quantitative comparison between various lifetime control techniques for the first time, and platinum doping has been identified as the most favorable lifetime control process at the present time.     

Thermal cycling lifetime of flip chip on board circuits with solder bumps and isotropically conductive adhesive joints

Flip chip on board (FCOB) circuits with solder bumps or isotropically conductive adhesives (ICA) may be subject to joint failure during thermal cycling. Although use of epoxy underfill can increase the lifetime significantly, there is still a risk of failure if the material properties of the underfill material are not adequate to prevent excessive values of stress and strain in the joints. This paper presents experimental measurements of the number of thermal cycles to failure for both solder reflow and ICA joint FCOB circuits. Measurements have been carried out for several different material systems with various types of underfill. The measurements of solder bump lifetime are compared to a lifetime model based on analytical calculations of solder strain. For an underfill type without filler (CTE=58 ppm//spl deg/C), the measurements are in excellent agreement with the model predictions, both giving an average lifetime of around 1500 thermal cycles between -55 and 125/spl deg/C. For two filled types of underfill with CTE nearly matched to that of solder, the measured average lifetimes vary from around 2700 to 5500 cycles. The corresponding model predictions are around 6000 and 7000 cycles, respectively. Measurements of the lifetime of FCOB's with ICA connections have been carried out for two different material systems. The obtained lifetimes vary between approximately 500 and 4000 cycles. No systematic lifetime variation with the thermal expansion of the underfill has been observed, but the lifetime seems to be dependent on the properties of the bump on the chip pad. Delamination, for instance at the ICA/bump interface, is found to be an important cause of failure.     

Dynamic NBTI lifetime model for inverter-like waveform

In this paper, a simple yet accurate NBTI lifetime model has been formulated for a pMOSFET working in dynamic AC condition. The model is based on detailed dynamic NBTI (DNBTI) characterization for inverter-like waveform stress. The fitting parameters of the model can be readily obtained from the calibration of one-time DNBTI lifetime measurement for a small set of frequency/duty cycle matrix. After that, it can be employed to estimate the NBTI lifetime for a pMOSFET under any AC operating condition with reasonably good agreement. Additionally, it is shown that the lifetime enhancement by a shorter duty cycle is even more significant than that by a higher frequency. The application of the model to the lifetime estimation of circuits with multiple operation modes is also discussed.     

硅基异构三维集成技术研究进展

为满足电子系统小型化高密度集成、多功能高性能集成、小体积低成本集成的需求,硅基异构集成和三维集成成为下一代集成电路的使能技术,成为当前和今后的研究热点.硅基三维集成微系统可集成化合物半导体、CMOS、MEMS等芯片,充分发挥材料、器件和结构的优势,使传统的高性能射频组件电路进入到射频前端芯片化,可集成不同节点的CPU、...     

Gerentology of Silicon Integrated Circuits

The lifetime of silicon ICs in relation to material and component aging is discussed. The service time of the circuits was predicted from accelerated tests. The lifetime of circuits of series 106, 134, 1804, 582, and 136 was evaluated from parameter failures with the Box–Jenkins model.     

Distortion In p-i-n Diode Control Circuits

Traditionally, distortion in p-i-n diodes has been thought to be only a function of the carrier lifetime and frequency of operation. This understanding is based on empirical evidence and is not entirely accurate. This paper will discuss the origins of p-i-n diode distortion and study the effects of various devices parameters on distortion performance. Included in the investigation on single-diode circuits will be switching circuits and reflective attenuators. In switch circuits, the analysis shows that distortion can be minimized by maximizing the stored-to-charge resistance ratio in the diode. In attenuators, the analysis shows that maximizing the i-region thickness will minimize distortion, independent of the device carrier life-time. In attenuators where multiple p-i-n diodes are used (the bridged-tee and PI are discussed), maximizing the i-region thickness also minimizes the distortion, independent of carrier lifetime. The model accurately predicts distortion signal cancellation in both single and multiple p-i-n diode circuits.     

Amorphous Silicon Display Backplanes on Plastic Substrates

Amorphous silicon (a-Si) thin-film transistor (TFT) backplanes are very promising for active-matrix organic light-emitting diode displays (AMOLEDs) on plastic. The technology benefits from a large manufacturing base, simple fabrication process, and low production cost. The concern lies in the instability of the TFTs threshold voltage (V_T) and its low device mobility. Although V_T-instability can be compensated by means of advanced multi-transistor pixel circuits, the lifetime of the display is still dependent on the TFT process quality and bias conditions. A-Si TFTs with field-effect mobility of 1.1 cm²/Vmiddots and pixel driver circuits have been fabricated on plastic substrates at 150 degC. The circuits are characterized in terms of current drive capability and long-term stability of operation. The results demonstrate sufficient and stable current delivery and the ability of the backplane on plastic to meet AMOLED requirements     

Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Sources of failures and yield improvement for VLSI

Redundancy of both logic circuits and interconnections is the core principle of both RVLSI (Restructurable or Fault-Tolerant VLSI) and WSI (Wafer Scale Integration). For varying complexity and sizes of circuits different factors of redundancy are required. Effective use of redundancy requires understanding of the failures and failure modes at different stages of the processing and lifetime of VLSI and WSI circuits. This paper consists of two parts. In Part I, sources of failures for MOS devices are discussed. Manifestations of physical failures are described. Use of redundancy for the yield improvement of VLSI circuits is explored through the use of a mathematical model. It is shown that interconnection density and pattern complexities around each section determines the effectiveness of yield improvement. In Part II (to be published in a forthcoming issue), programmable interconnect technologies are described to facilitate restructuring of VLSI and WSI circuits, in this case as they apply to yield improvement through the use of redundancy.     

Improved understanding of metal ion reservoirs within barrier-metal systems

Within integrated circuits there are many instances where low current density lines feed directly (without a via) into a single line of much higher current density, for example with clock or power supply distribution. This work demonstrates and discusses increased lifetime with increasing numbers of current feed lines in a barrier metal interconnect system. The low current density feed lines (branches) act as reservoirs or sources of additional Al and Cu ions, which can re-fill portions of voids and/or slow void growth in the high current density line (trunk). It is discussed that any area of metal at a lower current density might be considered a reservoir or source of metal ions for higher current density regions, and can effectively extend the lifetime of the higher current density region. Narrow lines may get more benefit than wide lines. Increasing reservoir size will increase lifetime, within limits.     

Time-Efficient Identification Method for Aging Critical Gates Considering Topological Connection

The shrinking silicon feature size causes the continuous increment of the aging effect due to the negative bias temperature instability (NBTI), which becomes a potential stopper for IC development. As the basis of circuit-level aging protection, an efficient aging critical-gate identification method is crucially required to select a set of gates for protection to guarantee the normal lifetime of the circuits. The existing critical-gate identification methods always depend on a critical path set which contains so many paths that its generation procedure requires undesirable CPU runtime; furthermore, these methods can achieve a better solution with taking account of the topological connection. This paper proposes a time-efficient critical gates identification method with topological connection analysis, which chooses a small set of critical gates. Experiments over many circuits of ITC99 and ISCAS benchmark demonstrate that, to guarantee the normal lifetime (e.g., 10 years) of each circuit, our method achieves a 3.97x speedup and saves as much as 27.21% area overhead compared with the existing methods.     

Pass Transistor-Based Pull-Up/Pull-Down Insertion Technique for Leakage Power Optimization in CMOS VLSI Circuits

Reduction in leakage power consumption is one of the important issues in the field of VLSI. Numerous techniques have been proposed by several researchers, based on threshold voltage variations and gate modifications. In this paper, a novel pass transistor-based pull-up/pull-down insertion technique is proposed to minimize standby leakage. Experimental results on various ISCAS’89 benchmark circuits show that proposed technique has an improvement up to 20, 36 and 33 % on average in leakage reduction, delay improvement and area savings respectively, compared to the transmission gate-based technique. All benchmark circuits are simulated using H-spice Tool with an 180-nm standard cell library based on BSIM3 transistor model. Finally, the efficacy of the proposed approach in improving various metrics has been compared with present state-of-art methods.     

NBTI-Aware Design of Integrated Circuits: A Hardware-Based Approach for Increasing Circuits’ Life Time

Advances in CMOS technology have made possible the increase of integrated circuit’s density, which impacts directly on the circuit’s performance. However, technology scaling poses some reliability concerns that directly affect the circuit’s lifetime. One of the most important issues in nanoscale circuits is related to the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). This phenomenon increases the threshold voltage of pMOS transistors, which introduces delay along the integrated circuits’ paths, eventually causing functional failures. In this paper, a hardware-based technique able to increase the lifetime of Integrated Circuits (ICs) is proposed. In more detail, the technique is based on an on-chip sensor able to monitor IC’s aging and to adjust its power supply voltage in order to minimize NBTI effects and increase the circuit’s lifetime. Experimental results obtained throughout simulations demonstrate the technique’s efficiency, since the circuit’s lifetime has been increased by 150 %. Finally, the analysis of the main overheads introduced as well as the impact related to process variation renders the evaluation of the proposed approach possible.     

Contemporary CMOS aging mitigation techniques: Survey,taxonomy, and methods

The proposed paper addresses the overarching reliability issue of transistor aging in nanometer-scaled circuits. Specifically, a comprehensive survey and taxonomy of techniques used to model, monitor and mitigate Bias Temperature Instability (BTI) effects in logic circuits are presented. The challenges and overheads of these techniques are covered through the course of this paper. Important metrics of area overhead, power and energy overhead, performance overhead, and lifetime extension are discussed. Furthermore, the techniques are assessed with regards to ease of implementation and the ability to cope with challenges such as increase in manufacturing induced process variations. Finally, a taxonomy of the surveyed techniques is presented to facilitate generalization of the discussed approaches and to foster new inspiring techniques for this important reliability phenomenon leading to advancements in the design of defect-tolerant digital circuits.     

动态应力下MOS器件热载流子效应研究

研究了 MOS器件中的热载流子效应 ,在分析了静态应力下 MOSFET寿命模型的基础上 ,提出了动态应力条件下 MOSFET的寿命模型。此外 ,还研究了沟道热载流子的产生和注入与器件偏置条件的关系 ,讨论了热载流子效应对电路性能的影响。通过对这些失效因素的研究和通过一定的再设计手段 ,可以减少热载流子效应导致的器件退化