HCS degradation of 5 nm oxide high-voltage PLDMOS

Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5 nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (V_GS) and high drain voltage (V_DS), reduction of the ON-resistance (R_ON) is observed. At stress times at which R_ON almost reaches its constant level, an increase of the drain leakage in OFF state (V_DS = −60 V, V_GS = 0 V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25 nm gate oxide thickness, the threshold voltage of 5 nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS.     

Charge trapping related channel modulation instability in P-GaN gate HEMTs

In this paper, a study of the channel modulation instability of commercial p-GaN gate HEMTs is presented. During the gate-voltage stress test, substantial R_DS(ON) variations up to 78 mΩ (93.8%) were observed. It is found that the p-GaN/AlGaN/GaN gate structure enables the injection of holes and electrons, which can be captured by the donor/acceptor-like traps located in the AlGaN layer. Therefore, the trapped holes and electrons concurrently modulate the channel conductivity, resulting in R_DS(ON) variations. Device simulation was performed to help explain the mechanism from the perspective of energy band. In addition, results reveal that with the recommended working gate-voltage stress V_GS = 7 V, the on-state resistance, the threshold voltage and the off-state drain to source leakage current vary up to 8 mΩ (16.3%), 0.2 V (14.8%) and 12.8 μA (42.66%) within 1 h, respectively, which could raise reliability issues for the power electronics applications of p-GaN gate HEMTs.     

A methodology for projecting SiO2 thick gate oxide reliability on trench power MOSFETs and its application on MOSFETs VGS rating

In this work, a methodology based on the E-model for the reliability projection of a thick (> 20 nm) SiO₂ gate oxide on a vertical trench power MOSFET, is presented. Experimental results suggest that a Logic Level (LL) trench MOSFET with 35 nm of gate oxide can be rated at V_GS = + 12 V if one assumes continuous DC Gate-Source bias of V_GS = + 12 V at T = 175 °C for 10 years at a defect level of 1 Part Per Million (PPM). We will demonstrate that if we take into account MOSFET device lifetime as dictated by the Automotive Electronics Council (AEC Q101) mission profile, then devices can be rated higher to V_GS = + 14.7 V at T = 175 °C for the same PPM level (1 PPM). The application of the methodology for establishing the oxide thickness, t_ox, for any required voltage rating, is discussed.     

Temperature dependence of the electrical characteristics up to 370 K of amorphous In-Ga-ZnO thin film transistors

The temperature dependence in the typical temperature operating range from 300 K up to 370 K of the electrical characteristics of IGZO TFTs fabricated at temperatures not exceeding 200 °C is presented and modeled.It is seen that up to T = 330 K, the transfer curves show a parallel shift toward more negative voltages. In both subthreshold and above threshold regimes, the drain current shows Arrhenius-type dependence. In the latter case, for low temperatures, the activation energy is around 0.35 eV for V_GS = 10 V, reducing as V_GS is increased. The observed behavior is consistent with having the VRH transport mechanism as the predominant one in conduction.     

A high-yield vacuum-evaporation-based R2R-compatible fabrication route for organic electronic circuits

Advances are described in a vacuum-evaporation-based approach for the roll-to-roll (R2R) production of organic thin film transistors (TFTs) and circuits. Results from 90-transistor arrays formed directly onto a plasma-polymerised diacrylate gate dielectric are compared with those formed on polystyrene-buffered diacrylate. The latter approach resulted in stable, reproducible transistors with yields in excess of 90%. The resulting TFTs had low turn-on voltage, on–off ratios ∼10⁶ and mobility ∼1 cm²/V s in the linear regime, as expected for dinaphtho[2,3-b:2′,3′-f] thieno[3,2-b]thiophene the air stable small molecule used as the active semiconductor. We show that when device design is constrained by the generally poor registration ability of R2R processes, parasitic source–drain currents can lead to a >50% increase in the mobility extracted from the resulting TFTs, the increases being especially marked in low channel width devices. Batches of 27 saturated-load inverters were fabricated with 100% yield and their behaviour successfully reproduced using TFT parameters extracted with Silvaco’s UOTFT Model. 5- and 7-stage ring oscillator (RO) outputs ranged from ∼120 Hz to >2 kHz with rail voltages, V_DD, increasing from −15 V to −90 V. From simulations an order of magnitude increase in frequency could be expected by reducing parasitic gate capacitances. During 8 h of continuous operation at V_DD = −60 V, the frequency of a 7-stage RO remained almost constant at ∼1.4 kHz albeit that the output signal amplitude decreased from ∼22 V to ∼10 V. Over the next 30 days of intermittent operation further degradation in performance occurred although an unused RO showed no deterioration over the same period.     

High performance inkjet-printed C60 fullerene thin-film transistors: Toward a low-cost and reproducible solution process

We have demonstrated high performance inkjet-printed n-channel thin-film transistors (TFTs) using C₆₀ fullerene as a channel material. Highly uniform amorphous C₆₀ thin-film patterns were fabricated on a solution-wettable polymer gate dielectric layer by inkjet-printing and vacuum drying process. Fabricated C₆₀ TFTs shows great reproducibility and high performance; field-effect mobilities of 2.2–2.4 cm² V^?1 s^?1, threshold voltages of 0.4–0.6 V, subthreshold slopes of 0.11–0.16 V dec^?1 and current on/off ratio of 10⁷–10⁸ in a driving voltage of 5 V. This is due to the efficient annealing process that extracting the solvent residue and the formation of low trap-density gate dielectric surface.     

Device characteristics of AlGaN/GaN MIS–HEMTs with high-k HfxZr1−xO2 (x = 0.66, 0.47, 0.15) insulator layer

This study investigates the characteristics of AlGaN/GaN MIS–HEMTs with Hf_xZr_1−xO₂ (x = 0.66, 0.47, and 0.15) high-k films as gate dielectrics. Sputtered Hf_xZr_1−xO₂ with a dielectric constant of 20–30 and a bandgap of 5.2–5.71 eV was produced. By increasing the Zr content of HfZrO₂, the V_TH shifted from −1.8 V to −1.1 V. The highest Hf content at this study reduced the gate leakage by approximately one order of magnitude below that of those Zr-dominated HFETs. The maximum I_DS currents were 474 mA/mm, 542 mA/mm, and 330 mA/mm for Hf content of 66%, 47%, 15% at V_GS = 3 V, respectively.     

Performance of commercial foundry-level AlGaN/GaN HEMTs after hot electron stressing

The performance degradation of commercial foundry level GaN HEMTs placed under a constant-power drain voltage step-stress test has been studied. By utilizing electroluminescence measurement techniques to optimize hot electron stress testing conditions (Meneghini, 2012), no significant permanent changes in saturation current (I_dss), transconductance (Gm), and threshold voltage (V_th) can be seen after stress testing of drain voltages from 30 V up to 200 V. We observe little permanent degradation due to hot electron effects in GaN HEMTs at these extreme operating conditions and it is inferred that other considerations, such as key dimensions in channel or peak electric field (Chynoweth, 1958; Zhang and Singh, 2001) [2,3], are more relevant to physics of failure than drain bias alone.     

Complementary-like inverters based on an ambipolar solution-processed molecular bis(naphthalene diimide)-dithienopyrrole derivative

We report on high-mobility top-gate organic field-effect transistors (OFETs) and complementary-like inverters fabricated with a solution-processed molecular bis(naphthalene diimide)-dithienopyrrole derivative as the channel semiconductor and a CYTOP/Al₂O₃ bilayer as the gate dielectric. The OFETs showed ambipolar behavior with average electron and hole mobility values of 1.2 and 0.01 cm² V^?1 s^?1, respectively. Complementary-like inverters fabricated with two ambipolar OFETs showed hysteresis-free voltage transfer characteristics with negligible variations of switching threshold voltages and yielded very high DC gain values of more than 90 V/V (up to 122 V/V) at a supply voltage of 25 V.     

Scaling down of organic complementary logic gates for compact logic on foil

In this work, we realize complementary circuits with organic p-type and n-type transistor integrated on polyethylene naphthalate (PEN) foil. We employ evaporated p-type and n-type organic semiconductors spaced side by side in bottom-contact bottom-gate coplanar structures with channel lengths of 5 μm. The area density is 0.08 mm² per complementary logic gate. Both p-type and n-type transistors show mobilities >0.1 cm²/V s with V_on close to zero volt. Small circuits like inverters and 19-stage ring oscillators (RO) are fabricated to study the static and the dynamic performance of the logic inverter gate. The circuits operate at V_dd as low as 2.5 V and the inverter stage delay at V_dd = 10 V is as low as 2 μs. Finally, an 8 bit organic complementary transponder chip with data rate up to 2.7 k bits/s is fabricated on foil by successfully integrating 358 transistors.     

Novel organic inverters with dual-gate pentacene thin-film transistor

We report on the fabrication and characterization of dual-gate pentacene organic thin-film transistors (OTFTs) with plasma-enhanced atomic-layer-deposited (PEALD) 150 nm thick Al₂O₃ as a bottom-gate dielectric and PEALD 200 nm thick Al₂O₃ as a top-gate dielectric. The V_th of dual-gate OTFT has changed systematically with the application of voltage bias to top-gate electrode. When voltage bias from −10 V to 10 V is applied to top gate, V_th changes from 1.95 V to −9.8 V. Two novel types of the zero drive load logic inverter with dual-gate structure have been proposed and fabricated using PEALD Al₂O₃ gate dielectrics. Because the variation of V_th due to chemical degradation and the spatial variation of V_th are inherent in OTFTs, the compensation technology by dual-gate structure can be essential to OTFT applications.     

Photo-patternable polyimide gate insulator with fluorine groups for improving performance of 2,7-didecyl[1]benzothieno[3,2-b][1]benzothiopene (C10-BTBT) thin-film transistors

Surface properties of gate insulators strongly affect the device performance of organic thin-film transistors (OTFTs). To improve the performance of OTFTs, we have developed photo-sensitive polyimide gate insulator with fluorine groups. The polyimide gate insulator film could be easily patterned by selective UV exposure without any photoinitiator. The polyimide gate insulator film, fabricated at 130 °C, has a dielectric constant of 2.8 at 10 kHz, and leakage current density of <1.6 × 10^?10 A/cm² while biased from 0 to 90 V. To investigate the potential of the polyimide with fluorine groups as a gate insulator, we fabricated C₁₀-BTBT TFTs. The field-effect mobility and the on/off current ratio of the TFTs were measured to be 0.76 ± 0.09 cm²/V s and >10⁶, respectively.     

Ultra-thin polymer gate dielectrics for top-gate polymer field-effect transistors

We have demonstrated top-gate polymer field-effect transistors (FETs) with ultra-thin (30–50 nm), room-temperature crosslinkable polymer gate dielectrics based on blending an insulating base polymer such as poly(methyl methacrylate) with an organosilane crosslinking agent, 1,6-bis(trichlorosilyl)hexane. The top-gate polymer transistors with thin gate dielectrics were operated at gate voltages less than ?8 V with a relatively high dielectric breakdown strength (>3 MV/cm) and a low leakage current (10–100 nA/mm² at 2 MV/cm). The yield of thin gate dielectrics in top-gate polymer FETs is correlated with the roughness of underlying semiconducting polymer film. High mobilities of 0.1–0.2 cm²/V s and on and off state current ratios of 10⁴ were achieved with the high performance semiconducting polymer, poly(2,5-bis(3-alkylthiophen-2yl)thieno[3,2-b]thiophene.     

New degradation mechanism observed for AlGaN/GaN HEMTs with sub 100 nm scale unpassivated regions around the gate periphery

AlGaN/GaN HEMTs with low gate leakage current in the μA/mm range have been fabricated with a small-unpassivated region close to the gate foot. They showed considerably higher critical voltage values (average VCR = 60 V) if subjected to step stress testing at OFF-state conditions and room temperature as compared to standard devices with conventional gate technology. This is due to the fact that electrons injected from the gate can be accumulated at the unpassivated region and thus builds up negative charge. The lower gate leakage is due to virtual gate formation, which is reducing local electric field in the vicinity of the gate. In contrast to devices with standard gate technology, degradation during step stressing is not associated with a simultaneous gate leakage and drain leakage current increase but with a strong increase of drain current at OFF-state conditions while the gate leakage is practically not affected. Then a relatively higher critical voltage of around 60 V is achieved. An abrupt increase of subthreshold drain current implies the formation of a conductive channel bypassing the gate region without influencing gate leakage. It is believed that hopping conductivity via point defects formed during device stressing creates this channel. Once this degradation mode takes place, the drain current of affected devices significantly drops. This can be explained by negative trap formation in the channel region affecting the total charge balance in 2DEG region. Electroluminescence measurements on both fresh and degraded devices showed no hot spots at OFF-state conditions. However, there is additional emission at ON-state bias, which suggests additional energetic states that lead to radiative electron transition effects in the degraded devices, most possibly defect states in the buffer.     

Controllable threshold voltage of a pentacene field-effect transistor based on a double-dielectric structure

The authors report controllable threshold voltage (V_th) in a pentacene field-effect transistor based on a double-dielectric structure of poly(perfluoroalkenyl vinyl ether) (CYTOP) and SiO₂. When a positive switching voltage is applied to the gate electrode of the transistor, electrons traverse through the pentacene and CYTOP layers and subsequently trapped at the CYTOP/SiO₂ interface. The trapped electrons induce accumulation of additional holes in the pentacene conducting channel, resulting in a large V_th shift from ?4.4 to +4.6 V. By applying a negative switching voltage, the trapped electrons are removed from the CYTOP/SiO₂ interface, resulting in V_th returning to an initial value. The V_th shift caused by this floating gate-like effect is reversible and very time-stable allowing the transistor to be applicable to a nonvolatile memory that has excellent retention stability of stored data.     

High-performance pentacene field-effect transistors using Al2O3 gate dielectrics prepared by atomic layer deposition (ALD)

High-performance pentacene field-effect transistors have been fabricated using Al₂O₃ as a gate dielectric material grown by atomic layer deposition (ALD). Hole mobility values of 1.5 ± 0.2 cm²/V s and 0.9 ± 0.1 cm²/V s were obtained when using heavily n-doped silicon (n⁺-Si) and ITO-coated glass as gate electrodes, respectively. These transistors were operated in enhancement mode with a zero turn-on voltage and exhibited a low threshold voltage (< −10 V) as well as a low sub-threshold slope (<1 V/decade) and an on/off current ratio larger than 10⁶. Atomic force microscopy (AFM) images of pentacene films on Al₂O₃ treated with octadecyltrichlorosilane (OTS) revealed well-ordered island formation, and X-ray diffraction patterns showed characteristics of a “thin film” phase. Low surface trap density and high capacitance density of Al₂O₃ gate insulators also contributed to the high performance of pentacene field-effect transistors.     

Self-aligned inversion n-channel In0.2Ga0.8As/GaAs metal–oxide–semiconductor field-effect-transistors with TiN gate and Ga2O3(Gd2O3) dielectric

A self-aligned process for fabricating inversion n-channel metal–oxide–semiconductor field-effect-transistors (MOSFET’s) of strained In_0.2Ga_0.8As on GaAs using TiN as gate metal and Ga₂O₃(Gd₂O₃) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at V_g = 4 V and V_d = 2 V, a low gate leakage of <10^?7 A/cm² at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at V_g = 3 V, V_d = 2 V, and an on/off ratio of ～10⁵ in drain current. For comparison, a TiN/Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10^?8–10^?9 A/cm², well-behaved capacitance–voltage (C–V) characteristics giving a high dielectric constant of ～16 and a low interfacial density of state of ～(2～6) × 10¹¹ cm^?2 eV^?1, and an atomically sharp smooth Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As interface.     

Influence of processing and annealing steps on electrical properties of InAlN/GaN high electron mobility transistor with Al2O3 gate insulation and passivation

We report on preparation and electrical characterization of InAlN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors (MOS HEMTs) with Al₂O₃ gate insulation and surface passivation. About 12 nm thin high-κ dielectric film was deposited by MOCVD. Before and after the dielectric deposition, the samples were treated by different processing steps. We monitored and analyzed the steps by sequential device testing. It was found that both intentional (ex situ) and unintentional (in situ before Al₂O₃ growth) InAlN surface oxidation increases the channel sheet resistance and causes a current collapse. Post deposition annealing decreases the sheet resistance of the MOS HEMT devices and effectively suppresses the current collapse. Transistors dimensions were source-to-drain distance 8 μm and gate width 2 μm. A maximum transconductance of 110 mS/mm, a drain current of ～0.6 A/mm (V_GS = 1 V) and a gate leakage current reduction from 4 to 6 orders of magnitude compared to Schottky barrier (SB) HEMTs was achieved for MOS HEMT with 1 h annealing at 700 °C in forming gas ambient. Moreover, InAlN/GaN MOS HEMTs with deposited Al₂O₃ dielectric film were found highly thermally stable by resisting 5 h 700 °C annealing.     

Low-voltage,high speed inkjet-printed flexible complementary polymer electronic circuits

We report the development of high-performance inkjet-printed organic field-effect transistors (OFETs) and complementary circuits using high-k polymer dielectric blends comprising poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) and poly(methyl methacrylate) (PMMA) for high-speed and low-voltage operation. Inkjet-printed p-type polymer semiconductors containing alkyl-substituted thienylenevinylene (TV) and dodecylthiophene (PC12TV12T) and n-type P(NDI2OD-T2) OFETs showed high field-effect mobilities of 0.1–0.4 cm² V^?1 s^?1 and low threshold voltages down to 5 V. These OFET properties were modified by changing the blend ratio of P(VDF-TrFE) and PMMA. The optimum blend – a 7:3 wt% mixture of P(VDF-TrFE) and PMMA – was successfully used to realize high-performance complementary inverters and ring oscillators (ROs). The complementary ROs operated at a supplied bias (V_DD) of 5 V and showed an oscillation frequency (f_osc) as high as ～80 kHz at V_DD = 30 V. Furthermore, the f_osc of the complementary ROs was significantly affected by a variety of fundamental parameters such as the electron and hole mobilities, channel width and length, capacitance of the gate dielectrics, V_DD, and the overlap capacitance in the circuit configuration.