Boundary element analysis of thermal fatigue effects on high power IGBT modules

The technology of high power IGBT modules has been significantly improved these last years against thermal fatigue. The most frequently observed failure modes, due to thermal fatigue, are the solder cracks between the copper base plate and the direct copper bonding (DCB) substrate and bond wire lift-off. Specific simulation tools are needed to carry out reliability researches and to develop device lifetime models. In other respects, accurate temperature and flux distributions are essential when computing thermo-mechanical stresses in order to assess the lifetime of high power modules in real operating conditions. This study presents an analysis method based on the boundary element method (BEM) to investigate thermal behavior of high power semiconductor packages subjected to power cycling loads. The paper describes the boundary integral equation which has been solved using the BEM and applied to the case of a high power IGBT module package (3.3 kV–1.2 kA). A validation of the numerical tool is presented by comparison with experimental measurements. Finally, the paper points out the effect on the thermal stress of the IGBT chips position on the DCB substrate. In particular, a light shifting of the silicon chips may be sufficient to delay significantly the initiation and the propagation of the cracks, allowing a higher device lifetime of the studied module.     

An improved reliability model for Si and GaN power FET

The existing standard reliability models for power devices are not satisfactory and they fall short of predicting failure rates or wear-out lifetime of semiconductor products. This is mainly attributed to two reasons; the lack of a unified approach for predicting device failure rates and the fact that all commercial reliability evaluation methods relay on the acceleration of one dominant failure mechanism. Recently, device reliability research programs are aimed to develop new theoretical models and experimental methods that would result a better assessment of the device lifetime as well as point out on the dominating failure mechanism for particular operating conditions. A new model, named Multi failure mechanism, Overstress Life test (MOL) has been introduced and posed a better understanding of the dominating failure mechanisms under various stressed conditions in advanced FPGA devices (for 45 and 28 nm technologies). In this work we present, for the first time, the implementation of the MOL model to investigate the reliability of silicon power MOSFET and GaN power FET devices. Both, LTSpice simulation and experimental data are presented for a test circuit of a ring oscillator, based on CMOS-FET, NMOS-FET, PMOS-FET and N-channel e-GaN FET. The monitored data was acquired in-situ in form of the ring frequency or Vds values that enabled to assess the lifetime and determine the dominating mechanism during accelerated wearout by temperature, applied bias voltage, thermal cycling, gamma and electron irradiation. Moreover, in the case of GaN devices, RDS-On monitoring circuit has also been operated during thermal cycling of the tested component and the acceleration factor was derived for various operational parameters.     

Advanced power cycler with intelligent monitoring strategy of IGBT module under test

Power cycling (PC) test is one of the important test methods to assess the reliability performance of power device modules related to packaging technology, in respect to temperature stress. In this paper, an advanced power cycler with a real-time V_{CE_ON} and V_F measurement circuit for the IGBT and diode, which for the wear-out condition monitoring are presented. This advanced power cycler allows to perform power cycling test cost-effectively under conditions close to real power converter applications. In addition, an intelligent monitoring strategy for the separation of package-related wear-out failure mechanisms has been proposed. By means of the proposed method, the wear-out failure mechanisms of an IGBT module can be separated without any additional efforts during the power cycling tests. The validity and effectiveness of the proposed monitoring strategy are also verified by experiments.     

非硅MEMS惯性开关可靠性研究

非硅MEMS惯性开关具有体积小、成本低、可批量生产以及强度和导电性能较好的优点,但其可靠性问题制约了其应用领域。通过开展非硅MEMS惯性开关的可靠性实验(包括温度循环实验和随机振动实验),找出其主要失效模式为分层。通过对失效部位进行分析,并利用有限元方法分析器件上的应力分布,研究了相应的失效机理。研究结果表明:引发惯性开关分层失效的主要原因是层间产生疲劳效应,温度循环应力会使惯性开关各层间由于热膨胀系数失配而产生疲劳,而振动应力则直接加载在惯性开关上而使其产生疲劳;惯性开关中铬层与铜层之间最易发生失效,而分析表明该层间界面处热应力最大;经历温度循环实验和振动实验的惯性开关相较只经历一种实验的样本更容易失效,进一步说明了温度循环应力会使开关层间发生疲劳,而振动应力则会引起应力集中而加速分层失效。     

On the crack and delamination risk optimization of a Si-interposer for LED packaging

3D-integration becomes more and more an important issue for advanced LED packaging solutions as it is a great challenge for the thermo-mechanical reliability to remove heat from LEDs to the environment by heat spreading or specialized cooling technologies. Thermal copper-TSVs provide an elegant solution to effectively transfer heat from LED to the heat spreading structures on the backside of a substrate. But, the use of copper-TSVs generates also novel challenges for reliability as well as also for reliability analysis and prediction, i.e. to manage multiple failure modes acting combined – interface delamination, cracking and fatigue, in particular. In this case, the thermal expansion mismatch between copper and silicon yields to risky stress situations.To overcome cracking and delamination risks in the vicinity of thermal copper-TSVs the authors performed extensive simulative work by means of fracture mechanics approaches – an interaction integral approach within a simulative DoE and the X-FEM methodology to help clarifying crack propagation paths in silicon. The results provided a good insight into the role of model parameters for further optimizations of the intended thermal TSV-approaches in LED packaging applications.     

Reliability aspects of high temperature power MOSFETs

Gate oxide reliability and thermal shock resistance of power MOSFETs for high temperature applications, have been investigated by accelerated tests and several analytical and electrical techniques. Thermal shock tests have been performed between -40°C and 200°C with subsequent electrical tests and failure analysis. Time Dependent Dielectric Breakdown (TDDB) of the gate oxide has been studied in detail by means of in-situ leakage current measurements at various voltages and temperatures.A statistical analysis of the results yields information on the underlying failure time distribution, failure mechanisms and lifetime.     

Reliability of large periphery GaN-on-Si HFETs

GaN devices exhibit excellent potential for use in many RF applications. However, commercial acceptance of the technology has been hindered by the scarcity and non-statistical nature of reliability results. In this work we present a full device level reliability study of GaN-on-Si HFETs. Reliability results on this technology include three-temperature DC data that show an activation energy of 1.7 eV and an average failure time >10⁷ h at 150 °C. Additionally, long duration DC lifetest (30 000 device hours) and RF lifetest (4000 device hours) results demonstrate a repeatable low drift process. Environmental tests such as autoclave and ESD demonstrate the ruggedness of the material system and technology. Finally, initial failure analysis is discussed.     

Study of thermal cycling and temperature aging on PbSnAg die attach solder joints for high power modules

High power modules are still facing the challenges to increase their power output, increase the junction temperature, and increase their reliability in harsh conditions. Therefore this study is doing a detail analysis of the soldering joint between a direct copper bonded substrate and a high power IGBT made with the high lead solder alloy Pb_92.5Sn_5.0Ag_2.5. The intermetallic phases and the microstructure of standard chip to substrate solder joint will be analysed and compared to deteriorated joints coming from modules which have undergone an active thermal cycling. As expected, the as soldered joint was clearly different than solder joints made for ball grid array or small components on PCBs. The as soldered joint shows no sign of Cu₆Sn₅ intermetallic layer, but instead shows the presence of Ag₃Sn particles at the solder–chip interface. Furthermore, the failure mechanisms under active thermal cycling also seem to be different. There is no growth of intermetallic phases and no strong delamination of the device. Instead a large network of intermetallic particles (Ag₃Sn) is produced during aging and seems to degrade the solder thermal properties.     

Ensuring the reliability of power electronic devices with regard to terrestrial cosmic radiation

Terrestrial cosmic radiation is a significant factor for the reliability of power electronic devices, for voltage classes that range from about 300 V to beyond 6500 V. As such, cosmic radiation-induced device failure concerns power diodes, MOSFETs and IGBT, irrespective of the base semiconductor material, Silicon, SiC or GaN. Though the basic mechanism of failure varies with device type, failure is invariably initiated by the creation of ionizing spallation fragments following a collision of a high-energy neutron with a substrate nucleus. This paper summarizes the results of device simulations and dedicated experiments to substantiate our knowledge about failure mechanisms. It will discuss the possibilities of failure rate prediction for different device types and classes. Main focus of this paper is the presentation and discussion of methods for the determination of failure rates by accelerated testing. Results of nucleon irradiation test are compared with storage tests. The effect of bias voltage and temperature, which are the main stressors, is discussed.     

Some aspects on ruggedness of SiC power devices

This article is on effects that can destroy SiC power semiconductor devices. The failure physics in SiC devices are discussed based on the well understood effects in silicon devices. In some device properties, such as surge current, short circuit, static avalanche and dynamic avalanche, SiC has significant possible advantages compared to silicon. For cosmic ray stability, there are no unique results. Regarding thermal mechanical stress on interface materials, SiC is more challenging. The same may hold for electrical stress in passivation layers at the junction termination.     

Reliability evaluation of a silicon-on-silicon MCM-D package

This paper presents the results of reliability testing on a multichip module technology with active silicon substrates. The modules use flip-chip technology to attach silicon chips to the active substrate and this assembly is then packaged into a plastic ball grid array package. Performance was evaluated using two custom designed test chips incorporating thermal, thermomechanical, electrical and reliability test structures. A rigorous environmental test sequence including temperature, cycling, humidity, highly accelerated stress test and power cycling were carried out on the demonstrators. A full destructive physical analysis was then performed, consisting of die/substrate shear, wire bond pull tests and microsectioning.     

A simple metal-semiconductor substructure for the advanced thermo-mechanical numerical modeling of the power integrated circuits

The metallization of double-diffused metal-oxide semiconductor (DMOS) power devices, which operate under fast thermal cycling (FTC), undergoes thermal induced plastic metal deformation (TPMD). The design of the metallization has a significant impact on the device lifetime and thus requires a thorough understanding of the temperature, stress and strain distribution. A simple three-dimensional (3D) transistor substructure which is commonly found in various high integration Bipolar-CMOS-DMOS (BCD) technologies is analysed. The thermomechanical behaviour is studied with the finite element method (FEM) for investigation of two potential failure mechanisms: delamination of power metal and accumulation of plastic deformation in signal metallization layer (which leads to inter-metal dielectric cracking). These failure mechanisms are analysed on two versions of the structure: the first one has only signal and power metal lines and the second one has vias, in addition to the signal and power metal lines. The target of the paper is to propose an efficient finite element analysis (FEA) model that can be used for a qualitative assessment of thermo-mechanical phenomena in the metal system of high integration BCD technologies.     

Preliminary reliability assessment and failure physical analysis on AlGaN/GaN HEMTs COTS

GaN based FETs have demonstrated high microwave performance since several years, and exhibit attractive potential for microwave power source in electronic warfare and military radar application, and also for civilian telecommunication applications like wireless basestations, Wi-Max, Wi-Fi as well. Up to now, the main challenge remaining for this technology is the proof of good reliability. The Information Warfare Technology Center (CELAR) launched a GaN COTS assessment campaign in order to achieve a state of the art on this topic. In this paper, we presented and discussed the first results of a life test evaluation on HFET GaN/AlGaN structure on silicon substrate and the first results of investigations by physical analysis on a failed device. These preliminary reliability investigations show all the importance of reliability tests conditions applied in order to compare reliability results and also, the benefits of a screening to obtain representative technology quality of the batch of sample before stress. Our investigations on failure analysis by STEM around the gate area of a failed device show defects which could be responsible of a degradation of the Schottky gate.     

Thermal optimization of GaN-on-Si HEMTs with plastic package

In this paper, the degradation of a GaN-on-Si based RF power amplifier is investigated by means of electrical characterization. The reliability issues identified during this work are clearly related to the high thermal resistance between the device and the heat sink, which causes gate-leakage current and output power degradation. Moreover, we have demonstrated a low cost thermal optimization approach by increasing the thermal dissipation area and reducing the device carrier thickness. Measurement results show that the saturated output power can be increased from 1 W up to 5 W without device degradation at 3.8 GHz.     

Three-dimensional flip-chip on flex packaging for power electronicsapplications

We have extended the concept of flip-chip technology, which is widely used in IC packaging, to the packaging of three-dimensional (3-D) integrated power electronics modules (IPEMs). We call this new approach flip-chip on flex IPEM (FCOF-IPEM), because the power devices are flip-chip bonded to a flexible substrate with control circuits. We have developed a novel triple-stacked solder bump metallurgy for improved and reliable device interconnections. In this multilayer structure, we have carefully selected packaging materials that distribute the thermo-mechanical stresses caused by mismatching coefficients of thermal expansion (CTEs) among silicon chips and substrates. We have demonstrated the feasibility of this packaging approach by constructing modules with two insulated gate bipolar transistors (IGBTs), two diodes, and a simple gate driver circuit. Fabricated FCOF-IPEMs have been successfully tested at power levels up to 10 kW. This paper presents the materials and reliability issues in the package design along with electrical, mechanical, and thermal test results for a packaged IPEM     

Prediction of interfacial delamination in stacked IC structures using combined experimental and simulation methods

Interfacial delamination is an often-observed failure mode in multi-layered IC packaging structures, which will not only influence the yield of wafer processes, but also have direct impact on the packaging reliability. The difference in coefficient of thermal expansion, together with thermal and thermal–mechanical loading are the main driving forces for interfacial delamination. First of all, this type of delamination is considered as a mixed mode of failure at the material interfaces. Hence, at least two stress components are needed to predict its occurrence. However, due to the singular stress field at the interface, one could hardly obtain the correct stresses at the interface. Therefore, a combined experimental–numerical method is used to investigate the initiation and propagation of the interface delamination. The purpose of the experimental shear and tensile tests is to measure the critical loads, at which delamination initiates. Then, a Finite Element (FE) model is constructed to convert the critical load into critical failure data for further numerical investigation. The FE model is so constructed that it reproduces the geometrical configurations of the tests. Due to the singular stress distribution at the interface, the calculated local stresses will be both mesh and residual-stiffness dependent. The influences of the FE parameters on the interface stresses are studied. After that, a progressive failure approach is, in combination with a group of failure criteria and the estimated local critical stresses, applied to predict the initiation and propagation of the delamination between epoxy mould compound and the passivation layer in the Integrated Circuit (IC) for three different package structures. The present method and the obtained results are valuable to determine design rules for IC packaging structures.     

Reliability and performance limitations in SiC power devices

Despite silicon carbide’s (SiC’s) high breakdown electric field, high thermal conductivity and wide bandgap, it faces certain reliability challenges when used to make conventional power device structures like power MOS-based devices, bipolar-mode diodes and thyristors, and Schottky contact-based devices operating at high temperatures. The performance and reliability issues unique to SiC discussed here include: (a) MOS channel conductance/gate dielectric reliability trade-off due to lower channel mobility as well as SiC–SiO₂ barrier lowering due to interface traps; (b) reduction in breakdown field and increased leakage current due to material defects; and (c) increased leakage current in SiC Schottky devices at high temperatures.Although a natural oxide is considered a significant advantage for realizing power MOSFETs and IGBTs in SiC, devices to date have suffered from poor inversion channel mobility. Furthermore, the high interface state density presently found in the SiC–SiO₂ system causes the barrier height between SiC and SiO₂ to be reduced, resulting in increased carrier injection in the oxide. A survey of alternative dielectrics shows that most suffer from an even smaller conduction band offset at the SiC–dielectric interface than the corresponding Silicon–dielectric interface and have a lower breakdown field strength than SiO₂. Thus, an attractive solution to reduce tunneling such as stacked dielectrics is required.In Schottky-based power devices, the reverse leakage currents are dominated by the Schottky barrier height, which is in the 0.7–1.2 eV range. Because the Schottky leakage current increases with temperature, the SiC Schottky devices have a reduction in performance at high temperature similar to that of Silcon PN junction-based devices, and they do not have the high temperature performance benefit associated with the wider bandgap of SiC.Defects in contemporary SiC wafers and epitaxial layers have also been shown to reduce critical breakdown electric field, result in higher leakage currents, and degrade the on-state performance of devices. These defects include micropipes, dislocations, grain boundaries and epitaxial defects. Optical observation of PN diodes undergoing on-state degradation shows a simultaneous formation of mobile and propagating crystal stacking faults. These faults nucleate at grain boundaries and permeate throughout the active area of the device, thus degrading device performance after extended operation.     

Validation of TSV thermo-mechanical simulation by stress measurement

Because of the large mismatch in coefficients of thermal expansion (CTE) between copper vias and the silicon substrate in through-silicon vias (TSVs), thermal stresses are induced. These stresses cause severe reliability issues, such as performance degradation of stress-sensitive devices, and interfacial delamination between TSVs and the silicon substrate. Finite element method (FEM) simulation is a useful tool for thermal stress analysis; however, developers and users are concerned about the range of accuracy of simulation models. Direct validation of the thermal simulation via stress measurement is extremely difficult. As non-destructive methods can measure the stresses only at the surface or several micrometers below, it is difficult to measure the internal stresses. Furthermore, any attempt to use an internal measurement location in the sample affects the stress situation. We propose a methodology to validate the simulation model with stress measurements using polarized Raman spectroscopy on cross-sections of TSV samples. The stress-free assumption at room temperature for simulation was compensated for using the measured residual stresses. An accurate comparison of stress data between experiment and simulation was achieved by considering the re-location of measurement points under thermal deformation. The agreement between simulation and experimental data for radial and axial thermal stresses validated the simulation model.The validated simulation model is useful for structural parametric analysis of TSV. The proposed methodology with stress measurement by polarized Raman spectroscopy and stress analysis by simulation can be used to study the radial and axial thermal stress of other devices.     

Unclamped inductive switching behaviour of high power SOI vertical DMOS transistors with lateral drain contacts

The switching dynamics of silicon-on-insulator (SOI) high power vertical double diffused MOS (VDMOS) transistors with an inductive load has been investigated by device simulation. Unlike other conventional VDMOS devices, this device has drain contacts at the top surface. In general the switching behaviour of a power device during the unclamped inductive switching (UIS) test will determine the reliability of the power device as the energy stored in the inductor during the on state is dumped directly into the device when it is turned off. In this paper we compare the switching dynamics of the SOI VDMOS transistor with standard bulk silicon VDMOS device by doing numerical simulations. It is shown here, using 2D-device simulations that the power dissipated in the SOI VDMOS device during the UIS test is smaller by approximately a factor of 2 than in the standard bulk silicon VDMOSFET. The lower dissipation is due to the presence of the silicon film/buried oxide/substrate structure (this structure forms a SOI capacitor). In the case of the SOI VDMOS transistor the energy released from the inductor during the UIS test is stored to some extent in the SOI capacitor and partly dumped directly into the device. As a result the maximum current through the SOI device is separated in time from the maximum voltage across the device, unlike in the bulk case, thereby reducing the maximum power.     

An RDL UBM Structural Design for Solving Ultralow-K Delamination Problem of Cu Pillar Bump Flip Chip BGA Packaging

Copper (Cu) pillar bumps tend to induce high thermal–mechanical stress during environmental tests and fabrication processes due to the high hardness of Cu, especially when applied with an ultralow-K (ULK) chip. A previous experiment showed that interfacial delamination was often observed in the ULK layers of conventional Cu pillar bump-type flip chip ball grid array (FCBGA) packages under thermal cycling, where under bump metallurgy (UBM) layers directly sit on the metal pads of silicon chips (herein termed ‘‘direct UBM structure’’). In this study, a UBM pad relocation scheme through redistribution layer (RDL) technology (herein termed ‘‘RDL UBM structure’’) is proposed to relieve the stress or ULK delamination issue. The proposed technique is tested on Cu pillar bump-type FCBGA packages subjected to thermal loading, the effectiveness of which is demonstrated through finite element stress simulation and experimental reliability tests. Simulation results reveal that the RDL UBM structure can greatly reduce the maximum stress in the ULK layers by as much as about 10% to 44%. Besides, it turns out that the Cu pillar bump-type FCBGA packages with the RDL UBM structure show good interconnect reliability performance in terms of thermal cycling, highly accelerated stress, and high-temperature storage.