Modeling and simulation of enhancement mode p-GaN Gate AlGaN/GaN HEMT for RF circuit switch applications

An enhancement mode p-GaN gate AlGaN/GaN HEMT is proposed and a physics based virtual source charge model with Landauer approach for electron transport has been developed using Verilog-A and simulated using Cadence Spectre, in order to predict device characteristics such as threshold voltage, drain current and gate capacitance. The drain current model incorporates important physical effects such as velocity saturation, short channel effects like DIBL (drain induced barrier lowering), channel length modulation (CLM), and mobility degradation due to self-heating. The predicted I_d-V_ds, I_d-V_gs, and C-V characteristics show an excellent agreement with the experimental data for both drain current and capacitance which validate the model. The developed model was then utilized to design and simulate a single-pole single-throw (SPST) RF switch.     

Evidence for causality between GaN RF HEMT degradation and the EC-0.57 eV trap in GaN

The degradation of industry-supplied GaN high electron mobility transistors (HEMTs) subjected to accelerated life testing (ALT) is directly related to increases in concentrations of two defects with trap energies of E_C-0.57 and E_C-0.75 eV. Pulsed I-V measurements and constant drain current deep level transient spectroscopy were employed to evaluate the quantitative impact of each trap. The trap concentration increases were only observed in devices that showed a 1 dB drop in output power and not the result of the ALT itself indicating that these traps and primarily the E_C-0.57 eV trap are responsible for the output power degradation. Increases from the E_C-0.57 eV level were responsible for 80% of the increased knee walkout while the E_C-0.75 eV contributed only 20%. These traps are located in the drain access region, likely in the GaN buffer, and cause increased knee walkout after the application of drain voltage.     

Failure mechanism analysis of off-state drain-to-source leakage current failure of a commercial 650 V discrete GaN-on-Si HEMT power device by accelerated power cycling test

A gallium nitride on silicon substrate (GaN-on-Si) high-electron-mobility transistor (HEMT) power device is commercially available. The package-level reliability of a GaN-based power device is necessary to respond market demands. Power cycling (PC) tests are a useful method to investigate the reliability of a packaged power component closer to a real application. An off-state drain-to-source leakage current failure (IDSS) of a 650 V discrete GaN-on-Si power device under PC test was reported in a previous study. In this paper, to investigate failure mechanism from the last study experiments to verify the root cause are conducted. Scanning acoustic microscope (SAM) images of failure samples exhibit the solder delamination between the discrete chip and the lead frame. The reasonable hypothesis of a correlation between the delamination and IDSS failure is suggested and is tested with a detailed analysis and supplemental experiments. In the process of analyzing the above hypothesis, the new risk of IDSS failure caused by losing electrical connection of silicon substrate rises. The solution for the risk also is proposed. It is discussed that the IDSS failure phenomenon is related to thermal stress induced during PC test. The tests and the analysis indicate that the failure is a thermal stress induced IDSS leakage, not matched previously reported mechanisms.     

A compact C–V model for 120 nm AlGaN/GaN HEMT with modified field dependent mobility for high frequency applications

We present a theoretical model of AlGaN/GaN high electron mobility transistor (HEMT) that includes the effect of spontaneous and piezoelectric polarization. Present model also incorporates the effect of mole fraction dependent mobility, saturation velocity and the accurate 2-DEG density in HEMT as a function of gate voltage in subthreshold, linear and saturation regimes. This paper reports a detailed 2-D analysis of capacitance–voltage (C–V) characteristics. The contribution of various capacitances including fringing field capacitance on the performance of the device is also shown. The model further predicts the transconductance, drain conductance and frequency of operation and is in close proximity with the experimental data which confirms the validity of proposed model.     

Electrical and thermal failure modes of 600 V p-gate GaN HEMTs

A study of electrical and thermal failure modes of 600 V p-doped GaN HEMTs is presented, which focuses on the investigation of short-circuit limitations. The electrical failure mode seems to be an electrical field breakdown in the structure which is caused by excessive carrier concentration, rather than primary thermal generated. Accordingly, a thermal failure mode is observed, which features a distinctive behaviour and seems to be similar to schottky-gate HEMTs. Concerning the electrical failure mode, a specific p-gate HEMT short-circuit safe operating area (SCSOA) is presented as a novelty. However, a short-circuit capability of up to 520 V can be achieved, regarding the design of the gate-drive circuit.     

Reliability enhancement with the aid of transient infrared thermal analysis of smart Power MOSFETs during short circuit operation

The usage of novel measurement techniques enhances the capabilities of researchers and power device manufacturers to understand and address reliability problems in novel Smart Power Devices. Along this line of argument, this work describes a method to improve the reliability of the smart Power MOSFET devices by design. The design optimization process involves Silicon layout, interconnections, packaging and protection strategy as well. Accurate thermal transient analyses, made possible by the unique features of a custom infrared radiometric microscope experimental setup which allows dynamic temperature detection with a bandwidth of 1 MHz over the chip area, indicated the way to minimize peak temperature and to verify the effect of the optimization.     

Influence of the Source–Gate Distance on the AlGaN/GaN HEMT Performance

In this paper, we present Monte Carlo simulation results on the source-gate (S-G) scaling effects in GaN-based HEMTs. The results show that a downscaling of the S-G distance can improve device performance, enhancing the output current and the device transconductance. The main reason for this effect is related to the peculiar dynamic of electrons in the GaN-based HEMTs, which leads to a nonsaturated velocity regime in the source access region, even for high drain applied voltages. On the contrary, the gate-drain distance does not affect the output current within the analyzed device geometries. Based on these results, new optimization strategies for GaN HEMTs could be defined     

Record 1.0 V open‐circuit voltage in wide band gap chalcopyrite solar cells

Tandem solar cell structures require a high‐performance wide band gap absorber as top cell. A possible candidate is CuGaSe₂, with a fundamental band gap of 1.7 eV. However, a significant open‐circuit voltage deficit is often reported for wide band gap chalcopyrite solar cells like CuGaSe₂. In this paper, we show that the open‐circuit voltage can be drastically improved in wide band gap p‐Cu(In,Ga)Se₂ and p‐CuGaSe₂ devices by improving the conduction band alignment to the n‐type buffer layer. This is accomplished by using Zn_1−x Sn_x O_y , grown by atomic layer deposition, as a buffer layer. In this case, the conduction band level can be adapted to an almost perfect fit to the wide band gap Cu(In,Ga)Se₂ and CuGaSe₂ materials. With an improved buffer band alignment for CuGaSe₂ absorbers, evaporated in a 3‐stage type process, we show devices exhibiting open‐circuit voltages up to 1017 mV, and efficiencies up to 11.9%. This is to the best of our knowledge the highest reported open‐circuit voltage and efficiency for a CuGaSe₂ device. Temperature‐dependent current‐voltage measurements show that the high open‐circuit voltage is explained by reduced interface recombination, which makes it possible to separate the influence of absorber quality from interface recombination in future studies.     

Hydrodynamic simulation of surface traps in the AlGaN/GaN HEMT

Computer simulation of an AlGaN/GaN HEMT is carried out using commercially available software DESSIS. Traps located at the top of the AlGaN layer have been identified as being the primary source of electrons in the AlGaN/GaN HEMT. Recent experiments have focused on their role in HEMT performance with regard to the virtual gate effect and current collapse. In this work, analysis is carried out on these devices through the development of two different models designed to describe the 2DEG formation. Simulation of these models using the hydrodynamic model, which takes into account heating of the electrons, has been carried out to provide a more detailed understanding of the role of surface traps.     

DC and microwave characteristics of Lg 50 nm T-gate InAlN/AlN/GaN HEMT for future high power RF applications

The DC and microwave characteristics of L_g = 50 nm T-gate InAlN/AlN/GaN High Electron Mobility Transistor (HEMT) on SiC substrate with heavily doped n+ GaN source and drain regions have demonstrated using Synopsys TCAD tool. The proposed device features an AlN spacer layer, AlGaN back-barrier and SiN surface passivation. The proposed HEMT exhibits a maximum drain current density of 1.8 A/mm, peak transconductance (g_m) of 650 mS/mm and ft/fmax of 118/210 GHz. At room temperature, the measured carrier mobility, sheet charge carrier density (n_s) and breakdown voltage are 1195 cm²/Vs, 1.6 × 10¹³ cm⁻² and 18 V respectively. The superlatives of the proposed HEMTs are bewitching competitor for future monolithic microwave integrated circuits (MMIC) applications particularly in W-band (75–110 GHz) high power RF applications.     

Analysis and resolution of a thermally accelerated early life failure mechanism in a 40 V GaN FET

An early life failure mechanism was discovered on a 0.25-µm 40 V GaN FET technology. Through accelerated life testing (ALT), it was determined that the early life failure mechanism was thermally accelerated with a high activation energy, which means that it is not a concern a normal operating conditions up to the maximum rated junction temperature. Subsequent improvements to the process resulted in elimination of the early life failure mechanism. With the improved process, single-mode ALT lifetime distributions and excellent reliability performance down to low failure fractions were demonstrated.     

Trapping Effects in the Transient Response of AlGaN/GaN HEMT Devices

In this paper, the transient analysis of an AlGaN/GaN high-electron mobility transistor (HEMT) device is presented. Drain-current dispersion effects are investigated when gate or drain voltages are pulsed. Gate-lag and drain-lag turn-on measurements are analyzed, revealing clear mechanisms of current collapse and related dispersion effects. Numerical 2-D transient simulations considering surface traps effects in a physical HEMT model have also been carried out. A comparison between experimental and theoretical results is shown. The presence of donor-type traps acting as hole traps, due to their low energy level of 0.25 eV relative to the valence band, with densities >1e20 cm^-3 (>5e12 cm^-2), uniformly distributed at the HEMT surface, and interacting with the free holes that accumulated at the top surface due to piezoelectric fields, accounts for the experimentally observed effects. Time constants next to 10 ms are deduced. Some additional features in the measured transient currents, with faster time constants, could not be associated with surface states     

New degradation mechanism observed for AlGaN/GaN HEMTs with sub 100 nm scale unpassivated regions around the gate periphery

AlGaN/GaN HEMTs with low gate leakage current in the μA/mm range have been fabricated with a small-unpassivated region close to the gate foot. They showed considerably higher critical voltage values (average VCR = 60 V) if subjected to step stress testing at OFF-state conditions and room temperature as compared to standard devices with conventional gate technology. This is due to the fact that electrons injected from the gate can be accumulated at the unpassivated region and thus builds up negative charge. The lower gate leakage is due to virtual gate formation, which is reducing local electric field in the vicinity of the gate. In contrast to devices with standard gate technology, degradation during step stressing is not associated with a simultaneous gate leakage and drain leakage current increase but with a strong increase of drain current at OFF-state conditions while the gate leakage is practically not affected. Then a relatively higher critical voltage of around 60 V is achieved. An abrupt increase of subthreshold drain current implies the formation of a conductive channel bypassing the gate region without influencing gate leakage. It is believed that hopping conductivity via point defects formed during device stressing creates this channel. Once this degradation mode takes place, the drain current of affected devices significantly drops. This can be explained by negative trap formation in the channel region affecting the total charge balance in 2DEG region. Electroluminescence measurements on both fresh and degraded devices showed no hot spots at OFF-state conditions. However, there is additional emission at ON-state bias, which suggests additional energetic states that lead to radiative electron transition effects in the degraded devices, most possibly defect states in the buffer.     

AlGaN/GaN HEMT栅阶跃脉冲响应实验研究

通过对AlGaN/GaN HEMT漏极电流栅阶跃脉冲响应实验测试,发现栅脉冲相同时,HEMT开启时间在线性区随VDS增加而增加,而在饱和区随VDS增加而减小;在VDS一定时,器件开启时间随栅脉冲低电平的降低而增加。基于表面态电子释放过程与ID、VDS和阶跃脉冲之间关系的分析,提出了用快电子与慢电子释放两种过程来解释表面态电子弛豫,并建立漏极电流响应过程拟合算式。拟合得到与快、慢电子释放相关的时间常数分别为τ1=0.23s、τ2=1.38s,且拟合曲线与实验结果的最大误差不超过测试值的3%。该研究结果有助于电流崩塌机理的进一步探索。     

The influence of 1 nm AlN interlayer on properties of the Al0.3Ga0.7N/AlN/GaN HEMT structure

The sheet carrier concentrations, conduction band profiles and amount of free carriers in the barriers have been determined by solving coupled Schrödinger and Poisson equation self-consistently for coherently grown Al_0.3Ga_0.7N/GaN and Al_0.3Ga_0.7N/AlN/GaN structures on thick GaN. The Al_0.3Ga_0.7N/GaN heterojunction structures with and without 1 nm AlN interlayer have been grown by MOCVD on sapphire substrate, the physical properties for these two structures have been investigated by various instruments such as Hall measurement and X-ray diffraction. By comparison of the theoretical and experimental results, we demonstrate that the sheet carrier concentration and the electrons mobility would be improved by the introduction of an AlN interlayer for Al_0.3Ga_0.7N/GaN structure. Mechanisms for the increasing of the sheet carrier concentration and the electrons mobility will be discussed in this paper.     

Experimental observation of velocity overshoot in n-channelAlGaAs/InGaAs/GaAs enhancement mode MODFETs

Velocity overshoot phenomena in n-channel Al-GaAs/InGaAs/GaAs enhancement mode MODFETs have been investigated for gate lengths ranging from 1 to 0.5 μm. The study is based on Motorola's established CGaAs ^TM technology. The observed average electron velocity υ _aυ under the gate is 1.05, 1.34, 1.48, and 1.71×10 ⁷ cm/s for a gate length L_G of 1, 0.7, 0.6, and 0.5 μm, respectively. The presence of velocity overshoot in InGaAs channels is clearly proven with average electron velocities exceeding the steady-state saturation velocity of ≅1×10⁷ cm/s for L_G⩽0.7 μm, and with the significant increase of υ_aυ with shorter gate length     

On the temperature and carrier density dependence of electron saturation velocity in an AlGaN/GaN HEMT

The temperature and carrier density dependence of electron intrinsic saturation velocity (v/sub si/) in a 0.3-/spl mu/m gate length AlGaN/GaN HEMT was extracted from multibias S-parameter measurements. It was found that v/sub si/ fell rapidly with increasing sheet carrier concentration (n/sub s/), but was only a very weak function of ambient temperature (T/sub amb/). This behavior is consistent with the hot-phonon model of carrier transport.     

Experimental and theoretical studies of I—V characteristics of zinc-doped silicon p-n junctions using the exact DC circuit model

The exact distributed steady-state equivalent circuit model is used to calculate the forward current-voltage characteristics of zinc-doped p-n junction diodes. The experimental values of the Shockley-Read-Hall (SRH) coefficients at zinc centers in silicon and measured recombination center (zinc) density were used in the model. The theoretical forwardI-Vcharacteristics are compared with experimentalI-Vover a wide range of temperatures, showing excellent agreement.     

Formation of Ohmic contacts in AlGaN/GaN HEMT structures at 500 °C by Ohmic contact recess etching

Good Ti/Al/Ti/Au Ohmic contacts were achieved in undoped-AlGaN/GaN HEMT structures at 500 °C (measured by a thermocouple) by using an Ohmic contact recess etch. The Ohmic recess etch is deeper than the undoped AlGaN layer and hence reaches the two-dimensional electron gas. Good morphology and well-defined edge profile are also achieved. Because of the low temperature, this process can tolerate quite some water vapor related issue during Ohmic contact anneal.     

雪崩晶体管退压电路用于电光调Q的实验研究

采用雪崩晶体管作退压开关元件比冷阴极陶瓷触发管有许多优点。 通过电路分析和实验对比我们得到如下的结论: 一、雪崩晶体管可作电光Q开关的退压开关元件,激光工作正常。 二、雪崩晶体管比冷阴极陶瓷触发管有以下几方面优点:(1)激光输出功率增加15～20％;(2)激光输出脉宽变窄1～2毫微秒;(3)激光输出功率稳定性好,均方根差≤3％,同