Theoretical analysis of high-k dielectric gate stacks

Density functional theory (DFT) has proved to be a useful tool in engineering of emerging research devices. At the nanoscale, and particularly when novel materials are involved, it provides not only the fundamental understanding of the microscopic physics governing the behavior of a system, but often can give quantitative results that can be directly used in process development. In this paper we briefly review the recent applications of DFT in the area of the advanced gate stack materials engineering     

The properties of high-k gate dielectric films deposited on HRSOI

In this paper, HfO₂ dielectric films with blocking layers (BL) of Al₂O₃ were deposited on high resistivity silicon-on-insulator (HRSOI), and the interfacial and electrical properties are reported. High-resolution transmission electron microscopy (HRTEM) indicated that BL could thin the interfacial layer, keep the interface smooth, and retain HfO₂ amorphous after annealing. Energy dispersive X-ray spectroscopy (EDS) and X-ray photoelectron spectroscopy (XPS) confirmed that BL weaken Si diffusion and suppressed the further growth of HfSiO. Electrical measurements indicated that there was no hysteresis was observed in capacitance–voltage curves, and Flatband shift and interface state density is 0.05 V and −1.3 × 10¹² cm⁻², respectively.     

Electrical characteristics of gold nanoparticle-embedded MIS capacitors with parylene gate dielectric

Memory characteristics of gold nanoparticle-embedded metal–insulator–semiconductor (MIS) capacitors with polymer (parylene-C) gate insulating material are investigated in this study. The gold nanoparticles used in this work were synthesized by the colloidal method. Current density versus voltage curves obtained from the MIS capacitors exhibit better performance for the parylene-C gate insulator, compared with other gate insulating materials. Capacitance versus voltage (C–V) curves show a flat band voltage shift, which indicates the possibility of charge storage in the gold nanoparticles. In addition, the charge retention characteristic for the gold nanoparticle-embedded MIS capacitor is described in this paper.     

Investigation of strontium tantalate thin films for high-k gate dielectric applications

Strontium tantalate (STO) films were grown by liquid-delivery (LD) metalorganic chemical vapor deposition (MOCVD) using Sr[Ta(OEt)₅(OC₂H₄OMe)]₂ as precursor. The deposition of the films was investigated in dependence on process conditions, such as substrate temperature, pressure, and concentration of the precursor. The growth rate varied from 4 to 300 nm/h and the highest rates were observed at the higher process temperature, pressure, and concentration of the precursor. The films were annealed at temperatures ranging from 600 to 1000 °C. Transmission electron microscopy (TEM), X-ray diffraction (XRD), and ellipsometry indicated that the as-deposited and the annealed films were uniform and amorphous and a thin (>2 nm) SiO₂ interlayer was found. Crystallization took place at temperatures of about 1000 °C. Annealing at moderate temperatures was found to improve the electrical characteristics despite different film thickness (effective dielectric constant up to 40, the leakage current up to 6×10⁻⁸ A/cm², and lowest midgap density value of 8×10¹⁰ eV⁻¹ cm⁻²) and did not change the uniformity of the STO films, while annealing at higher temperatures (1000 °C) created voids in the film and enhanced the SiO₂ interlayer thickness, which made the electrical properties worse. Thus, annealing temperatures of about 800 °C resulted in an optimum of the electrical properties of the STO films for gate dielectric applications.     

外延CeO2高k栅介质层的结构及介电性能

利用脉冲激光沉积两步生长法在Si(111)衬底上制备了厚度为10～40nm的外延CeO<,2>薄膜,构建了Pt/CeO<,2>/Si MOS结构.研究了CeO<,2>薄膜的界面及介电性能,实验发现,界面处存在的电荷对MOS结构C-V特性的测量有较大影响,采用两步生长法制备的外延CeO<,2>薄膜在保持较大介电常数的同时...     

高k栅介质SOILDMOS管阈特性分析与建模

通过分析高k栅介质SOI LDMOS管沟道与埋氧层的关系,建立了SOI LDMOS管的阈特性模型。研究了器件主要结构参数对阈特性及小尺寸效应的影响,分析了阈值电压与高k栅介质的介电常数和应变Si层的掺杂浓度的关系。通过软件ISE TCAD进行模拟仿真。结果表明,在不同的tSi和NA条件下,阈值电压的模型计算与数值模拟值吻合率为94.8%,最大差值为0.012 V,不同沟道长度SOI LDMOS的阈值电压漂移率为3.52%,最大漂移电压为0.008 V,模型计算值与数值模拟结果基本吻合。     

Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET

Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide (SiO₂) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt to characterize the analog and RF performance of the high-k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2-D device simulation. The results demonstrates the impact of high-k oxide layer as single and gate stack (GS). The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performance exhibited by the device. The major figures of merit (FOMs) studied in this paper are transconductance (g_m), output conductance (g_d), transconductance generation factor (g_m/I_D), early voltage (V_EA), intrinsic gain (A_V), cut off frequency (f_T), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). The effects of downscaling of channel length (L) on analog performance of the proposed devices have also been presented. It has been observed that the performance enhancement of GS configurations (k=7.5 i.e device D5 in the study) is encouraging as far as the nanoscale DG-MOSFET is concerned. Also it significantly reduces the short channel effects (SCEs). Parameters like DC gain of (91.257 dB, 43.436 dB), nearly ideal values (39.765 V⁻¹, 39.589 V⁻¹) of TGF, an early voltage of (2.73 V, 16.897 V), cutoff frequency (294 GHz, 515.5 GHz) and GTFP of (5.14×10⁵ GHz/V, 1.72×10⁵ GHz/V) for two different values of V_DS=0.1 V and 0.5 V respectively are found to be close to ideal values. Analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper i.e. device D5.     

Cyanoethylated pullulan as a high-k solution processable polymer gate dielectric for SWCNT TFTs

Cyanoethylated pullulan (CEP), a high-k solution processable polymer gate dielectric, is used to fabricate bottom gated single wall carbon nanotube (SWCNT) network thin film transistors (TFTs). Both aqueous and organic dispersions of highly semiconducting enriched SWCNTs are used as the channel material. Use of CEP as the dielectric enables fabrication of devices operating at low voltage (<3 V) with high on-state currents, good on/off ratios (∼10⁵), low subthreshold swings (∼200 mV/decade) and minimal hysteresis (<1 V). However, despite high apparent mobilities extracted from gate voltage sweeps, driving these devices at even modest frequencies (>1 Hz) is found to significantly decrease the transconductance. This is shown to be related to a significant frequency dependence of the capacitance associated with a slow polarization response of the dielectric. Despite this limitation, CEP could be a useful dielectric in SWCNT TFTs for applications such as sensors and low frequency amplifiers.     

Deuterium passivation of interface traps in MOS devices

The mechanism for deuterium passivation of interface traps in MOS devices is studied. Normal channel hot electron (CHE) stress was performed on hydrogen-passivated devices to locally desorb hydrogen from the interface at the drain region. The stressed devices were annealed in deuterium at 400°C, resulting in a full recovery of device characteristics. These devices were then subjected to CHE stress again in two modes. Some of them were stressed in the normal mode while others were stressed in the reverse mode in which the source and drain were interchanged. Compared with hydrogenated devices, these deuterated devices under the normal stress exhibit a significant reduction in interface trap generation and threshold voltage shift. In contrast, insignificant reliability improvement was observed for the reverse stress case. The asymmetric degradation behaviors on these deuterated devices suggest that the effectiveness of implementing deuterium to improve device reliability is limited by its replacement of pre-existing hydrogen at the oxide/silicon interface     

Study of CVD nanowire high-k metal interface quality for interconnect level MOS devices

We report a study of low temperature gate stack on silicon nanowires compatible with Back-End-Of-Line (BEOL) integration. The same gate stack is deposited at low temperature on Si nanowires obtained thanks to either Chemical Vapor Deposition (CVD) or Selective Epitaxial Growth (SEG) in patterns. Gate stack characterization on CVD nanowires (NWs) shows low leakages and good agreement with simulated curves without interface states. A dramatic decrease of the capacitance in accumulation region and faster electron generation are observed and attributed to NW defects. In contrast, SEG devices reveals lower capacitance decrease with frequency but higher interface state density of about 10¹³ cm⁻².     

A nanoanalytical investigation of high-k dielectric gate stacks for GaAs based MOSFET devices

In this paper a quantitative determination of the elemental distributions across a ∼10 nm Ga₂O₃/GdGaO layer with a Pt metal gate cap on top of an InGaAs/AlGaAs/GaAs substrate is presented. Some effects of annealing on the elemental distribution across the Ga₂O₃/GdGaO oxide layer are described. The paper also discusses the analysis of the interface GaAs/Ga₂O₃/GGO at a sub-nm level by high-resolution HAADF STEM imaging.     

超薄高介电Er2O3栅介质薄膜的漏电机理

采用激光分子束外延设备在不同温度下制备了不同厚度的超薄晶态、非晶态高介电Er2O3栅介质薄膜,用X射线衍射和高分辨透射电镜分析了薄膜结构,用HP4142B半导体参数分析仪测试了Al/Er2O3/Si/Al结构MOS电容器的漏电流。XRD谱和HRTEM图像显示400℃以下制备的Er2O3薄膜呈非晶态,400℃到840℃制备的Er2O3薄膜是(111)方向高度择优取向的。电学测试表明：晶态Er2O3薄膜厚度由5.7 nm 减小到3.8 nm,漏电流密度从6.20×10-5 A/cm2突增到6.56×10-4 A/cm2,增加了一个数量级。而厚度3.8 nm的非晶Er2O3薄膜漏电流密度仅为1.73×10-5 A/cm2。漏电流数据分析显示高场下超薄Er2O3薄膜的漏电流主要来自于Fowler-Nordheim隧穿。低场下超薄晶态Er2O3薄膜较大的漏电流是由晶粒边界产生的杂质缺陷引起。     

A 2-D analytical threshold-voltage model for GeOI/GeON MOSFET with high-k gate dielectric

A 2-D analytical threshold-voltage model for ultra-thin-body MOSFET with buried insulator and high-k gate dielectric is established by solving the 2-D Poisson's equation for the gate-dielectric, channel and buried-insulator regions. The validity of the model is confirmed by comparing with experimental data and other models. Using the model, the influences of gate-dielectric permittivity, buried-insulator permittivity, channel thickness, buried-insulator thickness and channel doping concentration on threshold behaviors are investigated. It is found that the threshold behaviors can be improved by using buried insulator with low permittivity, thin channel and high channel doping concentration. However, the threshold performance would be degraded when high-k gate dielectric is used due to enhanced fringing-field effect.     

CHC degradation of strained devices based on SiON and high-k gate dielectric materials

A comparison between the Channel Hot-Carrier (CHC) degradation on strained pMOSFETs with SiGe source/drain (S/D) based on different gate dielectric materials, as SiON or HfSiON, has been done. The influence of the device channel orientation, channel length and temperature on the CHC damage has been studied.     

Temperature dependence of transfer characteristics of OTFT memory based on DNA-CTMA gate dielectric

A nonvolatile memory based on an organic thin-film transistor (OTFT) with a biopolymer of DNA-cetyltrimethylammonium chloride (DNA-CTMA) acting as the gate dielectric layer was fabricated. The transfer characteristics of the device prepared by both DNA alone and DNA-CTMA showed a very large and stable hysteresis. In order to analyze the memory mechanism, the temperature dependence of the transfer characteristics, electric conductivity, differential scanning calorimetry (DSC), thermally stimulated depolarization current (TSDC) as well as the dielectric property of the DNA-CTMA film have been investigated. As a result, the quasi-ferroelectric polarization originating from the alignment of the intrinsic dipole moment inside the DNA-CTMA complex was identified as the main source of hysteresis in the lower temperature region.     

Atomic-layer-deposited tantalum silicate as a gate dielectric for III-V MOS devices

TaSiO_x thin films with Si/(Ta + Si) mole fractions between 0 and 0.6 have been deposited using atomic-layer deposition on Si and InGaAs at 250 °C. Interface defects on InGaAs were on the order of 10¹² cm⁻² eV⁻¹, which is comparable to state-of-the-art Al₂O₃ deposited by atomic-layer deposition using Al(CH₃)₃ and H₂O while the dielectric permittivity of TaSiO_x is considerably higher.     

A methodology for the implementation of MOSFETs with a high-k dielectric gate material on the design of 90 nm technology circuits

Up to date, MOSFETs have been made through well established techniques that use SiO₂ as the gate dielectric and the related design issues are well established. The need to scale down device dimensions allowed researchers to seek for alternative materials, in order to replace SiO₂ as the gate dielectric. The implementation of such MOS devices in memory or logic circuits needs to take into account the effects that the use of the new gate dielectrics has on parameters such as the threshold voltage and the drain current. Hence, parameters such as the high dielectric constant values, extra oxide charges and process related defects at the physical level must be taken into account during the device design. As far as circuit applications are concerned, these changes may substantially affect the required performance. This paper presents and provides proposals about the issue of replacing commonly used parameters of the MOSFET modelling with new parameters, in which the presence of a gate dielectric with different properties from those of SiO₂ is taken into account. A stepwise procedure is described for the new device design. Moreover, a case study is presented which examines a memory circuit built up by such new technology devices. In particular, this paper presents and analyses the design of a DRAM cell made up of MOSFETs with an alternative gate dielectric. The 90 nm technology and the BSIM4 model equations are used to derive the single MOSFET behaviour and subsequently the DRAM circuit performance. The results are analysed and compared to those obtained from conventional SiO₂ devices. A cell layout is provided and the DRAM circuit characteristics are also presented.     

Multi-layer high-κ interpoly dielectric for floating gate flash memory devices

We present a systematic simulation and experimental study of tunneling leakage current of the interpoly dielectric (IPD) layer in a floating gate (FG) type flash memory. IPD layers with different structural and material combinations such as HfLaO and 4% Tb-doped HfO₂ were studied. It is shown that compared with a conventional Al₂O₃–HfO₂–Al₂O₃ high–low–high barrier structure, the HfO₂–Al₂O₃–HfO₂ multilayer IPD stack with a low–high–low barrier structure has a lower leakage current due to the longer effective electron tunneling distance. Results also show that multilayer IPD structure has advantage of better thermal stability compared to the single layer IPD. Further work with simulations and experiments results suggest that the presence of a thin interfacial layer between polysilicon FG and IPD can increase the magnitude of leakage current by two or three orders. Nitridation of polysilicon floating gate reduced the leakage current by around two orders of magnitude at a constant equivalent oxide thickness. This is due to the elimination of the interfacial layer between polysilicon and high-κ IPD.