Zero-Current Soft-Switching Performance of 1200-V PT Clustered Insulated Gate Bipolar Transistor

Zero-current soft-switching performance of a 1200-V, 20-A punch-through (PT) clustered insulated gate bipolar transistor (CIGBT) is evaluated in this paper. Turn-on over-voltage transients have been witnessed in 2D numerical simulations and experimental results. These have been shown to be influenced by circuit parameters and internal device structure. Conductivity modulation lag within the device is found to be dependant upon dI/dt; however, this alone does not explain the significant over-voltages at turn-on. The device structure is found to influence the magnitude of such voltage peaks. By optimization of the structure, over-voltages can be minimized, resulting in a significant improvement in losses compared to an IGBT. The current bump associated with zero-current turn-off has been analyzed under various dV/dt values and is influenced by circuit capacitance, switching timings, and carrier lifetime. Internal dynamics of the CIGBT have been analyzed to give an insight into the performance under zero-current switching (ZCS). ZCS tests at 600 V, 20 A have shown that the CIGBT performs well with respect to a commercial IGBT of the same rating. Dynamic saturation voltage of the CIGBT has been shown to be 15% lower at room temperatures to that of an equivalent IGBT.     

Theoretical modification of the negative Miller capacitance during the switching transients of IGBTs

The insulated gate bipolar transistor (IGBT) has negative Miller capacitance during switching transients. It has conventionally been attributed to the voltage dependency of the Miller capacitance. However this explanation has physical ambiguity, yet, it lacks a discussion of the conditions for the occurrence of negative Miller capacitance as well. We argue that it is the current dependence to the Miller capacitance that results in the negative case. In this paper, we provide a modification to the theoretical analysis of this phenomenon. The occurrence condition for it and the device parameters about it are discussed. It is discovered that the negative Miller capacitance must occur during the turn-off process for any IGBT, while it is relatively difficult during the turn-on process. At the device design level, the current gain of the PNP transistor in the IGBT is an important factor for the negative Miller capacitance.     

dV/dt对IPM中IGBT栅极电路的影响分析

The effect of dV/dt on the IGBT gate circuit in IPM is analyzed both by simulation and experiment.It is shown that a voltage slope applied across the collector-emitter terminals of the IGBT can induce a gate voltage spike through the feedback action of the parasitic capacitances of the IGBT.The dV/dt rate,gate-collector capacitance, gate-emitter capacitance and gate resistance have a direct influence on this voltage spike.The device with a higher dV/dt rate,gate-collector capacitance,gate resistance and lower gate-emitter capacitance is more prone to dV/dt induced self turn-on.By optimizing these parameters,the dV/dt induced voltage spike can be effectively controlled.     

IGBT关断瞬态电压尖峰影响及抑制

绝缘栅双极晶体管(IGBT)是一种性能优良的全控型电力电子器件,由于线路和器件内部分布电感的存在,关断时集电极电流的快速变化会感应产生一个较大的电压尖峰从而引起过电压击穿。分析了栅极结电容放电时间常数和拖尾电流对电压尖峰的影响,通过改变栅极驱动电阻和温度可以抑制电压尖峰。分析了电压尖峰引起过压击穿的失效机理以及失效模式,表明IGBT过压击穿引起失效的本质仍然是结温过高引起的热击穿失效。     

Application of the Shubnikov-de Haas oscillations in the characterization of Si MOSFET's and GaAs MODFET's

The Shubnikov-de Haas magnetoconductance oscillations were used to measure directly the gate-to-channel capacitance of Si MOSFET's and GaAs MODFET's, to detect the onset of parallel conduction in GaAs MODFET's, and to provide an approximate measure of channel length in sub-100-nm channel of Si MOSFET's. The measurements do not require knowledge of any device parameters, are immune to any gate parasitic capacitance, and are independent of source and drain series resistances. One needs to know only the magnetic field, the oscillation period (for gate-to-channel capacitance measurement), the gate voltage (for detection of the onset of parallel conduction), and the number of oscillation peaks (for the channel length characterization). Experimental results have shown that the characterization methods are accurate, and can be applied to FET's with sub-100-nm channel length.     

Modelling of the shoot-through phenomenon introduced by the next generation IGBT in inverter applications

The shoot-through phenomenon has not been fully discussed for high-power inverters with IGBTs. This is because a negative gate voltage is applied to IGBTs during off states. Recently, attention is paid to an improved gate driver with only a positive gate voltage in order to meet demands for simplification, integration, and reduction in power consumption as well as in cost of the gate driver. Moreover, the threshold voltage of the next-generation IGBT will decrease with microfabrication techniques of the gate structure. This will make the shoot-through phenomenon severer and degrade the inverter reliability with the next-generation IGBTs. The influence of the parasitic parameters in both the IGBT and circuit on the shoot-through mechanism has not been investigated so far.This paper clarifies the shoot-through mechanism and investigates the impact of the next generation IGBTs on the inverter reliability. The influence of the internal capacitance of IGBT including stray inductance on inverter reliability is experimentally confirmed.     

An advanced physics-based sub-circuit model of a punch-trough insulated gate bipolar transistor

An advanced sub-circuit model of the punch-trough insulated gate bipolar transistor (PT IGBT) based on the physics of internal device operation has been described in this article. The one-dimensional physical model of low-gain wide-base BJT is employed based on the equivalent non-linear lossy transmission line, whereas a SPICE Level 3 model is used for the diffused MOST part. The influence of voltage dependent drain-to-gate overlapping capacitance and the conductivity modulated base (drain) ohmic resistance are modelled separately. The main advantages of novel PT IGBT model are a small set of model parameters, an easy implementation in SPICE simulator and the high accuracy confirmed by comparing the simulation results with the electrical measurements of test power circuit.     

IGBT并联电流分配的研究

目前采用多个IGBT并联来提高电流容量在工业上得到广泛的应用。但IGBT自身参数的不一致以及电路结构布局的不对称,使得并联使用过程中电流分配出现不均衡现象,严重时甚至会烧毁器件。本文通过理论和实验分析,得出影响IGBT并联电流分配不均的原因。从而提出了改善IGBT电流不均的一些设施,最终选择对电路结构和栅极电阻进行优化来改善电流不均。     

一种低功耗4H-SiC IGBT的仿真研究

针对传统沟槽栅4H-SiC IGBT关断时间长且关断能量损耗高的问题,文中利用Silvaco TCAD设计并仿真了一种新型沟槽栅4H-SiC IGBT结构。通过在传统沟槽栅4H-SiC IGBT结构基础上进行改进,在N ⁺缓冲层中引入两组高掺杂浓度P区和N区,提高了N ⁺缓冲层施主浓度,折中了器件正向压降与关断能量损耗。在器件关断过程中,N ⁺缓冲层中处于反向偏置状态的PN结对N ^-漂移区中电场分布起到优化作用,加速了N ^-漂移区中电子抽取,在缩短器件关断时间和降低关断能量损耗的同时提升了击穿电压。Silvaco TCAD仿真结果显示,新型沟槽栅4H-SiC IGBT击穿电压为16 kV,在15 kV的耐压设计指标下,关断能量损耗低至4.63 mJ,相比传统结构降低了40.41%。     

Shielding region effects on a trench gate IGBT

In this paper we introduced the shielding region concept in order to relieve the electric field concentrated on the trench bottom corner. The shielded trench gate insulated gate bipolar transistor (IGBT) is a trench gate IGBT with a P+shielding region located in the bottom of a trench gate. By simulation results, we verified that a shielding region reduced the electric fields not only in the gate oxide but also in the P-base region. Compared with conventional trench gate IGBT, about 33% increment of forward breakdown voltages are achieved, but little forward voltage drop, which causes on-state loss to be increased by about 0.06 V in the shielded trench gate IGBT.     

The effect of high-K gate dielectrics on deep submicrometer CMOSdevice and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K_gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K_gate for different target subthreshold leakage currents has been identified     

Transient Performance Estimation of Charge Plasma Based Negative Capacitance Junctionless Tunnel FET

We investigate the transient behavior of an n-type double gate negative capacitance junctionless tunnel field effect transistor (NC-JLTFET). The structure is realized by using the work-function engineering of metal electrodes over a heavily doped n⁺ silicon channel and a ferroelectric gate stack to get negative capacitance behavior. The positive feedback in the electric dipoles of ferroelectric materials results in applied gate bias boosting. Various device transient parameters viz. transconductance, output resistance, output conductance, intrinsic gain, intrinsic gate delay, transconductance generation factor and unity gain frequency are analyzed using ac analysis of the device. To study the impact of the work-function variation of control and source gate on device performance, sensitivity analysis of the device has been carried out by varying these parameters. Simulation study reveals that it preserves inherent advantages of charge-plasma junctionless structure and exhibits improved transient behavior as well.     

Impact of High-k Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs

The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-effect transistors is studied over a wide range of dielectric permittivities k. It is observed that there is a decrease in the parasitic outer fringe capacitance C_of in addition to an increase in the internal fringe capacitance C_if with high-k dielectrics, which degrades the short-channel effects significantly. It is shown that fin width scaling is the most suitable approach to recover the degradation in the device performance due to high-k integration. Furthermore, from the circuit perspective, for the 32-nm technology generation, the presence of an optimum k for a given target subthreshold leakage current has been identified by various possible approaches such as fin width scaling, fin-doping adjustment, and gate work function engineering     

Reverse bias instabilities in bipolar power transistors withcellular layout

The different instabilities exhibited by power BJTs during inductive turn-off are classified, and then studied theoretically, by means of two-dimensional (2-D) simulator in which the device is simulated within a realistic external circuit, and experimentally, by means of a nondestructive method. It is shown that many instabilities originate by an interaction between electric field and charge within a single cell, which causes transit time oscillation phenomena. The role of the stray capacitance of the circuit in favoring these instabilities is described. Other kinds of instability cannot be understood by studying a single cell but rather require accounting for the interactions between cells. Finally, an “instability map” is used as a synthetic picture of the device behavior which ensures an easy way to link device behavior with its physical features     

A study on the short-circuit capability of field-stop IGBTs

The short-circuit failure mechanism of 1200 V trench gate field-stop insulated gate bipolar transistor (IGBT) has been investigated in this paper. Experimental testing shows that most of the devices failed during the blocking state after a few hundred microseconds of the short-circuit turn-off condition. This unusual failure mode was analyzed both with experimental and numerical investigation. It has been determined that due to significantly large leakage current, thermal run-away can occur causing device failure after short circuit turn-off. Due to the smaller heat capacity of the FS-IGBT structure, the device temperature after the turn-off becomes so high that the local heating produced by the high temperature leakage current results in the thermal run-away.     

Field-Line-Circuit Coupling Based Method for Predicting Radiated Electromagnetic Emission of IGBT-PMSM Drive System

Electric drive system with Insulated gate bipolar transistor (IGBT) power device is widely used in Electric vehicle (EV), which consists of inverter, cables and Permanent magnet synchronous motor (PMSM). Due to the fast switching in di/dt and dv/dt of IGBT device, the system produces serious radiated Electromagnetic interference (EMI) through the interconnection cables. Thus, modeling of EMI source, propagation path and load PMSM is the key to accurately evaluate the system's radiation level. In addition, the system's radiated EMI involves the integrated calculation of circuit, cable and electromagnetic field, which cannot be solved by using a single circuit or electromagnetic calculation method. Therefore, this paper develops an effective field-linecircuit coupling based method to investigate the radiated EMI problems for IGBT-PMSM drive system, which is validated by experimental measurement. Besides, the impact of power cable parameters on radiated EMI is discussed. The proposed approach has guiding significance for electromagnetic compatibility design of EV.     

IGBT过流关断主结边缘烧毁失效机理研究

针对4 500 V IGBT在过流关断过程中主结边缘烧毁失效的问题,设计了3种不同场板连接结构。为了分析失效机理,采用Sentaurus TCAD工具对IGBT的过流关断过程进行仿真,重点研究了主结边缘附近3种场板结构对过流关断的影响。结果表明,IGBT电阻区边缘场板结构参数是影响坚固性的重要因素,在一定程度上减小场板连接的倾斜角,可减弱主结附近电场强度,避免过流关断过程中器件在该处发生烧毁,提升了器件的动态坚固性。     

A new insulated gate tetrode with high drain breakdown potential and low miller feedback capacitance

Insulated gate field effect transistors (IGFET's) with the gate offset from the drain electrode exhibit high drain breakdown potential and very low Miller feedback capacitance. The new insulated gate tetrode (IGT) described in this paper utilizes a second stacked gate to create the offset channel. The main advantage is the possibility of optimizing the device performance, especially the drain breakdown potential for bothP-andN-channel devices. Considered in the paper are design and fabrication problems,V-Icharacteristics, drain breakdown potential, dynamic drain resistance, small-signal equivalent circuit, and large-signal limitations.P-channel IGT's with drain breakdown potentials up to 300 V have been built. The design of the IGT depends mainly on the tradeoff between drain breakdown potential and the limited frequency response caused by the time constant of the offset channel. The results to date indicate that the IGT has a large drain voltage range and an extremely low Miller feedback capacitance and is adaptable to different operating conditions. The IGT appears very promising for use in power amplifiers and switching applications.     

Physical CAD model for high-voltage IGBTs based on lumped-charge approach

A new insulated gate bipolar transistor (IGBT) model developed on a physical basis is presented. The Lumped-Charge method has been revised in order to point out a more general methodology for implementing the model into a circuit form. As an example, a version of the model for the popular PSPICE simulator is presented. The N-channel IGBT structure is described by means of an evolution of the PSPICE level-1 metal oxide semiconductor field effect transistor model. An accurate mobility model has been included to precisely predict the voltage drop in the ON state. Simulation results agree well with the experiments both in static and in switching operations. The comparison between the proposed and the native IGBT PSPICE model shows the better behavior of the former. The reasons for this result have been verified by means of two-dimensional MEDICI simulations. Moreover, the proposed model is able to predict the device behavior also in critical operations like its latchup during a turn-off under short-circuit conditions.