一种小型智能漏电保护器的工作原理

本文介绍一种在供电系统中适用的小型智能漏电保护器的功能和特点，分析了电路各部分的工作原理。     

灵敏的漏电保护器

市场上有些漏电保护器,功耗大,灵敏度不高,有时甚至不动作。本文介绍一种漏电保护器,其灵敏度较高,当有人触电或家电设备漏电时,能在0.1秒时间内切断电源,最大动作电流仅为1mA,在保护器所保护的电器线路恢复正常或漏电消失后,经30秒钟自动恢复供电。     

某型漏电保护器的分析与改进

为了有效防止武器系统试验过程中因电器设备绝缘损坏等原因引起漏电、触电等事故,保证人员安全以及武器装设备的正常运行和安全使用需要。通过对试验中使用的配电箱中漏电保护器的电路结构、工作原理的细致分析,并从试验工作中的需求出发,指出其工作过程中存在的不便之处并加以改进。扩展了其他方面的功能,使配电过程更加安全、可靠,一旦有故障发生,发现故障更加快速,有效缩短了排故时间,提高了工作效率。     

PIC单片机在漏电流保护器中的应用

本文叙述由电流互感器、PIC单片机、运算放大器等组成的智能漏电流保护器及其硬软件设计。智能漏电流保护器具有大漏电流和小漏电流控制,实现报警与保护作用,并具有缺相保护功能。     

漏电保护器的安装

漏电保护器是电器电路中一个重要部件,它对保护电器设备安全和人身安全起着极其重要的作用。在安装漏电保护器时应考虑以下几点。1.安装前必须对漏电保护器自检:先检查漏电保护器铭牌上的数据是否和使用要求相符,然后手动操作数次,观察其动作是否灵活,有无卡住现象。     

漏电保护器测试系统的设计

漏电保护器的性能对人身触电提供的安全保护起着重要作用.而漏电保护器的性能由它的漏电动作特性参数决定.随着对漏电保护的可靠性提高,对漏电保护器的漏电动作特性参数的测试提出了更高的要求.采用ARMLPC2132设计的漏电保护器动作特性自动测试系统,能自动对漏电保护器特性参数进行测试,为漏电保护器的性能研究、质量检验及生产提...     

漏电保护器的原理与使用

文章对触电的危害进行了分析,介绍了漏电保护器的原理,并指出了在使用漏电保护器时,应该注意的几个问题。     

漏电保护器智能化测试仪的设计

为了提高测量漏电保护器漏电动作特性参数的准确性,减少测量时间,实现漏电保护器的在线和非在线检测,设计了一种手持式漏电保护器测试仪。该测试仪采用ATmega32作为控制与数据处理核心,能自动对漏电保护器特性参数进行测试,既能检测非在线运行的漏电保护器,又能检测在线运行的漏电保护器,为漏电保护器的性能研究、质量检验及漏电保护技术的应用提供了有效手段。     

自制漏电保护器检测仪

市场购买的YLY-3系列漏电保护器检测仪,按照检测漏电保护器漏电动作电流（mA）值．选择检测仪器相适应的（mA）值检测按钮,并保持按下状态,有10mA、30mA、50mA、100mA值可选择。通过绿指示灯亮、红指示灯灭和电压表指示为零,表示检测通过。     

一种新型自复式过电压、欠电压保护器的设计

利用555集成块设计了一种新型自复式过电压、欠电压的低成本保护器。采用两个电压比较器构成双限电压比较器电路,具有判断电压准确误差小的特点,对于电压误差要求较高的仪器有很好的保护作用,同时还能根据负载的不同要求容易改变上限电压和下限电压。采用555触发器构成的延时电路,具有延时时间准确判断无误的特点,能根据负载的不同要求改变延时时间。采用控制继电器实现供电和断电的方法,很好地实现了保护器与负载的隔绝,使用更方便、安全。     

Analysis and design of a new COA-based current-mode instrumentation amplifier with robust performance against mismatches

In this paper, analysis and design of a new current-mode instrumentation amplifier (CMIA) circuit is presented. The proposed circuit employs two Current Operational Amplifiers (COA) as active building blocks, one resistor and two transistors operating as variable resistors to electronically control the differential-mode gain. The main feature of the proposed CMIA is that unlike most previously reported CMIAs, its CMRR has negligible sensitivity to mismatches. In addition, in the proposed circuit both active building blocks operate in negative feedback loop which results in an overall enhanced performance. SPICE simulation results using 0.18 μm TSMC CMOS parameters and supply voltage of ±0.9 V show a constant CMRR of about 51 dB regardless of mismatches and wide bandwidth ranging from 14.8 MHz to about 3 MHz for differential-mode gains between 3 and 18 dB, respectively.     

掺铒光纤放大器黑盒模型在波分复用系统中的实验验证

介绍了掺铒光纤放大器的黑盒模型 ,随后给出应用黑盒模型的参数测量步骤 ;测量了一台内部参数和结构未知的商用 EDFA对六信道 WDM光信号的放大光谱图。通过实测结果与黑盒模型仿真计算得到的结果相比较 ,证明了黑盒模型具有很好的精度 ,适用于估算商用波分复系统的性能。     

一种锂离子电池线性充电控制系统设计

在分析单节锂离子电池恒流(含涓流)与恒压独立充电方式的基本原理和典型结构基础上,根据锂离子(Li-ion)电池充电的基本功能要求,通过对恒流、恒压基本结构输出级耦合的控制方式,结合对电池电压与电流的精确检测与监控,设计了一种结构简单、控制稳定有效的锂电池线性充电控制系统.基于CSMC 0.6 μm CMOS工艺的仿真结果表明,系统在各种状态下均能可靠实现涓流、恒流、恒压的阶段式充电切换控制,并且恒流、恒压充电的精度可分别达到5%和1%以内.     

基于ToT的PET成像前端读出ASIC设计与实现

ToT(Time-over-Threshold)读出策略是在PET成像中利用信号的时间宽度同时获取能量和时间信息的方法。基于ToT的前端读出电路具有简单、高效、功耗低、面积小的优点。采用0.35 μm CMOS工艺,设计并实现了基于ToT的低噪声16通道PET成像前端读出ASIC芯片。为了实现低噪声,在电荷灵敏放大器中采用了输入管尺寸匹配技术,在成形器中采用了低噪声放大器。为了提高响应速度,在电压甄别器中采用了预放大和箝位推挽输出结构。芯片的测试结果表明,能量输入范围为3.5~56 fC,等效噪声电荷为211.4 e-+16.0 e-/pF,能量与输入电荷之间的非线性误差小于2%,单通道功耗为1.82 mW。与现有电路相比,该芯片的噪声降低了56.4%,在PET成像系统中具有广阔的应用前景。     

Design of a low-power CMOS transceiver for semi-passive wireless sensor network application

A 50 kbps/ISM band (902 − 926 MHz) low power transceiver for short-range wireless sensor networks (WSN) has been designed in 0.18 μm 1-poly-6 metal CMOS technology and occupy 950 μm × 800 μm. The proposed WSN transceiver designed based on an improved version of the Amplitude-Shift Keying communication scheme has a better continuous RF modulated carrier waveform as well as does not require complex modulator/demodulator circuits. In addition, to reduce power dissipation and increase power efficiency many circuit techniques have been adopted. The power dissipation and the power efficiency of the proposed WSN transceivers are 1.58 mW and 21%, respectively.     

Design and analysis of a flat gain and linear low noise amplifier using modified current reused structure with feedforward structure

In this paper, a Low Noise Amplifier (LNA) with the current reused topology is proposed for wideband applications. To increase input impedance matching common source with inductive degeneration and RC shunt feedback structure is used. To extend the bandwidth, inductive series peaking technique is utilized. In the next stage, two parallel structure is hired to have a high voltage gain with low power consumption in addition to improve linearity. Also, by using the self-forward-body-bias (SFBB) technique, supply voltage is reduced and as a result power consumption is decreased further. The proposed LNA exhibits the high and flat gain of 14.7–15.4 ​dB, input return loss of less than −11 ​dB and noise figure range of 2.3–4.4 ​dB from 1 ​GHz up to 8 ​GHz. It consumes 5.4 ​mW from a 1.2 ​V power supply. The achieved IIP3 range for the proposed LNA is 0 ​dBm up to +2.7 ​dBm. The proposed LNA occupies 0.45 ​mm² in 0.18-μm CMOS technology.     

A versatile signal flow graph realization of a general transfer function by using CDBA

A general synthesis procedure is given for a versatile signal flow graph realization of a general transfer function by using current differencing buffered amplifier (CDBA). The proposed configuration uses n+1 CDBAs, n capacitors and at most 2n+4 resistors. This number of resistors can be reduced to n+1 for special cases. The circuit is eligible to obtain a variety of transfer characteristics with the same common denominator polynomial, and it is easily converted to different modes of operations. It is straightforward to find the values of the passive elements from the coefficients of the transfer function to be realized. Simulations results are obtained by using commercially available active component AD844 and CMOS technology as well. All of these make the proposed circuit attractive.     

Implementation of a chaotic oscillator by designing Chua’s diode with CMOS CFOAs

The implementation of a chaotic oscillator which is based on Chua’s circuit, is presented. Chua’s diode is realized by using current feedback operational amplifiers (CFOAs). Furthermore, it is shown that a CMOS compatible CFOA can be designed by connecting two voltage followers sandwiched between two current mirrors. The proposed implementation is biased at ±1.2 V, and simulated by using SPICE and standard CMOS technology of 0.35 μm. Finally, simulation results are presented to show the sequence of chaotic behaviours for increasing values of the linear resistance. Esteban Tlelo-Cuautle received the B.Sc. degree in electronics engineering from the Technologic Institute of Puebla (ITP) México, in 1993, the M.Sc. and Ph.D. degrees from the National Institute for Astrophysics, Optics and Electronics (INAOE) México, in 1995 and 2000, respectively. In 1995 he joined the Department of Electronics at the ITP. Since 2001 he has been with the Department of Electronics at INAOE, where he is currently a Researcher. He has been member of reviewer-committees for the IEEE Trans. on CAS-I, IEEE Trans. on Education, IEEE Latin-America, Información Tecnológica, SCI Journal, IASTED, and IEEE ISCAS. He is member of IEICE, Senior Member of the IEEE, and his research interest include electronic design automation, modeling and simulation, symbolic analysis, circuit synthesis, and analog and mixed-signal CAD tools. Aarón Gaona-Hernández was born in Puebla, México in 1980. He received his B.Sc. degree from the Faculty of Sciences for Electronics at the Autonomous University of Puebla (BUAP-FCE), in 2005. His research interest include analog IC design and chaotic systems. Joel García-Delgado is with the BUAP-FCE México.     

Design of a PLL with improved locking range and its biomedical applications

This paper describes a phase locked loop employing a low voltage VCO using modified ECL inverter cells. The VCO circuit employed, features a positive feed back scheme to improve the operating frequency. The phase detector used in the PLL also uses a positive feedback scheme to improve the locked range and to reduce supply voltage of operation of the entire circuit. An improvement of locked range of around 35% was obtained from circuit simulation (using PSPICE) as well as from practical circuit, using discrete components. The minimum supply voltage required here is 2.5 volts. Some biomedical applications of this PLL are also proposed.