Electrical properties of high permittivity ZrO2 gate dielectrics on strained-Si

Deposition and electrical properties of high dielectric constant (high-k) ultrathin ZrO₂ films on tensilely strained silicon (strained-Si) substrate are reported. ZrO₂ thin films have been deposited using a microwave plasma enhanced chemical vapor deposition technique at a low temperature (150 °C). Metal insulator semiconductor (MIS) structures are used for high frequency capacitance–voltage (C–V), current–voltage (I–V), and conductance–voltage (G–V) characterization. Using MIS capacitor structures, the reliability and the leakage current characteristics have been studied both at room and high temperature. Schottky conduction mechanism is found to dominate the current conduction at a high temperature. Observed good electrical and reliability properties suggest the suitability of deposited ZrO₂ thin films as an alternative as gate dielectrics. Compatibility of ZrO₂ as a gate dielectric on strained-Si is shown.     

Effect of oxide resistance on the characterization of interface trap density in MOS structures

The oxide resistance in a practical MOS capacitor is generally not high enough to be negligible in the evaluation of interface trap density based on the qruasi-static capacitance-voltage (C–V) curve. The importance of the effects of oxide resistance ranging from 10¹³ to 10¹⁶ Ω on the C–V curve and the corresponding interface trap density is theoretically shown. To obtain the oxide resistance in MOS structures the newly reported charge-then-decay method is suggested. From the oxide resistance found, one can compare the distribution curves of interface trap density before and after removing the oxide resistance effect. It is found that the results obtained after removing the oxide resistance effect are more consistent than those without removing it. It addition, the removal of the oxide resistance effect for a sample having a hysteresis C–V behavior is also discussed.     

Sensing behavior and mechanism of titanium dioxide-based MOS hydrogen sensor

A Pd/TiO₂/Si MOS sensor (Pdtisin sensor) is proposed for the detection of hydrogen gas. The sensor is fabricated on a p-type 1 1 1 silicon wafer having resistivity of 3–6 Ω cm. The thickness of TiO₂ in this structure is about 600 nm. The capacitance–voltage (C–V) and conductance–voltage (G–V) characteristics of the device is observed on the exposure of hydrogen gas at room temperature. The mechanism of hydrogen sensing of titanium dioxide-based MOS sensor (MOS capacitor) has been investigated by evaluating the change in flat-band voltage (V_FB) and fixed surface state density of the device in presence of hydrogen gas. The device exhibits very large parallel shift in C–V as well in G–V characteristics. The possible mechanism on Pd/TiO₂ and TiO₂/Si surface in presence of hydrogen gas has been proposed. The response and recovery time of the device is also measured at room temperature.     

A novel linearly tunable butterfly-shape MEMS capacitor

A new MEMS tunable capacitor with linear capacitance–voltage (C–V) response is introduced. The design is developed based on a parallel-plate configuration and uses the structural lumped flexibility and geometry optimization to obtain a linear response. The moving electrode is divided into two segments connected to one another by a torsional spring. There are extra beams located between the two plates, which constrain the displacement of the moving plate. The resulting nonlinear structural rigidity provides the design with higher tunability than the parallel-plate ones. Furthermore, because the plate's displacement is controlled, the shape of C–V curve changes in such a way that high linearity is achieved. The proposed design can be fabricated by a three-structural-layer process such as PolyMUMPs. The results of analytical solution and experimental measurements verify that the new capacitor can produce tunability of over 100% with high linearity. The introduced design methodology can further be extended to flexible plates and beams to obtain smooth C–V curves.     

A complete analytical model of GaN MESFET for microwave frequency applications

A simple physics-based analytical model for a non-self-aligned GaN MESFET suitable for microwave frequency applications is presented. The model includes the effect of parasitic source/drain resistances and the gate length modulation. The model is then extended to evaluate I–V and C–V characteristics, transconductance, cut-off frequency, transit time, RC time constant, optimum noise figure and maximum power density. The transconductance of about 21 mS/mm is obtained for GaN MESFET using the present theory in comparison to 23 mS/mm of the reported data. The cut-off frequency of more than 1 GHz, optimum noise figure of 6 dB and maximum output power density of more than 1 W/mm are predicted.     

A circuit-compatible analytical device model for ballistic nanowire transistors

Silicon nanowire transistors (SNWTs) have attracted broad attention as a promising device structure for future integrated circuits. Silicon nanowires with a diameter as small as 2 nm and having high carrier mobility have been achieved. Consequently, to develop TCAD tools for SNWT design and to model SNWT for circuit-level simulations have become increasingly important. This paper presents a circuit-compatible closed-form analytical model for ballistic SNWTs. Both the current–voltage (I–V) and capacitance–voltage (C–V) characteristics are modeled in terms of device parameters and terminal voltages. Such a model can be efficiently used in a conventional circuit simulator like SPICE to facilitate transistor-level simulation of large-scale nanowire or mixed nanowire-CMOS circuits and systems.     

Noise studies in internal field emission diodes

The breakdown process of a zener diode in reverse direction is governed by internal field emission at low voltage and by impact ionization at higher voltage. For breakdown voltage in the transition range between 3 and 6 V, both physical processes appear in combination. Measuring the I–V characteristic and the noise current fluctuations spectral density it is possible to show the zener current multiplication by the multiplication effect described by Tager. In addition the I–V characteristic can be written empirically I = Vⁿ.     

Electrical properties of W/Si interfaces with embedded Ge/Si islands

In this work, we investigated electrical and morphological properties of W/p-type Si Schottky diodes with intentional inhomogeneities introduced by macroscopic Ge-islands embedded beneath the interface. The Si-cap layer thickness (or the island-distance to the interface) was progressively reduced by successive chemical etching cycles. Electrical characterizations were achieved through reverse current–voltage (I–V) at room temperature and forward I–V measurements as a function of the temperature. In parallel, Rutherford backscattering spectroscopy analyses were performed to follow the Si-cap/Ge islands chemical thinning down with increasing the number of etching cycles. In addition, the comparison of topographical and electrical properties of the etched silicon-cap layer was carried out by conductive atomic force microscopy analyses with a nanometer-scale resolution. Our results indicate that the areas on the top of islands exhibit lower resistance than those which covered the wetting layer. This lateral variation of resistance at the surface of the semiconductor may correspond to Schottky barrier height inhomogeneities observed on broad area I–V characteristics of Schottky contacts.     

Some pitfalls in fast ramp C-V measurements

The triangular voltage sweep or fast ramp C-V method, while leading to an easy measurement of deep depletion C-V curves, may have pitfalls for the unwary, particularly in the case of degraded oxides. Two examples of the difficulties associated with the measurement in the presence of positive oxide charge, viz., (i) a distorted fast ramp C-V curve at intermediate bias values and; (ii) a “peak” in the curve due to an inversion layer surrounding the device, are illustrated and explained.     

An analytical model for the power bipolar-MOS transistor

This paper presents an analytical model for the I–V characteristics of the bipolar-MOS power transistor, also known as IGT or COMFET. Good agreement between this model and experiments is found over a wide range of carrier lifetime and current density. The predicted trade-off between the forward voltage drop and device turn-off time (0.4–10 μsec) has been verified by experiment. For even shorter switching time, the model predicts only a moderate increase in V_F. Adding a more heavily doped buffer epitaxial layer is shown to only slightly increase V_F but offers several important benefits. The comparison between n-channel and p-channel devices is discussed using the model and the forward voltage drops for the two types of devices are shown to differ by only a small percentage in spite of the large difference in electron and hole mobilities.     

Breakdown degradation associated with elementary screw dislocations in 4H-SiC pn junction rectifiers

It is well-known that SiC wafer quality deficiencies are delaying the realization of outstandingly superior 4H-SiC power electronics. While efforts to date have centered on eradicating micropipes (i.e., hollow core super-screw dislocations with Burgers vector>2c), 4H-SiC wafers and epilayers also contain elementary screw dislocations (i.e., Burgers vector=1c with no hollow core) in densities on the order of thousands per cm², nearly 100-fold micropipe densities. This paper describes an initial study into the impact of elementary screw dislocations on the reverse-bias current–voltage (I–V) characteristics of 4H-SiC p⁺n diodes. First, synchrotron white beam X-ray topography (SWBXT) was employed to map the exact locations of elementary screw dislocations within small-area 4H-SiC p⁺n mesa diodes. Then the high-field reverse leakage and breakdown properties of these diodes were subsequently characterized on a probing station outfitted with a dark box and video camera. Most devices without screw dislocations exhibited excellent characteristics, with no detectable leakage current prior to breakdown, a sharp breakdown I–V knee, and no visible concentration of breakdown current. In contrast, devices that contained at least one elementary screw dislocation exhibited 5–35% reduction in breakdown voltage, a softer breakdown I–V knee, and visible microplasmas in which highly localized breakdown current was concentrated. The locations of observed breakdown microplasmas corresponded exactly to the locations of elementary screw dislocations identified by SWBXT mapping. While not as detrimental to SiC device performance as micropipes, the undesirable breakdown characteristics of elementary screw dislocations could nevertheless adversely affect the performance and reliability of 4H-SiC power devices.     

Novel structure of GaAs-based interdigital-gated HEMT plasma devices for solid-state THz wave amplifier

Theoretical analysis of potential distribution in the interdigital-gated high electron mobility transistor (HEMT) plasma wave device was carried out. The dc I–V characteristics of capacitively coupled interdigital structure showed that uniformity of electric field under the interdigital gates was improved compared to the dc-connected interdigital gate structure. Admittance measurements of capacitively coupled interdigital gate structure in the microwave region of 10–40 GHz showed the conductance modulation by drain–source voltage. These results indicate the existence of plasma wave interactions.     

New technique for measuring the threshold voltage in MOS devices

The present paper describes an experimental method that can be used to measure the threshold voltage in MOS devices in the form of transistors or capacitors. The proposed method is based on the detection of the non-steady-state/steady-state transition of the surface potential at the oxide–semiconductor interface of a MOS device, when it is swept from depletion to inversion regions. This detection is carried out as follows: a set of current versus gate signal frequency measurements, for different voltage amplitudes, is performed. The frequency values corresponding to the maximum measured current (optimum frequency) f_m, are read. Several gate voltage versus optimum frequencies (f_m–V_G) curves are plotted for gate voltage values ranging from 0.2 to 3 V with a 0.1 V step increment. The (f_m–V_G) curves are found to undergo an abrupt change of slope at a specific gate voltage value. The value of threshold voltage is extracted from the critical points of the former curves. Experiments have been carried out on different devices. The measured values of threshold voltage are found to be in good agreement to those obtained by the conventional I_D–V_GS and simulation methods as well as that supplied by the device manufacturer.     

High stability and low driving voltage green organic light emitting diode with molybdenum oxide as buffer layer

Green organic light emitting diodes (OLEDs) with copper phthalocyanine (CuPc), 4,4′,4″-tris[3-methylphenyl(phenyl)amino]triphenymine (m-MTDATA) and molybdenum oxide (MoO_x) as buffer layers have been investigated. The MoO_x based device shows superior performance with low driving voltage, high power efficiency and much longer lifetime than those with other buffer layers. At the luminance of 100 cd/m², the driving voltage is 3.8 V, which is 0.5 V and 2.2 V lower than that of the devices using CuPc (Cell-CuPc) and m-MTDATA (Cell-m-MTDATA) as buffer layer, respectively. Its power efficiency is 13.6 Lm/W, which is 38% and 30% higher than that of Cell-CuPc and Cell-m-MTDATA, respectively. The projected half-life under the initial luminance of 100 cd/m² is 42,400 h, which is more than 3.8 times longer than that of Cell-m-MTDATA and 24 times that of Cell-CuPc. The superior performance of Cell-MoO_x is attributed to its high hole injection ability and the stable interface between MoO_x and organic material. The work function of MoO_x measured by contact potential difference method and the J–V curves of “hole-only” devices indicate that a small barrier between MoO_x/N,N′-di(naphthalene-1-y1)-N,N′-dipheyl-benzidine (NPB) leads to a strong hole injection, resulting in the low driving voltage and the high stability.     

Effect of Channel Width Shortening on the Stability of a-Si:H/nc-Si:H Bilayer Thin-Film Transistors

The static bias-stress-induced degradation of hydrogenated amorphous/nanocrystalline silicon bilayer bottom-gate thin-film transistors is investigated by monitoring the turn-on voltage (V _on) and on-state current (I _on) in the linear region of operation. Devices of constant channel length 10 mum and channel width varying from 3 to 400 mum are compared. The experimental results demonstrate that the device degradation is channel-width dependent. In wide channel devices, substantial degradation of V _on is observed, attributed to electron injection into the gate dielectric, followed by I _on reduction due to carrier scattering by the stress-induced gate insulator trapped charge. With shrinking the channel width down to 3 mum, the device stability is substantially improved due to the possible reduction of the electron thermal velocity during stress or due to the gate insulator quality uniformity over small dimensions.     

Experimental studies of switching in metal semi-insulating n-p silicon devices

The switching properties of silicon structures comprising a p⁺-n junction and a metal electrode separated from the n-section of the p⁺-n junction by a semi-insulating (leaky) layer are presented. Two basic types of structure were studied: devices with relatively light doped n-sections, and those with relatively heavily doped sections.

The switching voltage of the first group was found to be proportional to the product of the doping density, N_d and the square of the width of the n-section, and to be only very weakly temperature-dependent. The capacitance-voltage relationship of the device in the high-impedance mode was found to be of the form C⁻¹ ∞ V^1/2, and these measurements established that switching occurred just as the depletion region of the n-section under the gate electrode reached through to the p⁺-n junction. It was thus established that these devices were operating in the punch-through mode.

In the second group of devices, the doping density of the n-section was increased by diffusing an n-well into the section. The switching properties were found to be quite different from the punch-through devices. The switching voltage was found to be independent of the width of the n-section and proportional to N_d^−3/4. Capacitance measurements also showed that the depletion region in the n-section under the oxide at switching, varied with the doping concentration, and was substantially less than the width of the n-layer. It was thus concluded that switching in these devices was of the avalanche-mode type.     

High Transconductance MISFET With a Single InAs Nanowire Channel

Metal-insulator field-effect transistors (FETs) are fabricated using a single n-InAs nanowire (NW) with a diameter of d = 50 nm as a channel and a silicon nitride gate dielectric. The gate length and dielectric scaling behavior is experimentally studied by means of dc output- and transfer-characteristics and is modeled using the long-channel MOSFET equations. The device properties are studied for an insulating layer thickness of 20-90 nm, while the gate length is varied from 1 to 5 mum. The InAs NW FETs exhibit an excellent saturation behavior and best breakdown voltage values of V _BR > 3 V. The channel current divided by diameter d of an NW reaches 3 A/mm. A maximum normalized transconductance g_m /d > 2 S/mm at room temperature is routinely measured for devices with a gate length of les 2 mum and a gate dielectric layer thickness of les 30 nm.     

Design optimization of stacked layer dielectrics for minimum gate leakage currents

An effective model to evaluate the leakage currents for different stacked gates deep submicron MOS transistors is presented. For a given equivalent oxide thickness of a stacked gate, the gate leakage current decreases with an increase of high-k dielectric thickness or a decrease of interlayer thickness. Turning points at high gate biases of the I–V curves are observed for Si₃N₄/SiO₂, Ta₂O₅/SiO₂, Ta₂O₅/SiO_2−yN_y, Ta₂O₅/Si₃N₄, and TiO₂/SiO₂ stacked gates except for Al₂O₃/SiO₂ structure. Design optimization for the stacked gate architecture to obtain the minimum gate leakage current is evaluated.     

Interface characteristics of Ge3N4-(n-type) GaAs MIS devices

Passivation of GaAs surfaces was achieved by the deposition of Ge₃N₄ dielectric films at low temperatures. Electrical characteristics of MIS devices were measured to determine the interface parameters. From C-V-f and G-V-f measurements, density of interface states has been obtained as (4–6)×10¹¹ cm⁻² eV⁻¹ at the semiconductor mid-gap. Some inversion charge buildup was seen in the C-V plot although the strong inversion regime is absent. Thermally stimulated current measurements indicate a trap density of 5×10¹⁸−10¹⁹ cm⁻³ in the dielectric film, with their energy level at 0.59 eV.     

Temperature-dependence of steady-state characteristics of SCR-type ESD protection circuits

Experimental analysis of the temperature-dependent I–V characteristics of various SCR (Silicon-Controlled Rectifier) electrostatic discharges (ESD) protection circuits have been carried out. These circuits include diode-chain-triggering SCR (DCTSCR), low-voltage zener diode trigger SCR (ZDSCR), low-voltage trigger SCR (LVTSCR) and gate-coupled low-voltage trigger SCR (GCSCR) circuits. The ZDSCR uses the zener breakdown mechanism of a reverse-biased p⁺–n⁺ diode as a trigger mechanism, the DCTSCR uses the current flowing through forward-biased diode chain as a trigger mechanism, the LVTSCR uses the grounded-gate MOSFET breakdown current as the trigger mechanism and the steady-state I–V characteristics of GCSCR also uses the avalanche breakdown as a triggering mechanism. The trigger voltage can decrease or increase with increasing temperature depending upon the triggering mechanism used in the circuit, however the holding voltages of these SCRs decrease with increasing temperature.