Algorithm and Implementation of Parallel Multiplication in a Mixed Number System

This paper presents a high-speed multiplication algorithm for the mixed number system of the ordinarybinary number and the symmetric redundant binary number.It is implemented with the multivalned logictheory,and 3-valued and 2-valued circuits are used.The 3-valued circuit proposed in this paper is anemitter-coupled logic circuit with high speed,simplicity and powerful functions.A 3-valued ECL thresholdgate can simultaneously produce six types of one-variable operations.The array multiplier,designed withthe algorithm and the circuits,is fast and simple,and is suitable for building LSI.It can be used in a high-speed computer just as an ordinary binary multiplier.     

Low power DCVSL circuits employing AC power supply

In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design, which adopts a gradually changing power clock. First, we discuss the algebraic expressions and the corresponding properties of clocked power signals. Then the design procedure is summed up for converting complementary CMOS logic gates employing DC power to the power-clocked CMOS gates employing AC power. On this basis, the design of differential cas-code voltage switch logic (DCVSL) circuits employing AC power clocks is proposed. The PSPICE simulations using a sinusoidal power-clock demonstrate that the designed power-clocked DCVSL circuit has a correct logic function and low power characteristics. Finally, an interface circuit to convert clocked signals into the standard logic levels of a CMOS circuit is proposed, and its validity is verified by computer simulations.     

Emitter-coupled spin-transistor logic

The recent invention of magnetoresistive bipolar spin-transistors makes possible the creation of new spintronic logic families. Here we propose the first logic family exploiting these devices, extending emitter-coupled logic (ECL) to achieve a greater range of basis logic functions. By placing the wire from the output stage of ECL logic elements near spin-transistors in other logic stages throughout the circuit, additional basis logic elements can be realized. These new logic elements support greater logic minimization, resulting in enhanced speed, area, and power characteristics. A novel magnetic shielding structure provides this logic family with the crucial ability to cascade logic stages. This logic family potentially achieves a power-delay product 10–25 times smaller than conventional ECL, and can therefore be exploited to increase the performance of very high-speed logic circuits while broadening the range of design choices for a variety of electronic applications.     

Dual threshold voltage and sleep switch dual threshold voltage DOIND approach for leakage reduction in domino logic circuits

Subthreshold leakage current becomes the major component of total power dissipation as scaling down the feature size. In this paper, two new circuit techniques are proposed for reducing the subthreshold leakage power consumption in domino logic circuit. Dual threshold voltage DOIND (Domino logic with clock and input dependent transistors) and NMOS sleep switch dual threshold voltage DOIND circuits for low leakage domino logic circuits are presented. High threshold voltage transistors are utilized to reduce the leakage current and a sleep transistor is added to the dynamic node that strongly turnoff all the high threshold voltage transistor and significantly reduce the subthreshold leakage power. The proposed circuit techniques, dual threshold voltage DOIND logic and sleep switch dual threshold voltage DOIND logic reduces the leakage current by 71.46 and 74.86% respectively as compared to standard domino logic circuit. Simulation results also shows that both the circuits are less affected by supply and temperature variations. The proposed sleep switch dual threshold voltage DOIND exhibits 19.95% less power consumption with 24% die area overhead for the buffer circuit as compared to standard domino logic circuit. The proposed sleep switch dual threshold voltage DOIND logic has improved normalized figure of merit of 1.17 as compared to standard domino logic circuit.

     

组合逻辑电路的软错误率自动分析平台

为在设计阶段快速评估集成电路的软错误率,以指导高可靠集成电路的设计,提出一种适用于组合逻辑电路和时序逻辑电路组合逻辑部分的快速软错误率自动分析平台HSECT-ANLY.采用精确的屏蔽概率计算模型来分析软错误脉冲在电路中的传播;用向量传播和状态概率传播的方法来克服重汇聚路径的影响,以提高分析速度;使用LL(k)语法分析技术自动解析Verilog网表,使分析过程自动化,且使得本平台可分析时序电路的组合逻辑部分.开发工作针对综合后Verilog网表和通用的标准单元库完成,使得HSECT-ANLY的实用性更强.对ISCAS'85和ISCAS'89 Benchmark电路进行分析实验的结果表明:文中方法取得了与同类文献相似的结果,且速度更快,适用电路类型更多,可自动分析电路的软错误率并指导高可靠集成电路的设计.     

随机信号环形高速采集电路

为了对随机到来的信号进行不丢失的高速采集,提出了一种基于CPLD的随机信号环形高速采集卡的设计与实现;通过采用三套采集电路形成一个环形结构,可以对随机到来的信号进行不遗漏的高速采集,而且在采集过程中利用阈值的方法鉴别出有用信号,并舍弃了大量的冗余无用数据,从而只将有用数据以DMA的方式传于主机,便于进行信号的处理;电路设计简洁可靠,并给出了主要的逻辑电路示意图与主要部件说明;该系统已经应用在采集α核素的工程实践中.     

可编程可逆计数器电路的逻辑设计与功能验证

计数器电路在集成电路领域有着很广泛的应用,常作为集成电路的基本器件使用。计数器电路可以输出多种可控的信号,配合其它电路一起使用。以一种八位可编程可逆计数器为例,阐述了这类计数器电路具体的电路逻辑设计,及形成电路逻辑后的功能验证。     

Design Technique of I~2L Circuits Based on Multi-Valued Logic

This paper proposes the use of the current signal to express logic values and establishes th theory of grounded current switches suitable for I^2L circuits.Based on the advantag that current signals are easy to be added,the design technique of I^2L circuits by means of the multi-valued current signal is proposed.It is shown that simpler structure of I^2L circuits can be obtained with this technique.     

Design of low power multi-ternary digit multiplier in CNTFET technology

This work introduces the method to implement energy efficient designs of arithmetic units such as a ternary full adder, ripple carry adder, single-trit multiplier and multi-trit multiplier using carbon nanotube field effect transistors (CNTFETs). A CNTFET unique feature of the threshold voltage variation by changing the CNT diameter, make it a suitable alternative for being employed in ternary logic designs. In designing the proposed circuits, decoder circuit functionality is realized by various threshold detector circuits tuned to a specific logical threshold voltage value. The multiplier circuit is designed by combing the capacitive logic and the minority function. In order to test the practicability of proposed circuits in cascaded circuits, multi-digit adder and multiplier circuits are constructed. The proposed multi-digit multiplier structure is based on classical Wallace multiplier and includes various optimized versions of adder and multiplier circuits. Extensive simulation has been done to examine the competency of proposed designs under different test conditions. The design of 3-trit multiplier formed by combing the proposed adder and multiplier circuits shows 16 times reduction in power consumption as well as energy consumption in comparison to previous multiplier design.     

Symbolic pattern manipulation of Karnaugh-Veitch maps for pneumatic circuits

Pneumatics continue to play a vital role in low-cost automation. The designing of pneumatic control circuits has to date been a slow manual process. This paper describes the computational symbolic manipulation of the Karnaugh-Veitch (KV) map which is the heart of the prototype expert system called PNEUMAES. The symbolic manipulation of a KV map is governed by two sets of generic rules for signal flow plotting and for logic equation minimisation applicable for complex pneumatic circuits. As the complexity of the circuit increases, the symbolic manipulation of a KV map leads to the combinatorial explosion problem. Because of this problem, PNEUMAES can only automatically generate pure pneumatic circuit design equations which will yield minimised circuit configuration for up to four cylinders with auxiliary control valves. A case study is included and issues and problems relating to the implementation of the KV map are discussed. Symbolic and sub-symbolic learning approaches are suggested as a means by which the search space of the symbolic patterns of the KV map can be pruned.     

A three-step decomposition method for the evolutionary design of sequential logic circuits

Evolvable hardware (EHW) refers to an automatic circuit design approach, which employs evolutionary algorithms (EAs) to generate the configurations of the programmable devices. The scalability is one of the main obstacles preventing EHW from being applied to real-world applications. Several techniques have been proposed to overcome the scalability problem. One of them is to decompose the whole circuit into several small evolvable sub-circuits. However, current techniques for scalability are mainly used to evolve combinational logic circuits. In this paper, in order to decompose a sequential logic circuit, the state decomposition, output decomposition and input decomposition are united as a three-step decomposition method (3SD). A novel extrinsic EHW system, namely 3SD–ES, which combines the 3SD method with the (μ, λ) ES (evolution strategy), is proposed, and is used for the evolutionary designing of larger sequential logic circuits. The proposed extrinsic EHW system is tested extensively on sequential logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library. The results demonstrate that 3SD–ES has much better performance in terms of scalability. It enables the evolutionary designing of larger sequential circuits than have ever been evolved before.     

A Fully-Automated Electron Beam Test System for VLSI Circuits

A fully automated, stroboscopic electrobeam test system that analyzes the behavior of logic VLSI circuits, this system consists of a stroboscopic electron-beam tester combined with an LSI CAD system. LSI circuit design data, read from the CAD system, provides a designed map. The host computer performs interconnection pattern recognition by superimposing this map onto an observed stroboscopic SEM image. Then, once the circuit nodes for voltage waveform measurements are automatically determined on the superimposed map. Next, the electron beam is positioned on the actual circuit-under-test wires. These automatic processes result in measured waveforms, which are displayed on the host computer terminal. This system has been applied to a 2.3K-gate logic LSI circuits, and has been successful in locating the critical path. This system, coupled with the recently developed fault diagnostic electron-beam tester, Finder, constitutes a unified electron-beam test system.     

Physical synthesis of quantum circuits using templates

Similar to traditional CMOS circuits, quantum circuit design flow is divided into two main processes: logic synthesis and physical design. Addressing the limitations imposed on optimization of the quantum circuit metrics because of no information sharing between logic synthesis and physical design processes, the concept of “physical synthesis” was introduced for quantum circuit flow, and a few techniques were proposed for it. Following that concept, in this paper a new approach for physical synthesis inspired by template matching idea in quantum logic synthesis is proposed to improve the latency of quantum circuits. Experiments show that by using template matching as a physical synthesis approach, the latency of quantum circuits can be improved by more than 23.55 % on average.     

Demand-driven logic simulation using a network of loosely coupled processors

Logic simulation is used extensively in the design of digital systems for the purpose of studying the behaviour of circuits under various conditions and for verifying the required performance of circuits. There is considerable interest in methods which reduce the simulation time during the design process. In this paper, we investigate how this can be achieved by simulating the action of logic circuits using a network of loosely coupled processors. Circuits modelled as directed graphs comprising clocked sequential components and (unclocked) arbitrary combinational logic gates can be partitioned into separate tasks each consisting of a sequential component with an associated network of combinational components. We present cost functions for evaluating a task subject to probabilistic assumptions about the functioning of the circuits. The circuit evaluation method used in the simulation process is significant. We apply lazy evaluation, a demand-driven evaluation strategy in which signals in the circuit are evaluated on a ‘need to do' basis, resulting in a considerable saving in circuit simulation time. We achieve distributed logic simulation using a network of workstations and show from experimental results that by using such a configuration, we essentially obtain a single computation engine which can be used to obtain speedups in circuit simulation when compared with uniprocessor simulation systems. Interprocess communications between tasks on different workstations proceed via remote procedure calls while local communications between tasks take place via shared memory. The method of partitioning used in the circuit model ensures that communications between tasks take place only at defined times in the simulation sequence.     

一种宽带高性能TIADC时钟发生器

针对并行交替模拟数字转换器(TIADC)发展遇到的时钟瓶颈,提出了一种宽带高性能TIADC时钟发生器设计方案.该方案利用时钟分路器和可编程延迟器分别实现通道扩展和相位延迟,采用可配置时钟源和逻辑转换电路使时钟发生器能够输出低抖动的CMOS和ECL逻辑TIADC时钟.设计实现的时钟发生嚣已经成功用于4通道12 bit 320 MHz采样率的TIADC系统.测试结果表明,该时钟发生器具有10 ps延迟偏差和在80MHz频率下不超过2 ps的时钟抖动.     

Generalized disjunction decomposition for evolvable hardware.

Evolvable hardware (EHW) refers to self-reconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the "generalized disjunction decomposition" (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the (1 + lambda) evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided.     

LORES-2: A Logic Reorganization System

LORES-2 is a logic reorganization system which greatly contributes to the effective automation of logic design. LORES-2 uses a macro-expansion technique to help designers transform printed-circuit assembly logic composed of SSI and MSI circuits into master-slice LSI logic circuits. The number of gates of the most reorganized LSI circuit falls within ± 20 percent of the number of gates of the original circuit. When ROMS and/or PLAs are not-allowed on the target LSI circuit, those elements are converted into optimized, multilevel random logic using logic minimization, factoring and macro-expansion techniques.     

Designing CMOS Circuits for Switch-Level Testability

Conventional testing techniques often fail to be effective for CMOS combinational circuits, since most of their switch-level faults cannot be detected by stuck-at-fault testing. The alternative is to design for testability. The design techniques presented here for fully testable CMOS combinational circuits use a three-pattern test scheme to detect both stuck-open and stuck-on switch-level faults. The circuit is implemented with specially designed gates that have no undetectable stuck-on faults. An inverting buffer is inserted between logic gates, and two FETs are added to each logic gate to make it testable for stuck-on faults.