Various effects of silicidation on shallow p+ junctionsformed by BF2+ implantation into thin poly-Sifilms on Si substrates

Various effects of silicidation on shallow p⁺ n junctions formed by the scheme that implants BF₂⁺ ions into thin poly-Si films on Si substrates are described. A post-Ni silicidation just slightly improves the preformed junctions of the annealed sample. However, as the sample is first deposited with thin Ni films after the implantation and then annealed, the resulting junctions are much better than the preformed ones. Moreover, as the sample is deposited with Ti films, the resultant junctions are just slightly better the preformed ones     

A novel process to form cobalt silicided p+ poly-Sigates by BF2+ implantation into bilayeredCoSi/a-Si films and subsequent anneal

A novel process that implants BF₂⁺ ions into thin bilayered CoSi/a-Si films has been shown to form cobalt silicided p ⁺ poly-Si gates with excellent gate oxide integrity and very small flatband shift. The effects of not only using the CoSi layer as an implantation barrier but also keeping the a-Si underlayer during the initial silicide formation both significantly suppress the boron penetration through thin gate oxide     

Rapid thermal annealing effects on Si p+-n junctionsfabricated by low-energy FIB Ga+ implantation

Effects of rapid thermal annealing (RTA) on sub-100 nm p⁺ -n Si junctions fabricated using 10 kV FIB Ga⁺ implantation at doses ranging from 10¹³ to 10¹⁵ cm ^-2 are reported. Annealing temperature and time were varied from 550 to 700°C and 30 to 120 s. It was observed that a maximum in the active carrier concentration is achieved at the critical annealing temperature of 600°C. Temperatures above and below the critical temperature were followed by a decrease in the active concentration, leading to a `reverse' annealing effect     

Characterization of ultra-shallow p+-n junction diodesfabricated by 500-eV boron-ion implantation

Ultrashallow gated diodes have been fabricated using 500-eV boron-ion implantation into both Ge-preamorphized and crystalline silicon substrates. Junction depths following rapid thermal annealing (RTA) for 10 s at either 950°C or 1050°C were determined to be 60 and 80 nm, respectively. These are reportedly the shallowest junctions formed via ion implantation. Consideration of several parameters, e.g. reduced B⁺ channeling, increased activation, and reduced junction leakage current, lead to the selection of 15 keV as the optimal Ge preamorphization energy. Transmission electron microscope results indicated that an 850°C/10-s RTA was sufficient to remove the majority of bulk defects resulting from the Ge implant. Resulting reverse leakage currents were as low as 1 nA/cm² for the 60-nm junctions and diode ideality factors for crystalline and preamorphized substrates ranged from 1.02 to 1.12. Even at RTA temperatures as low as 850°C, the leakage current was only 11 nA/cm ². The final junction depths were found to be approximately the same for both preamorphized and nonpreamorphized samples after annealing at 950°C and 1050°C. However, the preamorphized sample exhibited significantly improved dopant activation     

The effect of Co incorporation on electrical characteristics of n+/p shallow junction formed by dopant implantation into CoSi2 and anneal

The impact of Co incorporation on the electrical characteristics has been investigated in n⁺/p junction formed by dopant implantation into CoSi₂ and drive-in anneal. The junctions were formed by As⁺ (30 or 40 keV, 1×10¹⁶ cm ^-2) implantation into 35 nm-thick CoSi₂ followed by drive-in annealing at 900°C for 30 s in an N₂ ambient. Deeper junction implanted by As⁺ at 40 keV was not influenced by the Co incorporation. However, for shallower junction implanted by As ⁺ at 30 keV, incorporation of Co atoms increased its leakage current, which were supposed to be dissociated from the CoSi₂ layer by silicide agglomeration during annealing. The mechanism of such a high leakage current was found to be Poole-Frenkel barrier lowering induced by high density of Co traps     

p+-n junction formed by dual implantation of Zn and As in GaAs junction field-effect transistors

The performance of a p+-n junction formed in GaAs by dual implantation of Zn and As was investigated. The transconductance in linear operation of the junction field-effect transistors (JFET's) in which the p+-gate was formed by the dual implantation was measured and analyzed on a simple one-dimensional model. As the dose of As was increased, the devices showed negatively shifted pinchoff voltage and higher transconductance. It was found that the co-implantation of As significantly decreased the width of the compensated layer in the junction, which improved the JFET's performance.     

Enhancement of oxide break-up by implantation of fluorine inpoly-Si emitter contacted p+-n shallow junctionformation

In this study, it is demonstrated that the incorporation of fluorine can enhance poly-Si/Si interfacial oxide break-up in the poly-Si emitter contacted p⁺-n shallow junction formation. The annealing temperature for breaking up the poly-Si/Si interfacial oxide has been found to be as low as 900°C. As a result, the junction depth of the BF₂-implanted device is much larger than that of the boron-implanted device     

0.2-μm p+-n junction characteristics dependent onimplantation and annealing processes

Junction depth, sheet resistance, dopant activation, and diode leakage current characteristics were measured to find out the optimal processing conditions for the formation of 0.2-μm p⁺-n junctions. Among the 2×10¹⁵ cm^-2 BF₂ implanted crystalline, As or Ge preamorphized silicon, the crystalline and Ge preamorphized samples exhibit excellent characteristics. The thermal cycle of furnace anneal (FA) followed by rapid thermal anneal (RTA) shows better characteristics than furnace anneal, rapid thermal anneal, or rapid thermal anneal prior to furnace anneal     

Low-temperature growth of silicon-boron layer as solid diffusionsource for polysilicon contacted p+-n shallow junction

A new material, Si-B, is proposed as a solid diffusion source for fabrication of poly-Si contacted p⁺-n shallow junctions. The junction depth of the Si-B source diode has been measured and compared with that of a BF₂⁺-implanted poly-Si source diode. It was found that the Si-B source diode had a much shallower junction and was less sensitive to thermal budget than the BF₂⁺ source diode. This was attributed to the smaller surface concentration and diffusivity of boron in the silicon in Si-B source diodes. Regarding electrical characteristics of diodes with a junction depth over 500 Å, a forward ideality factor of better than 1.01 over 8 decades and a reverse-current density lower than 0.5 nA/cm² at -5 V were obtained. As the junction depth shrank to 300 Å, the ideality factor and reverse current density of diodes increased slightly to 1.05 and 1.16 nA/cm², respectively. These results demonstrated that a uniform ultrashallow p⁺-n junction can be obtained by using a thin Si-B layer as a diffusion source     

Formation of shallow p+-n junctions using boron-nitride solid diffusion source

Shallow p⁺-n junctions on the order of 0.1-µm deep have been fabricated using boron-nitride (BN) solid diffusion sources. The process combines the hydrogen-injection method and rapid thermal processing (RTP). Sheet resistivities, in ranges from 50 to 130 Ω/sq with junction depths from 0.1 to 0.19 µm, are possible in this technique. Diode characteristics of 0.11-µm junctions show low reverse leakage current, of the order of 10 nA/cm², indicating the possibility of this method to form PMOS source-drain contacts.     

Low-temperature fabrication of p+-n diodes with300-Å junction depth

Gas immersion laser doping (GILD) was used to fabricate p⁺ -n diodes with 300-Å junction depth. These diodes exhibit ideality factors of 1.01-1.05 over seven decades of current, reverse leakage current densities ⩽10 nA/cm² at -5-V reverse bias, breakdown voltages above 100 V, and electrical activation of the boron impurity to concentrations approaching 1×10²¹ atoms/cm³. This behavior is achieved without the use of a furnace or rapid thermal anneal     

Electrical properties of Ga-implanted Si p+-n shallowjunctions fabricated by low-temperature rapid thermal annealing

p⁺-n shallow-junction diodes were fabricated using on-axis Ga⁶⁹ implantation into crystalline and preamorphized Si, at energies of 25-75 keV for a dose of 1×10¹⁵/cm ², which is in excess of the dosage (2×10¹⁴/cm²) required to render the implanted layer amorphous. Rapid thermal annealing at 550-600°C for 30 s resulted in the solid-phase epitaxial (SPE) regrowth of the implanted region accompanied by high Ga activation and shallow junction (60-130 nm) formation. Good diode electrical characteristics for the Ga implantation into crystalline Si were obtained; leakage current density of 1-1.5 nA/cm² and ideality factor of 1.01-1.03. Ga implantation into preamorphized Si resulted in a two to three times decrease in sheet resistance, but a leakage current density orders of magnitude higher     

Electrical properties of Si p+-n junctions for sub-0.25μm CMOS fabricated by Ga FIB implantation

p⁺-n junction diodes for sub-0.25-μm CMOS circuits were fabricated using focused ion beam (FIB) Ga implantation into n-Si (100) substrates with background doping of N_b=(5-10)×10 ¹⁵ and N_b⁺=(1-10)×10¹⁷ cm^-3. Implant energy was varied from 2 to 50 keV at doses ranging from 1×10¹³ to 1×10¹⁵ cm^-2 with different scan speeds. Rapid thermal annealing (RTA) was performed at either 600 °C or 700°C for 30 s. Diodes fabricated on N_b⁺ with 10-keV Ga⁺ exhibited a leakage current (^I_R) 100× smaller than those fabricated with 50-keV Ga⁺. Tunneling was determined to be the major current transport mechanism for the diodes fabricated on N_b⁺ substrates. An optimal condition for I_R on N_b⁺ substrates was obtained at 15 keV/1×10¹⁵ cm^-2. Diodes annealed at 600°C were found to have an I_R 1000× smaller than those annealed at 700°C. I-V characteristics of diodes fabricated on N_b substrates with low-energy Ga⁺ showed no implant energy dependence. I-V characteristics were also measured as a function of temperature from 25 to 200°C. For diodes implanted with 15-keV Ga ⁺, the cross-over temperatures between I_diff and I_g-r occurred at 106°C for N_b ⁺ and at 91°C for N_b substrates     

Reduction of p+-n+ junction tunneling currentfor base current improvement in Si/SiGe/Si heterojunction bipolartransistors

The authors report a three-order-of-magnitude reduction in parasitic tunneling current at heavily doped p⁺-n⁺ Si/Si and SiGe/Si junctions grown by rapid thermal epitaxial chemical vapor deposition (CVD) compared with previously reported results in Si junctions fabricated by ion implantation. These results demonstrate the high quality of the epitaxial interface. The low tunneling currents allow higher limits to transistor base and emitter doping levels, yielding higher gains, reduced bias resistances, and higher Early voltages for scaled bipolar devices as well as Si/SiGe/Si heterojunction bipolar transistors     

The recrystalization of BF2+-implanted silicon by light-flash annealing

SEM, TEM and optical metallography have been applied to investigate the microstructural changes of the BF₂⁺-implanted silicon annealed by the intense irradiation of a flash tube. Slip traces and electron diffraction patterns as revealed on the annealed wafers clearly indicate epitaxial regrowth from liquid to solid phase after flash annealing with energy density higher than 20 J/cm². A strong-diffusion model has been used to solve the one-dimensional heat conduction of the flash irradiation on the semiconductor. The calculated threshold energy for the temperature of the surface to reach the melting point agrees well with experimental values.     

Suppression of boron penetration in p+ polysilicon gateP-MOSFETs using low-temperature gate-oxide N2O anneal

It has been reported that high-temperature (~1100°C) N₂ O-annealed oxide can block boron penetration from poly-Si gates to the silicon substrate. However, this high-temperature step may be inappropriate for the low thermal budgets required of deep-submicron ULSI MOSFETs. Low-temperature (900~950°C) N₂O-annealed gate oxide is also a good barrier to boron penetration. For the first time, the change in channel doping profile due to compensation of arsenic and boron ionized impurities was resolved using MOS C-V measurement techniques. It was found that the higher the nitrogen concentration incorporated at Si/SiO₂ interface, the more effective is the suppression of boron penetration. The experimental results also suggest that, for 60~110 Å gate oxides, a certain amount of nitrogen (~2.2%) incorporated near the Si/SiO₂ interface is essential to effectively prevent boron diffusing into the underlying silicon substrate     

Modeling boron diffusion in thin-oxide p+ Si gatetechnology

A network defect model suitable for use in process simulation is presented for the diffusion of B in SiO₂ and, in particular, B in the presence of F and H₂. We find that B diffuses via a peroxy linkage defect the concentration in the oxide of which changes under different processing conditions. From random walk theory it is possible then to calculate the resulting diffusion coefficients. These results are compared with measured diffusivities and empirical adjustments are made     

Anomalous reverse short-channel effect in p+ polysilicongated P-channel MOSFET

The boron-penetration-dependent Reverse Short Channel Effect (RSCE) on the threshold voltage is observed for short channel p⁺ poly-gate PMOSFET's. The RSCE is found to be more significant as the boron penetration becomes more severe. The RSCE is significant in BF ₂ doped poly-gated MOS devices and is alleviated in buffered poly-gated MOS devices. Fluorine enhanced boron diffusion in the gate oxide during high temperature process is believed to account for the RSCE, which is also confirmed by using a two-dimensional process simulator     

H2+和D2+谐波强度与波长的关系

为了了解H₂+及其同位素分子谐波光谱效率与激光波长之间的关系,采用求解2维薛定谔方程的方法,理论研究了600nm~1600nm激光波长下H₂+和D₂+谐波光谱强度随波长的变化关系。结果表明,光谱强度随波长增大而减小;在短波长区间,H₂+光谱强度减小的倍率要大于D₂+,在长波长区间,H₂+光谱强度减小的倍率要小于D₂+;此外,在弱光强下,H₂+光谱强度总是大于D₂+, 在强光强下,H₂+光谱强度在短波长区间小于D₂+, 而其在长波长区间大于D₂+; 核间距延伸和电荷共振增强电离在H₂+和D₂+谐波光谱强度变化上起到主要作用。这一结果对分子谐波调控是有帮助的。     

Effect of the annealing conditions on the electrical characteristics of p+/n shallow junctions

Shallow p+/n junctions are produced by low-energy (10-keV) boron implantation into amorphous silicon layers formed by a prior implantation of Si+ ions. Junctions about 0.1 µm deep with good electrical characteristics (reverse current density Jr< 10^-7A/cm²at - 1 V) are obtained both by electron-beam annealing (1100°C, 2 s) and conventional furnace annealing (800°C, 30 min). It is shown that, in the case of the furnace treatment, lower annealing temperatures produce very high reverse currents, while excellent electrical characteristics (Jr< 10^-8A/cm²) are achieved at higher annealing temperatures (900°C), the junction extending, however, much deeper into silicon (0.26 µm).