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1.
Use of the linearising current-mode cell (LCMC) concept is presented to design highly linear differential pair transconductors compatible with standard CMOS technology. The linearity an input voltage range of the proposed circuits are significantly improved over those of the conventional source-coupled differential pair biased by a current sink. The SPICE simulation results show that, for a power supply of +or-5 V, the linearity error is less than 0.2 Omega over +or-4 V differential input range.<> 相似文献
2.
《Solid-State Circuits, IEEE Journal of》1985,20(6):1158-1168
A novel technique is presented for performing the analog multiplication in CMOS technology. The circuit handles a wide range of input voltages. The MSO version of Gilbert's six-transistor cell (GSTC) is the basis for this multiplier. A simple source-coupled pair is used to study the MOS GSTC. Then, a technique is introduced for linearizing the source-coupled circuit. This scheme is extended to the MOS GSTC. The voltage ranges are further increased by introducing the folded CMOS GSTC. 相似文献
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Aimad El Mourabit Mohamed-halim Sbaa Guo-Neng Lu Patrick Pittet 《Analog Integrated Circuits and Signal Processing》2010,62(3):415-422
This paper presents a method to extend linear range of conventional CMOS source-coupled pair with transistor polarised on
saturation of strong inversion. The used principle is similar to the principle of source degeneration, but the additional
device is horizontally added, in parallel with the input transistors, which overcame the constraints on common mode range
and supply voltage and allow low voltage operation. SPICE simulations using 0.35 μm CMOS process and a bias current of 10 μA,
show that for less than 1% of transconductance variation, the linear range is up to 0.35 V
pp in comparison to 0.1 V
pp for source-degenerated pair, and 0.01 V
pp for conventional differential pair, under the same biasing current and geometrical dimensions. 相似文献
6.
This paper presents a modified design method for linear transconductor circuit in 130 nm CMOS technology to improve linearity,
robustness against process induced threshold voltage variability and reduce harmonic distortion. Source follower in the adaptively
biased differential pair (ABDP) linear transconductor circuit is replaced with flipped voltage follower to improve the efficiency
of the tail current source, which is connected to a conventional differential pair. The simulation results show the performance
of the modified circuit also has better speed, noise performance and common mode rejection ratio compared to the ABDP circuit. 相似文献
7.
This paper presents an analog predistortion circuit for RF optical fiber links. The circuit consists of two source-coupled differential transconductance amplifiers which could provide linear and nonlinear transfer charac-teristics by adjusting the bias voltage and the transistor sizes. The circuit was designed and realized in a standard 0.18-μm CMOS technology of SMIC. The chip occupies 0.48 × 0.24 mm~2. The DC supply is 3.3 V. Using this circuit, the third-order intermodulation distortion (IMD) suppression of a directly modulated RF optical fiber link can be improved by 9-16 dBc at relatively low cost. 相似文献
8.
In this paper a novel low-voltage ultra-low-power differential voltage current conveyor (DVCC) based on folded cascode operational transconductance amplifier OTA with only one differential pairs floating-gate MOS transistor (FG-MOST) is presented. The main features of the proposed conveyor are: design simplicity; rail-to-rail input voltage swing capability at a low supply voltage of ±0.5 V; and ultra-low-power consumption of mere 10 μW. Thanks to these features, the proposed circuit could be successfully employed in a wide range of low-voltage ultra-low-power analog signal processing applications. Implementation of new multifunction frequency filter based on the proposed FG-DVCC is presented in this paper to take the advantages of the properties of the proposed circuit. PSpice simulation results using 0.18 μm CMOS technology are included as well to validate the functionality of the proposed circuit. 相似文献
9.
针对低电源电压Gm-C复数滤波器线性度不足的问题,提出了一种使用大信号线性化技术的一阶复数带通滤波器。所提出的复数滤波器使用了不平衡差分对和自适应偏置电路两种线性化技术,通过扩展跨导相对恒定的输入电压范围提高滤波器的线性度。滤波器采用UMC 110 nm CMOS工艺设计,中心频率和带宽分别为2 MHz和1 MHz。Cadence仿真结果显示,在1.2 V电源电压下,滤波器功耗为229μW,镜像抑制比(IIR)为18 dB,线性度(输入三阶交调点IIP3)为9.53 dBm,总谐波失真(THD)为-55.7 dB。该复数滤波器电路结构简单、功耗较低,以期能广泛应用于低电源电压的接收机设计。 相似文献
10.
Galan J. Carvajal R.G. Torralba A. Munoz F. Ramirez-Angulo J. 《IEEE transactions on circuits and systems. I, Regular papers》2005,52(2):283-291
A new operational transconductance amplifier and capacitor based sinusoidal voltage controlled oscillator is presented. The transconductor uses two cross-coupled class-AB pseudo-differential pairs biased by a flipped voltage follower, and it exhibits a wide transconductance range with low power consumption and high linearity. The oscillator has been fabricated in a standard 0.8-/spl mu/m CMOS process. Experimental results show a frequency tuning range from 1 to 25 MHz. The amplitude is controlled by the transconductor nonlinear characteristic. The circuit is operated at 2-V supply voltage with only 1.58 mW of maximum quiescent power consumption. 相似文献
11.
Sougata Kumar Kar Siddhartha Sen 《Analog Integrated Circuits and Signal Processing》2012,72(1):163-171
The present article describes the design and analysis of an operational transconductance amplifier (voltage to current converter) with wide linear input range. The proposed configuration combines the techniques of signal attenuation and source degeneration in order to reduce the odd order harmonic distortion significantly. The proposed circuit is compared with several circuit topologies based on MOS differential pairs with respect to their achievable linearity, input referred noise and power consumption. The linear transconductor is designed and simulated in 180?nm CMOS process technology with 1.8?V power supply. Simulation results show third order harmonic distortion (HD 3) of ?70?dB for 600?mVpp input signal. For 1% transconductance variation the linear range is about 1.2?Vpp. The input referred noise of the transconductor is $70\,\hbox{nV}/\sqrt{\text {Hz}}$ at 10?MHz. The quiescent power consumption is only 450???W. 相似文献
12.
Zanming Xia Chunhua Wang Jun Kuang Jie Jin 《International Journal of Electronics》2016,103(4):704-721
In this article, we propose a novel high-performance complementary metal oxide semiconductor (CMOS) current differencing transconductance amplifier (CDTA) with a transconductance gain (GM) that can be linearly tuned by a voltage. By using a high-speed, low-voltage, cascaded current mirror active resistance compensation technique, the proposed CDTA circuit exhibits wide frequency bandwidths, high current tracking precisions as well as large output impedances. The linear-tunable GM of the CDTA is designed with the use of linear composite metal oxide semiconductor field-effect transistor as basic cells in the circuit. Combining these two approaches, several design concerns are studied, including: impedance characteristic, tracking errors, offset and linearity and noise. The prototype chip with a 0.25 mm2 area is fabricated in a GlobalFoundries’0.18 μm CMOS process. The simulated results and measured results with ±0.8 V DC supply voltages are presented, and show extremely wide bandwidths and wide linear tuning range. In addition, a fully differential band-pass filter for a high-speed system is also given as an example to confirm the high performance of the proposed circuit. 相似文献
13.
A 2-V 10.7-MHz CMOS limiting amplifier/RSSI 总被引:2,自引:0,他引:2
Po-Chiun Huang Yi-Huei Chen Chorng-Kuang Wang 《Solid-State Circuits, IEEE Journal of》2000,35(10):1474-1480
This paper presents low-voltage low-power CMOS circuit design techniques for an intermediate frequency (IF) limiting amplifier and received signal strength indicator (RSSI). The architecture of the limiting amplifier and RSSI employed is determined by the optimal power consumption for a specified speed, overall gain, and accuracy. Each gain cell of the limiting amplifier employs folded diode load for low-voltage operation. Offset is reduced by a cross-connected source-coupled pair offset subtractor that is along the signal path. Full-wave current rectification and summation are employed in the RSSI circuit to achieve high precision while maintaining low voltage and low power. Using a single 2-V supply voltage, measured results demonstrate the input dynamic range is larger than 75 dB for 10.7-MHz IF application. The prototype occupies an active area of 0.4 mm2 using a 0.6-μm digital CMOS technology. The power dissipation is 6.2 mW 相似文献
14.
Calvo B. Celma S. Sanz M.T. Alegre J.P. Aznar F. 《IEEE transactions on circuits and systems. I, Regular papers》2008,55(3):715-721
This paper presents a new low-voltage pseudodifferential continuous-time CMOS transconductor for wide-band applications. The proposed cell is based on a feedforward cancellation of the input common-mode signal and keeps the input common mode voltage constant, while the transconductance is easily tunable through a continuous bias voltage. Linearity is preserved during the tuning process for a moderate range of transconductance values. Measurements results for a 0.35-m CMOS design show a 1:2 tuning range with total harmonic distortion figures at 10 MHz below 58 dB over the whole range up to a 200- differential output current. The proposed cell consumes less than 1.1 mW from a single 1.8-V supply. 相似文献
15.
Veeravalli A. Sanchez-Sinencio E. Silva-Martinez J. 《Solid-State Circuits, IEEE Journal of》2002,37(6):776-781
A pseudodifferential CMOS operational transconductance amplifier (OTA) with wide tuning range and large input voltage swing has been designed for very small GM's (of the order of a few nanoamperes per volt). The OTA is based on a modified four-quadrant multiplier architecture with current division. A common-mode feedback circuit structure has been proposed and designed using floating-gate transistors to handle large differential signals. Large on-chip capacitors are emulated through impedance scaling circuits. The circuits, fabricated in a 1.2-μm CMOS process, have been used to design a fourth-order bandpass filter and a relaxation oscillator. Experimental results are in good agreement with the theoretical results 相似文献
16.
Suzuki T. Takahashi T. Hirose T. Takikawa M. 《Solid-State Circuits, IEEE Journal of》2004,39(10):1706-1711
80-Gbit/s operation of a static D-type flip-flop (D-FF) circuit was achieved using InP-based HEMT technology, which has a cut-off frequency of 245 GHz and a transconductance of 1500 mS/mm. The circuit was designed with differential operation based on source-coupled FET logic (SCFL). To overcome deterioration of the 80-GHz clock signals in a single-ended to differential signal converter in the input buffer, a rat-race circuit was used as a converter. Measurements showed that the circuit achieved a gain of over 2 dB higher than a conventional converter using a differential pair circuit, and power consumption was reduced from 380 to 260 mW. The power supply voltage was -5.7 V, and total power consumption was 1.2 W. Since there is no commercially available 80-Gbit/s-pulse pattern generator, we developed a selector module to measure the D-FF. These measurements showed that the D-FF successfully operated at 80 Gbit/s, which is almost twice the speed reported to date. 相似文献
17.
新型差动输入CMOS电流传送器及其应用 总被引:1,自引:0,他引:1
基于P阱CMOS工艺提出了一种新的差动输入电流传送器。通过引入误差抑制负反馈电路,有效地减小了信号失真,拓宽了电路线性动态范围。文中还详细分析了电路性能,并由此指导电路的优化。给出的几个典型应用电路表明,与第二代电流传送器(CCII)相比,差动输入电流传送器的通用性更强,可获得较简洁的电路结构。本文最后设计了一个既可作为电流模式又可作为电压模式的MOSFET-C二阶滤波器。PSPICE模拟表明所提出的电路与其它同类电路相比具有更好的电路特性。 相似文献
18.
Yichuang Sun Chris Hill Stanislaw Szczepanski 《Analog Integrated Circuits and Signal Processing》2003,34(3):247-255
A large dynamic range high frequency fully differential CMOS transconductance amplifier is introduced. It is based on the linear transconductance element proposed in [8] combined with the common-mode feedback circuit in [9]. The original transconductance and common-mode circuits which use two supply voltages are modified for operation under a single power supply. The performance of the complete transconductance amplifier is analysed in details. Simulation results of the whole circuit are also presented, which show that with a single 5 V supply, bandwidth in excess of 300 MHz, THD below 0.7% for a 1 V
pk–pk
differential input signal, and dynamic range in excess of 70 dB can be achieved for the fully differential transconductance amplifier. 相似文献
19.
This paper presents a transconductor suitable for implementation in submicron CMOS technology. The transconductor is nearly insensitive for the second-order effects of the MOS transistors, which become more and more prevalent in today's submicron processes. The transconductor relies on a differential pair with variable degeneration resistance, while the degeneration resistors are “soft-switched” by means of MOS transistors. The transconductance is continuously tunable. A transconductor, using a device in which the degeneration resistors and “soft switches” are merged, is optimized for a maximum tuning range and can be used in variable gain stages like in an automatic gain control (AGC) circuit. Besides, a third-order 5.5 MHz low-pass filter has been realized in a 0.5-μm CMOS process using the “soft-switched” transconductor. At a 3.3 V supply voltage the filter dissipates 12 mW and the dynamic range equals 62 dB where the total harmonic distortion (THD) is -48 dB for an input voltage of 1 Vpp 相似文献