Gate voltage and oxide thickness dependence of progressive wear-out of ultra-thin gate oxides

The progressive wear-out of a breakdown path in ultra-thin gate oxides depends on oxide thickness and follows the intrinsic voltage acceleration model of time to breakdown. The quantification of progressive wear-out in this work is the critical step towards product relevant assessment of ultra-thin gate oxides.     

Gate oxide thickness dependence of high-field-induced interface state generation in thin thermal oxides

The oxide thickness dependence of the high-field-induced interface state generation Delta D/sub it/ in the nanometre-range thin (6-10 nm) gate oxides prepared by rapid thermal oxidation have been studied. It is shown that Delta D/sub it/ is a strong function of the oxide thickness. The thickness dependence of Delta D/sub it/ is found to be a function of stress time. Physical mechanisms are discussed to account for the experimental results.<>     

Gate oxide integrity of MOS/SOS devices

Time-dependent dielectric breakdown and ramp-voltage oxide breakdown measurements were used to evaluate the oxide integrity of MOS/SOS devices fabricated by a 3-µm process with a 500-Åthick gate oxide and dry-etched silicon islands. Field and temperature acceleration factors were determined on device arrays which ranged from 1 to 1000 devices. The measured temperature and field acceleration factors are used to give reasonable stress conditions for elimination of defective multiple device arrays without significantly altering the wear out time for nondefective arrays. Extrapolation of the data is used to suggest stress conditions and predict wear out time for 4K RAM's.     

Gate oxide integrity on ITOX-SIMOX substrates and influence of testdevice geometry on characterization

The integrity of gate oxides on low-dose separation by implanted oxygen (SIMOX) substrates fabricated by the internal-thermal-oxidation (ITOX) process, so-called ITOX-SIMOX substrates, was evaluated, and the influence of test device geometry on the characterization was investigated. Characterization of time-dependent dielectric breakdown (TDDB) was performed for a gate oxide of 8.6-nm thick using lateral test devices. Experimental results show considerable influence of gate electrode geometry on the gate oxide integrity (GOI) characteristics. This can be explained by a model that includes a lateral parasitic resistance in the superficial Si layer beneath the gate electrode. Based on analysis using this model, a test device with a small gate array was proposed to reduce the influence of lateral parasitic resistance, and the advantage of the device was verified     

Effect of substrate thickness and metallization thickness on dispersion characteristics of CPW

Approximate conformal mapping techniques have been used for analysing the effect of finite substrate thickness on coplanar wave guide (CPW). Calculations for impedance and effective dielectric constant are presented for CPW's with finite substrate thicknesses. Analytical formulation are presented for calculations. Network analytical methods of electromagnetic fields are employed to evaluate the effect of thick metal coating on CPW. Dispersion characteristics of CPW have been plotted for various metallization thicknesses. Effect of thick metal coating on guide wavelength is also plotted. Increase in metallization thickness of CPW causes an increase in wavelength. Due to this fact characteristic impedance and effective dielectric constant decreases.     

Current-voltage characteristics of Al/SiO2/p-Si MOS tunnel diodes with a spatially nonuniform oxide thickness

The effect of nonuniform distribution of the insulator thickness on the behavior of Al/SiO₂/p-Si MOS tunnel structures with a (1–4)-nm-thick insulator is studied. The character and magnitude of the effect depend on the applied bias. In any conditions, the nonuniformity of the SiO₂ thickness enhances the total through currents as compared to those flowing across a uniform oxide layer of the same nominal thickness. Further, the potential of the inversion layer changes in the inversion mode. The calculations performed take into account the tunnel transport between the Si conduction band and the metal, that between the Si valence band and the metal (including in the inversion mode, the resonant transport, which is less clearly pronounced because of the thickness nonuniformity), and the band-to-band tunneling in the semiconductor.     

Gate oxide thickness dependence of edge charge trapping in NMOS transistors caused by charge injection under constant-current stress

This brief reports a study of charge injection-induced edge charge trapping in the gate oxide overlapping the drain extension which has an impact on the drain leakage current. The edge charge trapping is determined for the gate oxide thickness of 6.5, 3.9, and 2.0 nm by using a simple approach to analyze the change of the band-to-band tunneling current measured with a three-terminal gate-controlled-diode configuration. The edge charge trapping has a strong dependence on the gate oxide thickness, and it is different from the charge trapping in the oxide over the channel. A plausible explanation for both the oxide thickness dependence of the edge charge trapping and the difference between the edge charge trapping and the charge trapping over the channel is presented.     

Effect of post oxidation annealing on electrical characteristics of Ni/SiO2/4H-SiC capacitor with varying oxide thickness

This paper describes an experimental observation of post oxidation annealing (POA) treatment on current-voltage and capacitance-voltage characteristics of Ni/SiO₂/4H-SiC system with varying oxide thickness. The leakage current of fabricated structures shows an asymmetric behavior having noticeable effect of POA with the polarity of gate bias (+V or −V at the anode). When compared with the conventional wet oxidation, the POA processes greatly reduce interface-state density and enhance reliability of devices. An extensive increment in the barrier height at SiO₂/4H-SiC interface was observed due to POA, which resulted into lower forward leakage current. A significant improvement in the oxide charges are also demonstrated using C-V characteristics of POA treated structures.     

Influence of substrate conductivity on characteristics of ZnO/SiO2-diaphragm piezoelectric resonators

Most of the ZnO/SiO2-diaphragm piezoelectric composite resonators on silicon substrates exhibit Q-factors of the anti-resonance much lower than those of the resonance. It is demonstrated both theoretically and experimentally that this is caused by the conductivity of the substrate.     

Weibull breakdown characteristics and oxide thickness uniformity

In this work, we investigated both experimentally and numerically the impact of macroscopic oxide thickness uniformity on Weibull breakdown characteristics for both Weibull parameters, namely, the characteristic times and Weibull slopes over a wide range of oxide thicknesses. We report the abnormal characteristics of the Weibull time-to-breakdown distributions and non-Poisson area scaling behavior observed on ultrathin oxides. Two numerical methods using the parameters obtained from two independent sets of experimental results are developed to quantitatively explain these effects in the context of current modulation due to oxide thickness variation. The relationship between time-to-breakdown and charge-to-breakdown distributions has been clarified and established. It is found that without proper treatment of these effects, the use of Weibull slopes at higher failure percentiles can lead to erroneous and pessimistic reliability projection. Furthermore, me perform a detailed full-scale Monte Carlo analysis to evaluate the impact of thickness variation on low-percentile breakdown distributions and their sensitivity to the thickness dependence of the times-to-breakdown and Weibull slopes.     

Oxide thickness dependence of nitridation effects on TDDB characteristics

Wet oxide thicknesses dependence of nitridation effects on electrical characteristics, charge trapping properties and TDDB (Time Dependent Dielectric Breakdown) characteristics have been investigated. It is found that the difference of conduction current between the wet and nitrided wet oxide increases with increasing oxide thickness both for negative and positive bias to the gate until constant current stress is applied. After the stress, with decreasing oxide thickness both in wet and nitrided wet oxide leakage current increases. Up to 60 Å no difference was observed between the wet and nitrided wet oxide but at 50 Å nitrided wet oxide has less increase of current comparing to the wet oxide for the same stress. In wet oxide with increasing stress current density initial hole trap decreases but electron trap increases whereas in nitrided wet oxide has less initial hole trap and also electron trap is less comparing to the wet oxide. Both in wet and nitrided wet oxide for negative bias stress, time to 50 % breakdown decreases with decreasing thickness but at 50 Å a turn-around effect was observed due to nitridation i.e., the 50 % breakdown time is greater for nitrided wet oxide comparing to the wet oxide. On the contrary, for positive bias stress 50 % breakdown time increases with decreasing oxide thickness both in wet and nitrided wet oxide. For positive bias also a turn-around effect is observed at 50 Å i.e., 50% breakdown time is less in nitrided wet oxide comparing to the wet oxide. The improved reliability of nitrided wet oxide at the thin region of 50 Å seems to be due to the increase of more Si---N bond to the interface of oxide and Si comparing to the thick oxide of above 60 Å for the same nitridation conditions.     

Threshold voltage dependence of LOCOS-isolated thin-film SOINMOSFET on buried oxide thickness

Effects of buried oxide thickness on short-channel effect of LOCOS-isolated thin-film SOI n-MOSFETs have been investigated. Devices fabricated on SOI substrate with thin (100 nm) buried oxide have smaller roll-off of threshold voltage than those fabricated on SOI substrate with thick (400 nm) buried oxide. This is caused by a different boron concentration at the silicon film that results from the difference of stress with the buried oxide thickness. In the case of thin buried oxide, higher volumetric expansion of the field oxide causes higher stress at the interface between the silicon film and the surrounding oxide, including field and buried oxide, which prevents boron atoms from diffusing beyond the interface     

Gate bias dependence of the substrate signal coupling effect in RF MOSFETs

Analytical expressions for the Y-parameters of RF MOSFETs including the substrate signal coupling effect were systematically derived. The expressions are physically correct and simple enough to be intuitive. With the expressions, how signal coupling occurs through the substrate network of parasitics could be clearly explained in physical terms, for the first time. In particular, we focused on how substrate signal coupling makes an influence on the output admittance of an RF MOSFET as the gate bias varies. The developed theory was verified with S-parameter measurement results.     

Modeling oxide thickness dependence of charging damage by plasmaprocessing

Develops a quantitative model for thin oxide plasma charging damage by examining the oxide thickness dependence of charging current. The current is deduced from capacitance-voltage (CV) curves of metal-oxide-semiconductor (MOS) capacitors after plasma etch. The model predicts the oxide thickness dependence of plasma charging successfully. It is shown that plasma acting on a very thin oxide during processing may be modeled as essentially a current source. Thus the damage will not be greatly exacerbated as oxide thickness is further reduced in the future. Gate oxide breakdown voltage distribution of MOS capacitors after plasma processing can be predicted accurately from that of a control wafer by using a defect-induced breakdown model     

Gate oxide integrity of thermal oxide grown on high temperatureformed Si0.3Ge0.7

We have investigated the gate oxide integrity of thermal oxides direct grown on high temperature formed Si_0.3Ge_0.7. Good oxide integrity is evidenced by the low interface-trap density of 5.9×10¹⁰ eV^-1 cm^-2, low oxide charge density of -5.6×10¹⁰ cm^-2, and the small stress-induced leakage current after -3.3 V stress for 10 000 s. The good gate oxide integrity is due to the high temperature formed and strain-relaxed Si_0.3Ge_0.7 that has a original smooth surface and stable after subsequent high temperature process     

Novel Multistate Quantum Dot Gate FETs Using SiO2 and Lattice-Matched ZnS-ZnMgS-ZnS as Gate Insulators

Multistate behavior has been achieved in quantum dot gate field-effect transistor (QDGFET) configurations using either SiO _x -cladded Si or GeO _x -cladded Ge quantum dots (QDs) with asymmetric dot sizes. An alternative method is to use both SiO _x -cladded Si and GeO _x -cladded Ge QDs in QDGFETs. In this paper, we present experimental verification of four-state behavior observed in a QDGFET with cladded Si and Ge dots site-specifically self-assembled in the gate region over a thin SiO₂ tunnel layer on a Si substrate. This paper also investigates the use of lattice-matched high-κ ZnS-ZnMgS-ZnS layers as a gate insulator in mixed-dot Si QDGFETs. Quantum-mechanical simulation of the transfer characteristic (I _D–V _G) shows four-state behavior with two intermediate states between the conventional ON and OFF states.     

A practical model for growth kinetics of thermal SiO2 on silicon applicable to a wide range of oxide thickness

A simple and practical model which simulates the thermal growth of SiO₂ on silicon is presented. Dry O₂ oxidation is modeled assuming existence of a constant Si-SiO₂ interface potential with an accompanying field retarding the transport of charged oxidants in the oxide near the interface. It is shown that HCl oxidation also can be simulated in the framework of this model. Further, the model is extended to treat the pyrogenic H₂O oxidation in which both oxygen and water contribute as oxidants. The present model can be used to simulate the oxide growth kinetics for the above three types of oxidation, in a wide range of oxide thickness including very thin oxides below several hundred of Å the region which is important in the fabrication of MOS VLSI's.     

The impact of scaling-down oxide thickness on poly-Si thin-filmtransistors' I-V characteristics

The key factors reducing the fluctuations of poly-Si I-V fluctuations are investigated. Besides the trapping states at the grain boundary, the oxide thickness plays an important role in poly-Si characteristics. Scaling down the oxide thickness will improve both poly-Si performance and I-V uniformity     

Determination of tunnel mass and physical thickness of gate oxide including poly-Si/SiO/sub 2/ and Si/SiO/sub 2/ interfacial transition Layers

By including poly-Si/SiO/sub 2/ and Si/SiO/sub 2/ interfacial transition (IFT) layers, an excellent agreement in terms of both C-V and J-V characteristics is obtained between the experiment and theory for both polarities of gate voltage (V/sub G/) for the first time. The highly precise physical models for gate depletion and gate accumulation bring an oxide thickness extracted from the C-V fitting in a negative V/sub G/ close to that extracted in a positive V/sub G/. It is shown that the physical oxide thickness should be regarded as a distance between the middle points inside the IFT layers in both sides of the gate oxide. In addition, it is found that the tunnel mass is independent of the gate-oxide thickness from 14 to 28 /spl Aring/. It is also shown that the oxide-thickness dependence of the tunnel mass , is ascribable to the C-V-J-V fitting only in the case of a negative polarity of V/sub G/ while neglecting the poly-Si/SiO/sub 2/ IFT layer.     

N and P metal oxide semiconductor field effect transistor characteristics of hafnium-doped SiO2 gate dielectrics

This work presents the interfacial properties of hafnium-doped SiO₂ films via N and P metal oxide semiconductor (MOS) materials, MOS-capacitor, and N and P metal oxide semiconductor field effect transistor (MOSFET) characterization. The results indicate that HfSi_xO_y films (a) have excellent transistor characteristics; (b) remain amorphous through high-temperature processing; (c) are compatible with N+ and P+ polysilicon electrodes; (d) have lower gate leakage than SiO₂ of the same equivalent oxide thickness (EOT); and (e) have a dielectric constant of ∼8. Therefore, the hafnium-doped SiO₂ films are at-tractive as a dielectric material and offer a technologically relevant gate-stack node for insertion, prior to deployment of high-K dielectrics.