A quad CMOS single-supply op amp with rail-to-rail output swing

The realization of a commercially viable, general-purpose quad CMOS amplifier is presented, along with discussions of the tradeoffs involved in such a design. The amplifier features an output swing that extends to either supply rail, together with an input common-mode range that includes ground. The device is especially well suited for single-supply operation and is fully specified for operation from 5 to 15 V over a temperature range of -55 to +125/spl deg/C. In the areas of input offset voltage, offset voltage drift, input noise voltage, voltage gain, and load driving capability, this implementation offers performance that equals or exceeds that of popular general-purpose quads or bipolar of Bi-FET construction. On a 5-V supply the typical V/SUB os/ is 1 Mv, V/SUB os/ drift is 1.3 /spl mu/V//spl deg/C, 1-kHz noise is 36 nV//spl radic/Hz, and gain is one million into a 600-/spl Omega/ load. This device achieves its performance through circuit design and layout techniques as opposed to special analog CMOS processing, thus lending itself to use on system chips built with digital CMOS technology.     

A low-noise high-precision operational amplifier

A low-noise high-precision operational amplifier has recently been fabricated in monolithic form with dielectric isolation. The amplifier exhibits a V/SUB OS/ of 10 /spl mu/V, V/SUB OS/T/SUB c/ of 0.3 /spl mu/V//spl deg/C, voltage gain of 140 dB with a 600 /spl Omega/ load, and an input noise voltage of 9 nV//spl radic/Hz. The settling time to within 0.01 percent of final value is 15 /spl mu/s for a 10 V pulse.     

Amplifier techniques for combining low noise, precision, and high-speed performance

A monolithic operational amplifier is presented which optimizes voltage noise both in the audio frequency band, and in the low frequency instrumentation range. In addition, the design demonstrates that the requirements for low noise do not necessitate compromising the specifications in other respects. Techniques are set forth for combining low noise with high-speed and precision performance for the first time in a monolithic amplifier. Achieved results are: 3 nV//spl radic/Hz white noise, 80 nV/SUB p-p/ noise from 0.1 to 10 Hz, 17 V//spl mu/s slew rate, 63 MHz gain-bandwidth product, 10 /spl mu/V offset voltage, 0.2 /spl mu/V//spl deg/C drift with temperature, 0.2 /spl mu/V/month drift with time, and a voltage gain of two million.     

Design analysis of a gain-stabilized transistor amplifier at elevated temperatures using passive elements

The decrease of the emitter-base and collector-base junction voltages of a transistor with temperature and the effect of the external circuit resistances on these voltages are studied theoretically and experimentally. The influence of the shifting of the operating point with temperature on the gain is discussed. A new design approach based on V/SUB EB/ and V/SUB CB/ as the stability parameters is given using only passive components. It is found that this approach definitely leads to better gain stability with temperature than other design techniques using NTC elements. Although work in the early stages was concentrated on germanium transistors (-15 to +115/spl deg/C), already some encouraging results have also been attained in the study of silicon transistors.     

A low-voltage micropower JFET/bipolar operational amplifier

A single cell supply (operable down to 1.2 V) micropower operational amplifier using compatible low pinchoff voltage JFET's (V/SUB p/=0.4 V) in conjunction with standard bipolar technology has been developed. The subvolt pinchoff JFET's have proved useful in the common-mode feedback-assisted biasing of a simple p-n-p input stage to permit single supply operation, the design of a low-voltage high-performance current mirror and a differential to single-ended converter. The amplifier exhibits excellent ac performance (unity gain slew rate=0.25 V//spl mu/s, unity gain bandwidth=850 kHz) with low power dissipation (245 /spl mu/W).     

An integrated IF amplifier

An IF amplifier that provides a temperature insensitive Q (adjustable independently of center frequency) of 50 at a center frequency of f/SUB 0/ of 1 MHz, over a 100/spl deg/C temperature range is presented. The design also features supply independent biasing, input and output buffering, a 40-dB (automatic gain control) range and a center frequency voltage gain of up to 60 dB. Results obtained from computer simulations, discrete, and integrated prototypes are compared.     

Comments on `Silicon MESFET digital circuit techniques'

See also ibid., vol.SC-16, p.578-84 (Oct. 1981). It is shown that the design criterion for MESFET ED logic assumed by Hartgring et al.-that the low voltage level must be less than /SUP 1///SUB 3/ V/SUB T/-is overly restrictive, and that the technology is more tolerant of V/SUB T/ variation than would be surmised from such an assumption. Data for the operation of a MESFET ED logic divide-by-four circuit over a temperature range from 25/spl deg/C to 145/spl deg/C confirms the wider operating margin of this technology.     

A high precision component-tolerant A/D convertor

A pulse transformer is used to double and sum voltages in an A/D encoder that is based on the recursive algorithm V/SUB i+1/=V/SUB REF/-s|V/SUB i/|. As a result of isolating the transformer from the input signal d.c. component, independence of circuit zero drift is achieved. Resistor and V/SUB BE/ mismatch do not affect the encoder accuracy. Automatic zero and gain correction are employed to provide stable adjustment-free operation. A custom analog processor chip carrying both MOS and bipolar transistors was fabricated to implement the algorithm. The 12-bit resolution with a maximum encoder error of 250 /spl mu/V in a temperature range from 0-70/spl deg/C was achieved at 20-kHz sampling rate.     

Measurement of the temperature dependence of the I/SUB C/(V/SUB be/) characteristics of integrated bipolar transistors

The temperature dependence of the I/SUB C/(V/SUB be/) relationship of bipolar transistors can be characterized by two parameters /spl eta/ and V/SUB go/. The authors discuss a new method for the determination of these parameters. With this method there is no need for accurate temperature measurements. It is shown that the results fit very well with bandgap-reference temperature characteristics. An analytical method for the calculation of V/SUB g0/ and /spl eta/ from values of the base emitter voltage or the bandgap reference voltage at different temperatures is presented.     

CMOS integrated silicon pressure sensor

The sensor described includes a four-arm piezoresistance bridge circuit, an amplifier, and a bridge excitation circuit. This circuit is used to stabilize changes in sensitivity due to variations in temperature and supply voltage. The sensor was fabricated using a self-aligned double-poly Si gate p-well CMOS process combined with an electrochemical etch-stop technique using N/SUB 2/H/SUB 4/-H/SUB 2/O anisotropic etchant for the thin-square diaphragm formation. The silicon wafer was electrostatically adhered to a glass plate to minimize thermally induced stress. Less than a /spl plusmn/0.5% sensitivity shift and less than a /spl plusmn/5-mV offset shift were obtained in the 0-70/spl deg/C range, with a 1-V/kg/cm/SUP 2/ pressure sensitivity. By using a novel excitation technique, a sensitivity change of less than /spl plusmn/1.5% under a /spl plusmn/10% supply voltage variation was also achieved.     

A high precision monolithic super-beta operational amplifier

A single-chip (67/spl times/90 mil) integrated-circuit operational amplifier using thin-film resistors and super-gain transistors has been designed to achieve dc follower accuracies of 0.001 percent with 100-k/spl Omega/ source resistance. The circuit achieves gains of 140 dB using thermally balanced layout designs for both input and output stages, nulled drifts of 0.3 /spl mu/V//spl deg/C, and offset currents well under 1 nA. All other dc specifications including power-supply variation error (PSRR), common-mode gain error (CMRR), etc., are in the 1-10 ppm error range; and a procedure is given by which long-term drifts of less than 10 /spl mu/V/month can be assured. AC performance is comparable to general-purpose integrated-circuit operational amplifiers, i.e., f/SUB t/=300 kHz and slew rate of 1.2 V//spl mu/s at gain of ten. The circuit is externally compensated for unity gain with a single 390-pF capacitor and is fully input and output protected.     

A monolithic 14-bit D/A converter

A monolithic 14-bit D/A converter using `dynamic element matching' to obtain a high accuracy and good long-term stability is described. Over a temperature range from -50/spl deg/ to 70/spl deg/C the nonlinearity is less than one-half least significant bit (/SUP 1///SUB 2/LSB). Dynamic tests show a distortion at a level of about -90 dB with respect to the maximum sinewave output. Nearly no glitches are found, so the converter can be operated without a deglitcher circuit. The chip, with a size of 3.1/spl times/3.2 mm, contains all elements needed, except the output amplifier and digital input latches.     

Low voltage techniques [for micropower operational amplifiers]

A micropower operational amplifier is described that will operate from a total supply voltage of 1.1 V. The complementary class-B output can swing within 10 mV of the supplies or deliver /spl plusmn/20 mA with 0.4 V saturation. Common mode range includes V/SUP -/, facilitating single-supply operation. Otherwise, DC performance compares favourably with that of the LM108. An adjustable-output voltage reference is also presented that uses a new technique to eliminate the bow usually found in the temperature characteristics of the band-gap reference. Minimum supply is 1 V, and typical drift is 0.002 percent//spl deg/C.     

High-Gain 15-W Monolithic Power Amplifier with Internal Fault Protection

A combination of circuit and device innovations has resulted in the development of a 15-W integrated-circuit power amplifier that incorporates a preamplifier on the same chip to give an overall closed-loop gain of 60 dB. Two novel devices used are a new high-frequency drift-lateral p-n-p to improve stability and a new 3-A n-p-n power transistor design with individual emitter ballasting to achieve a larger safe-operating area. Other interesting features are an externally adjustable short-circuit current limit, a built-in thermal shutdown circuit that automatically limits the junction temperature to 175/spl deg/C, an electronic shutdown control to mute the amplifier; a supply voltage range of 10-40 V, excellent power-supply rejection (55 dB), and a unique biasing technique that ensures that the output quiescent point remains at one-half the supply voltage with the total bias current changing only 3 mA over the complete supply voltage range (10-40 V).     

A vertical channel JFET fabricated using silicon planar technology

A vertical channel JFET with a new structure was fabricated using a self-aligned process and doped polysilicon technology. This structure is suitable for a high power device, since many channels are easily integrated on a single chip. It is also suitable for a high frequency device, because two essential conditions for high frequency operation, sufficiently low gate resistance and small channel length, can be realized without difficulty. This device shows triode-like I-V characteristics, which are determined by the channel impurity concentration and gate diffusion profile. Typical performances of an n-channel, 4 mm/spl times/4 mm, 5520 channel power FET, designed for an audio amplifier, are a voltage amplification factor of 5, a source-to-gate breakdown voltage of 60 V, a drain-to-gate breakdown voltage of 200 V, and I/SUB DSS/=4 A at V/SUB DS/=7 V.     

Properties of Be-implanted planar GaAs p-n junctions

The fabrication and characteristics of planar junctions in GaAs formed by Be ion implantation are discussed. The critical processing step is shown to be the use of a carefully deposited oxygen-free Si/SUB 3/N/SUB 4/ encapsulation during post-implantation annealing. Forward and reverse characteristics are presented for Be-implanted junctions formed by encapsulating with SiO/SUB 2/, Si/SUB x/O/SUB y/N/SUB z/, or Si/SUB 3/N/SUB 4/ layers prior to annealing at 900/spl deg/C. Junctions which exhibit leakage current density of ~2/spl times/10/SUP -7/ A/cm/SUP 2/ at 80 V reverse bias and breakdown voltage >200 V have been fabricated using RF-plasma deposited Si/SUB 3/N/SUB 4/ layers as the encapsulant.     

A precision bipolar current-differencing amplifier

A temperature-stable wide-band current-differencing amplifier resulting from the replacement of the usual operational amplifier structures by integrable current-operated modules is reported. This unity gain network features nearly ideal terminal characteristics (R/SUB IN/<0.3 /spl Omega/, R/SUB OUT/ /spl esdot/ 2 M/spl Omega/) and an external adjustment to maximize the subtraction accuracy, or current gain common mode rejection ratio.     

1000-V, 30-A 4H-SiC BJTs with high current gain

This paper presents the development of 1000 V, 30A bipolar junction transistor (BJT) with high dc current gain in 4H-SiC. BJT devices with an active area of 3/spl times/3 mm/sup 2/ showed a forward on-current of 30 A, which corresponds to a current density of 333 A/cm/sup 2/, at a forward voltage drop of 2 V. A common-emitter current gain of 40, along with a low specific on-resistance of 6.0m/spl Omega//spl middot/cm/sup 2/ was observed at room temperature. These results show significant improvement over state-of-the-art. High temperature current-voltage characteristics were also performed on the large-area bipolar junction transistor device. A collector current of 10A is observed at V/sub CE/=2 V and I/sub B/=600 mA at 225/spl deg/C. The on-resistance increases to 22.5 m/spl Omega//spl middot/cm/sup 2/ at higher temperatures, while the dc current gain decreases to 30 at 275/spl deg/C. A sharp avalanche behavior was observed at a collector voltage of 1000 V. Inductive switching measurements at room temperature with a power supply voltage of 500 V show fast switching with a turn-off time of about 60 ns and a turn-on time of 32 ns, which is a result of the low resistance in the base.     

Gigahertz-band high-gain low-noise AGC amplifiers in fine-line NMOS

The design and test results of a single-chip NMOS automatic gain control (AGC) amplifier are described. The amplifier has a maximum flat gain of 50 dB, dynamic range of 70 dB, and a noise figure of 11 dB. The flat response from near DC to a 3-dB bandwidth of 1 GHz does not require tuning of any peaking circuits. The chip is also capable of operating at 3 GHz with unity gain delivering -8 dBm into a 50-/spl Omega/ load. The global feedback scheme designed for this chip stabilizes it against large shifts in threshold voltage and ambient temperature variation of 170/spl deg/C. This feedback scheme can provide stable DC feedback for a forward amplifier gain of at least 60 dB. Application of this application in the design of low-noise high-speed fibre-optic systems is envisaged.     

Power feedthrough via C/SUB cb/ in common-emitter class C RF power amplifiers-a commonly believed fallacy

It is suggested that the assumption that the direction of power flow through C/SUB cb/ of the transistor is necessarily from the input-drive source to the amplifier output is a fallacy. Depending on the collector circuit tuning, RF power may be fed to the drive source from the amplifier, or vice versa, or zero RF power may be exchanged through C/SUB cb/. The importance of a correct understanding of this subject is emphasized. It can guide the engineer in designing amplifiers which have higher power gain, higher collector efficiency, more margin of stability against oscillation, and which function properly by design instead of by luck. Circuit operation is explained with reference to experimental voltage and current waveforms.