Switched-current circuits test using pseudo-random method

A built in Pseudo-Random sequence testing for testing embedded switched-current filters is described in this paper. The generation approach of Pseudo-Random sequence and the match for z functions of switched-current filters is analyzed and calculated. Taking into account of the connection between special structural problems and CMOS’s parameters in switched current circuits such as the drain-gate capacitance C _dg , gate-source capacitance C _gs and transconductance g _m., a integrated fault model for testing is constituted. A 6-order switched-current low-pass filter has been tested based on catastrophic and parametric fault models. The technique does not intrude into the actual design of the switched-current blocks, Pseudo-Random sequence generated from existing digital hardware and analogue output pins are not required.     

A comparative study of charge pumping circuits for flash memory applications

Flash memories are now widely used in many portable electronic devices, in embedded systems and are even as replacement for computer hard disks. In flash memory systems, high-voltages (up to about 10 V) are indispensable for programming operations. In many cases, however, such programming voltages are not directly available from the supply, and are usually generated by embedded voltage converting or charge pumping circuits. These circuits produce the required programming voltage from available external supplies with voltages in the approximate range of 1–5 V. The power conversion efficiency, the chip size, the voltage regulation, as well as the loading characteristics have been the major concerns for such circuits. The present paper discusses some recently proposed charge pumping circuits for flash memory applications. We focus on the effects of the dynamic gate control, the 4-phase gate-boosting and cross-coupled configuration for enhancing the performance of the charge pump circuits. Several different charge pumps operated under different working conditions are then investigated in detail.     

Switched-current circuits in digital CMOS technology with low charge-injection errors

In this paper, digital CMOS switched-current (SI) circuits with low charge-injection errors are presented. These circuits are based on the operation of the switches at virtual-ground nodes to result in signal-independent charge injection. Based on this scheme, different topologies for the memory cell are discussed. To verify the theoretical concepts developed, a third-order elliptic low-pass SI filter is implemented in a 0.25-/spl mu/m digital CMOS process. The filter nominally operates with a clock frequency of 10 MHz, cutoff frequency of 1 MHz, and a power supply of 2.3 V, while consuming 29 mW of power and processing input signals as large as 600-/spl mu/A peak differential. The low-charge injection nature of the circuit is reflected in its low total harmonic distortion of -59 dB for a 0.3-MHz signal with a modulation index of 0.5.     

小波变换开关电流电路CAD设计

用开关电流技术实现小波变换,关键是小波滤波器的实现;小波滤波器传输表达式可通过对小波基函数的有理逼近来获得。基于Padé逼近的方法,采用高斯函数族作为小波基函数,对所选的高斯函数进行频域的有理分式逼近来获取小波滤波器传输表达式,从数学上提出一种设计小波变换开关电流(SI)滤波器的CAD方法。结合SI的电流模信号特点,利用双二次滤波器的性质,用SI单元电路的级联结构来实现电路的灵活设计。设计举例给出了设计思路,MATLAB仿真结果显示这种方法的可行性。     

MOSFET memory circuits

Metal-oxide-semiconductor first effect transistors (MOSFETs) are currently being used in a variety of memory applications. The requirements of memory usage and the characteristics of MOSFET devices and technology have led to a number of unique circuits for these applications. Organization and design considerations of memory systems using MOSFET devices are reviewed, and examples of specific circuits are presented and analyzed. These include random access cells, shift registers, read only storage, and on-chip support circuits; both complementary and noncomplementary circuits are discussed.     

High-speed high-precision min/max circuits in CMOS technology

New voltage-mode min/max circuits are introduced that have a simple architecture. Unlike conventional winner-take-all or source follower based schemes, the proposed circuits are characterised by reduced voltage swing at all internal nodes and by a very low output impedance, which enables them to provide high-speed and high-precision operation. Their complexity grows linearly with the number of inputs. The characterisation of a test chip prototype has provided experimental verification of these features     

Investigation of EBG surface performance for high-precision GPS applications

A mushroom-like electromagnetic bandgap (EBG) surface for interference mitigation in GPS L2 and L1 band is presented. This printed metallo-dielectric structure is designed to act like commercially available choke rings (cylindrically corrugated surface). Measurements exhibit comparable performance, while weight and thickness are significantly reduced.     

CMOS RF circuits for data communications applications

The author describes the recent development of two analog CMOS circuits operating at RF frequencies with applications to data communications. One is a four-quadrant analog multiplier which exhibits a 100-MHz bandwidth with a measured linearity error of 0.7% for X and Y inputs of 0.6 and 0.8 V, respectively. The other is a 90/spl deg/ phase shifter which maintains the grain and phase errors of less than 0.5 dB and 3/spl deg/, respectively, for a signal within 40-60-MHz frequency range.     

CMOS/SOS memory circuits for radiation environments

Memory circuit techniques which combine radiation hardness with high density, high speed, and low power dissipation have been developed. CMOS/SOS circuits featuring self-compensation, self-biasing, and parameter tracking accommodate a wide range of nonuniform on-chip parameter variations. These variations may occur as the result of exposure to a nuclear radiation event or from MOS device processing, temperature, or power-supply effects. The circuits discussed in this paper are key elements for radiation-hardened memory designs [up to 10/SUP 6/ rad (Si)] with state-of-the-art LSI density and performance. The CMOS/SOS memory cell sizes (3.1 mil/SUP 2/ for a six-device static cell and 2.5 mil/SUP 2/ for a four-device static cell) are nearly five times smaller than previous radiation-hardened cells.     

Switched-current chaotic neurons

The authors present two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural networks. They have been fabricated in a double-metal, single-poly 1.6 μm CMOS technology. The neuron soma circuits use a novel, highly accurate CMOS circuit strategy to realise piecewise-linear characteristics in the current-mode domain. Their prototypes obtain reduced area and low voltage power supply (down to 3 V) with a clock frequency of 500 kHz     

Active-pull-down nonthreshold logic BiCMOS circuits for high-speedlow-power applications

A new active-pull-down nonthreshold logic (APD-NTL) BiCMOS circuit is presented and its performance has been evaluated and compared to that of standard NTL gate. The circuit utilizes an NMOS active-pull-down emitter-follower stage. A first-order analysis has been conducted to demonstrate the NMOS-APD concept. Simulation results based on 0.6 μm BiCMOS technology indicate that at a power consumption of 1 mW/gate, the APD-NTL circuit offers 4× improvement in the load driving capability and 3.4× improvement in the speed compared to conventional NTL circuits for a load of 1 pF/gate and a logic swing of 800 mV     

Switched-current circuit design issues

Switched-current (SI) circuits represent a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. Unlike switched-capacitor (SC) circuits, SI circuits require only a standard digital CMOS process. SI circuits use MOS transistors as the storage elements to provide analog memory capability. Similar to the operation of dynamic logic circuits, a voltage is sampled onto the gate of a MOSFET and held on its noncritical gate capacitance. The held voltage signal on the gate causes a corresponding held current signal in the drain, usually proportional to the square of the gate-to-source voltage. Design issues related to the implementation and performance of SI circuits are presented. SI filters show comparable performance to SC filters except in terms of passband accuracy. The major source of error is nonunity current gain in the SI integrator due to device mismatch and clock-feedthrough effects. For the initial CMOS prototypes, the current track and hold (T/H) gain error was about 2.5%     

PVD HfO/sub 2/ for high-precision MIM capacitor applications

Metal-insulator-metal (MIM) capacitors are fabricated using sputtered HfO/sub 2/ with Ta and TaN for top and bottom electrodes, respectively. High-capacitance densities from 4.7 to 8.1 fF//spl mu/m/sup 2/ have been achieved while maintaining the leakage current densities around 1 /spl times/ 10/sup -8/ A/cm/sup 2/ within the normal circuit bias conditions. A guideline for the insulator thickness and its dielectric constant has been obtained by analyzing the tradeoff between the linearity coefficient and the capacitance density.     

Switched-current oversampling converters

There are many choices in designing a real-time signal processing system. To exploit the advantages that inexpensive digital CMOS process technologies provide, it is usually a good choice to use digital signal processing circuits extensively and to use analog circuits only as a bridge between the real analog world and digital signal processing circuits. The mixed analog/digital circuits usually have high performance and low cost. SI oversampling converters in particular are the ideal choice as the front ends for the mixed analog/digital design. They serve to bridge the real world and modern process technologies     

Switched-current signal processing for video frequencies and beyond

Switched-current (SI) signal processing circuits with video frequency performance are presented. The delay cells employ negative feedback to produce a `virtual earth' at the input node to improve transmission accuracy. Fully differential structures with common-mode feedback are used to reduce charge injection errors and crosstalk from digital signals. An IC test circuit, in a 1 μm standard digital CMOS process, containing simple delay lines and an FIR filter section is described, and measured performance is given. Typically, a 2T delay line sampling at 13.3 MHz gave a low-frequency gain error of -54 dB, a settling error of -60 dB, a third-harmonic distortion of -40 dB with 75% modulation, and an S/N ratio of 60 dB. Scaling of the memory cell device dimensions and currents should permit SI operation at clock frequencies beyond 100 MHz     

Logic and memory with nanocell circuits

Molecular electronics is an emerging field that seeks to build faster, cheaper, denser computers from nanoscale devices. The nanocell is a molecular electronics design wherein a random, self-assembled array of molecules and metallic nanoparticles is addressed by a relatively small number of input/output pins. The challenge then is to program the nanocell post-fabrication. We have previously demonstrated the ability to program individual simulated nanocells as logic gates. In this paper, we further explore the problem of programming nanocells and consider connecting nanocells into circuits using bistable latches at the interconnects. These latches are critical because they permit signal restoration. Simulated nanocell circuits for logic and memory are presented here.     

Magnetic bubble memory linear interface circuits

Two bipolar integrated circuits are described which provide the write and sense functions required by magnetic bubble memory systems, both organized in four-channel format to minimize board area occupied. The write driver circuit has a 300 mA drive capability and includes on-chip circuitry which prevents fusing of the delicate bubble `hairpin' structure under fault conditions. The sense amplifier has programmable sensitivity in the range of 1 mV to 10 mV and allows the bubble device to be directly coupled to the differential input while tolerating DC offsets of up to /spl plusmn/150 mV without significantly modifying sensitivity.     

High-speed memory architectures for multimedia applications

In order to meet the requirements for multimedia applications, several approaches to DRAM architecture have emerged. Instead of a single, common memory device, several advanced approaches, such as extended data out (EDO) DRAM, and synchronous DRAM (SDRAM) will each play a major role in the future memory market. Furthermore, advanced interface technologies, such as Rambus RAM (RDRAM), RamLink, and SyncLink are very promising for future-generation memory. Also, application-specific memory, such as cache DRAM (CDRAM), enhanced DRAM (EDRAM), and video DRAM (VRAM) offer unique characteristics to improve performance in particular applications. Since it is beneficial to understand which type of high-speed memory can improve the speed performance of a particular system most effectively, this article discusses the fundamental concepts of these recent high-speed performance memory architectures to aid in the selection of memories for multimedia applications