TCAM/CAM-QCA: (Ternary) Content Addressable Memory using Quantum-dot Cellular Automata

This paper describes a Content Addressable Memory (CAM) architecture and its ternary variant called Ternary Content Addressable Memory (TCAM) using the Quantum-dot Cellular Automata (QCA). QCA is an alternative to the current integrated circuit (CMOS) paradigm based on the characteristics of confinement and mutual repulsion between electrons. It is expected to run with clocks in high frequency (in THz order), in nanometers scale and with very low energy consumption. First, this work presents the basic building blocks (1-bit memory cell, array of memory cells, ternary memory line and encoder). Then, we describe the complete TCAM and CAM architectures. Finally, the proposed architectures are tested and validated using QCADesigner simulator, attesting their functionalities. If QCA consolidates as a possible CMOS substitute, this study can impact the design of future components that uses TCAM and CAM such as routers and switches respectively.     

Novel multiple-selected and multiple-valued memory design using negative differential resistance circuits suitable for standard SiGe-based BiCMOS process

A novel multiple-selected and multiple-valued memory (MSMVM) design using the negative differential resistance (NDR) circuits is demonstrated. The NDR circuits are made of Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT). During suitably designing the parameters and connecting three MOS–HBT–NDR circuits, we can obtain the three-peak current–voltage (I–V) curves with different peak currents in the combined I–V characteristics. For the traditional resonant-tunneling-diode (RTD) memory circuit, one can only obtain four-valued memory states using a constant current source to bias the three-peak NDR circuit. However in this paper, we utilize two switch-controlled current sources to bias the three-peak NDR circuit at different current levels. By controlling the switches on and off alternatively, we can obtain the four-valued, three-valued, two-valued, and one-valued memory levels under the four different conditions. Our design is based on the standard 0.35 μm SiGe BiCMOS process.     

Lossless average inductor current sensor for CMOS integrated DC–DC converters operating at high frequencies

A novel average inductor current sensing circuit integrable in CMOS technologies is presented. It is designed for DC–DC converters using buck, boost, or buck-boost topologies and operating in continuous conduction mode at high switching frequencies. The average inductor current value is used by the DC–DC controllers to increase the light load power conversion efficiency (e.g., selection of the modulation mode, selection of the dynamic width of the transistors). It can also be used to perform the constant current charging phase when charging lithium-ion batteries, or to simply detect overcurrent faults. The proposed average inductor current sensing method is based on the lossless sensing MOSFET principle widely used in monolithic CMOS integrated DC–DC converters for measuring the current flowing through the power switches. It consists of taking a sample of the current flowing through the power switches at a specific point in time during each energizing and de-energizing cycle of the inductor. By controlling precisely the point in time at which this sample is taken, the average inductor current value can be sensed directly. The circuit simulations were done with the Cadence Spectre simulator. The improvements compared to the basic sensing MOSFET principle are a lower power consumption because no high bandwidth amplifier is required, and less noise emission because the sensing MOSFET is no more switched. Additionally, the novel average inductor current sensing circuit overcomes the low bandwidth limitation previously associated with the sensing MOSFET principle, thus enabling it to be used in DC–DC converters operating at switching frequencies up to 10 MHz and above.     

A new circuit configuration for a static memory cell with an area of 880 /spl mu/m/SUP 2/

A new 5-transistor memory cell in double polysilicon technology with depletion-load elements and a minimum linewidth of 3 /spl mu/m is presented. The circuit configuration, based on a Schmitt trigger, leads to static memory cells having a bit density of 1100 bit/mm/SUP 2/ and an average power consumption of 5.5 /spl mu/W/cell. With the help of computer simulations the static and dynamic behavior of the basic circuit are calculated and discussed in detail as well as the two possible operation modes of the memory cell. These results compare favorably with the experimental results obtained on a realized 2/spl times/4 memory array. The performance of the proposed memory cell is the same as that of a conventional 6-transistor cell, but the area is reduced.     

S/sup 2/I: a switched-current technique for high performance

A new switched-current memory cell is presented which enhances basic cell performance through successive refinement of the memorised sample. This is achieved in a two-step technique, called S/sup 2/I, in which the input sample is coarsely memorised, a process which introduces a combination of all the normal errors followed by detection and suppression of the combined errors. The circuit solution requires the addition to the basic memory cell of only extra switches and so carries few of the penalties associated with alternative techniques.<>     

半绝缘GaAs光电导开关亚皮秒传输特性的研究

 本文应用Ensemble-Monte Carlo方法模拟了半绝缘GaAs(SI-GaAs)光电导开关基于Auston等效电路亚皮秒传输特性.从载流子在开关体内的动态特性出发,研究了光电导开关在飞秒激光脉冲触发下光电导传输特性、电介质弛豫特性、开关储能特性以及开关工作模式;分析了非线性光电导开关对光能阈值和偏置电场阈值要求的物理机制.     

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations

The variation tolerant assist circuits of an SRAM against process and temperature are proposed. Passive resistances are introduced to the read assist circuit with replica memory transistors to lower the wordline voltage accurately reflecting the process and temperature variations. For the sake of not only enlarging the write margin but also reducing power consumption and speed overhead, the divided dynamic power-line scheme based on a charge sharing is adopted. Test chips of 512-Kb SRAM macros and isolated memory cell TEGs are fabricated using 45-nm bulk CMOS technology. Two types of 6-T SRAM cells, whose sizes were 0.245 mum² and 0.327 mum² were designed and evaluated. From the measurement results, we achieved over 100-mV improvement for static noise margin, and 35 mV for write margin for both SRAM cells at 1.0-V worst condition by using assist circuitry. It enables the wordline level to keep higher voltage at the slowest condition than the typical process condition, which results in 83% improvement of the cell current compared with the conventional assist circuit. Furthermore, the minimum operating voltage in the worst case condition was improved by 170 mV, confirming a high immunity against process and temperature variations with less than 10% area overhead.     

0.75 V micro-power SI memory cell with feedthrough error reduction

A simple technique to realise a switched current memory cell operating from low supply voltage (0.75 V) with clock-feedthough (CFT) error reduction is presented. Unlike previous techniques that try to minimise current error by compensation at the output, this technique prevents the occurrence of current error by removing the feedthrough voltage from the input port of the memory transistor directly. As a result, the CFT error current at the output is almost completely eliminated employing a simple and compact circuit structure. Simulation results are given, showing good agreement to the theory.     

Design of Integrated Selection and Recirculation Circuitry for a High-Speed, Low-Power, Magnetic Thin-Film Memory

The circuit design for a high-speed, low-power, magnetic thin-film memory is described. The modest operating-current requirements of the memory element, 50 milliampere word currents and 40 milliampere bit currents, permit the use of integrated selection and recirculation circuits. The selection system uses one transistor per word line and has a matrix array of word drivers and word switches to select one word line. Word current rise time is 2 to 3 nanoseconds. The 1-millivolt readout signal, 6 nanoseconds in duration, is amplified by means of a high-gain (1400), wide-band (50 Mc/s) sense amplifier with a differential input stage. Information is written into the memory with a bit driver which generates 40 milliampere current pulses of either polarity. Design considerations such as the ac coupling in the sense arnplifier, the relation between amplifier internal noise and system mean free time between errors, and the minimization of noise are discussed. A variety of transistor geometries was used to optimize the devices to the individual circuit functions. These geometries are illustrated.     

A new architecture of photonic ATM switches

A photonic asynchronous transfer mode (ATM) switch architecture for ATM operation at throughputs greater than 1 Tbit/s is proposed. The switch uses vertical-to-surface transmission electrophotonic devices (VSTEPs) for the optical buffer memory, and an optical-header-driven self-routing circuit in contrast with conventional photonic ATM switches using electrically controlled optical matrix switches. The optical buffer memory using massively parallel optical interconnections is an effective solution to achieve ultra-high throughput in the buffer. In the optical-header-driven self-routing circuit, a time difference method for a priority control is proposed. For the optical buffer memory, the write and read operations to and from the VSTEP memory for 1.6 Gbit/s, 8-bit optical signal are confirmed. The optical self-routing operation and priority control operation by the time difference method in the 4×4 self-routing circuit were performed by 1.6-Gbit/s 256-bit data with a 10-ns optical header pulse     

一种动态电流测试产生方法的SPICE模拟验证

数字电路状态发生改变时,数字电路中的逻辑跳变直接影响电路中的动态电流.基于布尔过程的波形模拟器能够快速准确地对电路进行模拟,其结果既能反映电路的逻辑特性又能反映电路的定时特性.利用波形模拟器可以准确的了解电路中跳变的情况.本文利用波形模拟器改进并实现了一种基于逻辑跳变计数的动态电流测试方法.对于S208电路中的部分开路故障和延时故障,本文用该方法产生了一组测试结果,并利用SPICE软件对这些测试结果进行了模拟实验.模拟结果表明,对于某些故障,测试向量对能够使故障电路的动态电流和无故障电路的动态电流产生较大的差别.通过比较两者平均动态电流的大小,我们能够区分出故障电路和无故障电路.实验结果验证了本文中的动态电流测试产生方法的有效性和可行性.     

Simulation of the neurodynamic system of working memory

The electronic circuit of the basic element of a neurodynamic memory system has been developed and implemented. The dynamic modes of the circuit and its responses to different external signals have been investigated experimentally. The circuit under study is shown to have all dynamic properties required for the memory system. The experimental results agree with those obtained in the previous theoretical studies of the neurodynamic memory system.     

A 10-b 120-MS/s 45?nm CMOS ADC using a re-configurable three-stage switched amplifier

A 10-b 120-MS/s pipeline analog-to-digital converter (ADC) is implemented in a 45?nm CMOS process. Three-stage amplifiers based on reversed nested Miller compensation and Multipath zero cancellation techniques are employed in the input sample-and-hold amplifier (SHA) and two multiplying digital-to-analog converters (MDACs). A single re-configurable three-stage switched amplifier is shared between two adjacent MDACs without MOS series switches and memory effects by employing two separate NMOS input pairs. A charge redistributed input sampling network properly handles both single-ended and differential SHA inputs with a swing range of 1.2?Vpp around a 1.6?V common-mode voltage. The prototype ADC with an active die area of 0.58?mm² consumes 61.6?mW at 120?MS/s and 1.1?V. The measured differential and integral nonlinearities are within ±0.44 and ±0.75?LSB, respectively. At a sampling rate of 120?MHz with a 4.2?MHz sinusoidal input, the measured maximum signal-to-noise-and-distortion ratio and spurious-free dynamic range are 55.6 and 70.4?dB, respectively.     

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

A 64-Mb dynamic random access memory (DRAM) with a 30-ns access time and 19.48-mm×9.55-mm die size has been developed. For reducing inter-bit-line coupling noise, the DRAM features a latched-sense, shared-sense circuit with open bit-line readout and folded bit-line rewrite operations. To reduce test costs and increase chip reliability, it has been equipped with built-in self-test and self-repair (BIST and BISR) circuits that use spare SRAM cells     

Low power dynamic circuit for power efficient bit lines

In this paper, a low power dynamic circuit is presented to reduce the power consumption of bit lines in multi-port memories. Using the proposed circuit, the voltage swing of the pull-down network is lowered to reduce the power consumption of wide fan-in gates employed in memory’s bit lines. Wide fan-in OR gates are designed and simulated using the proposed dynamic circuit in 90 nm CMOS technology. Simulation results show at least 40% reduction of power consumption and 1.2X noise immunity improvement compared to the conventional dynamic circuits at the same delay. Exploiting the proposed dynamic circuit, wide fan-in multiplexers are also designed. The multiplexers are simulated using a 90 nm CMOS model in all process corners. The results show 41% power reduction and 27% speed improvement for the proposed 128-input multiplexer in comparison with the conventional multiplexer at the same noise immunity.     

A Capacitive-Based Accelerometer IC Using Injection-Nulling Switch Technique

This paper presents a new fully integrated sensing interface and signal-conditioning application-specific integrated circuit (ASIC) for automotive accelerometers based on an ldquoinjection-nulling switchrdquo (INS) technique. The INS technique simplifies the design of both the switched-capacitor (SC) sensing amplifier and its supporting building blocks without jeopardizing its performance. This is done by counteracting the impact of charge injection and clock-feedthrough effects on sensitivity, resolution, and offset. It also decreases the number of opamps, capacitors, and switches being used. This results in reduction of power consumption, potential switching noise, and noise (sampled thermal noise which increases with the number of SC pairs being used) in the ASIC. A two-chip approach has been adopted in the implementation, with sensing element and ASIC. The built-in trimming circuitry and signal-conditioning blocks, which includes a self-test circuit, are implemented internally to eliminate the need for external components. The experimental results have shown that the sensing system IC has achieved a power consumption of 10 mW (2 mA at 5 V), a maximum noise root spectral density of 11.87 equivalent to rms noise root spectral density of 0.187 at 15.63 Hz, a signal-to-noise dynamic range of 77dB for 500-Hz bandwidth and 74 dB for 1-kHz bandwidth based on 50 g, and a maximum clock noise of 1.562 mV. The die size of the ASIC is 2.8 mm 2.3 mm using a standard 0.6- mum CMOS technology.     

Dynamic range and switching speed limitations of an N×Noptical packet switch based on low-gain semiconductor optical amplifiers

Two important system performance limitations-dynamic range and switching speed-of an integrated packet switch fabric based on low-gain semiconductor optical amplifiers (SOA's) have been examined by using cascaded blocks of an SOA model, which includes transient effect, nonlinear pulse distortion effect, and amplified spontaneous emission (ASE) noise. Low-gain SOA's were used to minimize ASE noise considering that no optical filters can be integrated in an SOA-based switch fabric. The system performance with and without a narrowband optical filter at the receiver were both studied. By assuming fixed-wavelength transmitters and no optical filter can be used at the receiving end owing to the unpredictability of arriving packet wavelengths, our simulation results indicate that the dynamic ranges of 4×4 and 8×8 SOA-based packet switches at 2.5 Gb/s can only be about 3.2 and 0.8 dB, respectively. However, at 155 Mb/s, even without a receiving-end optical filter, the dynamic range of each switch size can be increased by more than 17 dB as compared to the cases of 2.5 Gb/s. Note that the dynamic ranges were estimated under the conditions of a bit error rate (BER) ⩽10^-9 and a pulse distortion ratio ⩽30%. We have also shown that, when an optical filter with a 1 nm bandwidth was used at the receiving end to simulate (1) a circuit-switched condition where the center wavelength of the filter can be adjusted according to the established circuit, or (2) a packet-switched condition where each receiver has a wavelength demultiplexer and a detector array, the dynamic range of 4×4 and 8×8 switches can be increased to 16.3 and 14 dB, respectively, at 2.5 Gb/s     

Application of source biasing technique for energy efficient DECODER circuit design: memory array application

Researchers have proposed many circuit techniques to reduce leakage power dissipation in memory cells.If we want to reduce the overall power in the memory system,we have to work on the input circuitry of memory architecture i.e.row and column decoder.In this research work,low leakage power with a high speed row and column decoder for memory array application is designed and four new techniques are proposed.In this work,the comparison of cluster DECODER,body bias DECODER,source bias DECODER,and source coupling DECODER are designed and analyzed for memory array application.Simulation is performed for the comparative analysis of different DECODER design parameters at 180 nm GPDK technology file using the CADENCE tool.Simulation results show that the proposed source bias DECODER circuit technique decreases the leakage current by 99.92％ and static energy by 99.92％ at a supply voltage of 1.2 V.The proposed circuit also improves dynamic power dissipation by 5.69％,dynamic PDP/EDP 65.03％ and delay 57.25％ at 1.2 V supply voltage.     

A high-speed clamped bit-line current-mode sense amplifier

A clamped bit-line current-mode sense amplifier that maintains a low-impedance fixed potential on the bit lines is introduced. Using a general model for active-drive memory cells that include the two-transistor (2T) and three-transistor (3T) dynamic cells and the four-transistor/two-resistor (4T-2R) and six-transistor (6T) static cells, the new sense amplifier is shown to have a response speed that is insensitive to bit-line capacitance. This is achieved by relocating the large bit-line capacitance to a node within the sense amplifier that has only a minimal effect on the speed of the circuit. Bit-line clamping also minimizes inter-bit-line voltage noise coupling     

A Complementary Switched MOSFET Architecture for the 1/f Noise Reduction in Linear Analog CMOS ICs

We present a novel principle for 1/f noise reduction in linear analog CMOS ICs. The principle is experimentally demonstrated for a two-stage CMOS Miller operational amplifier in a standard 0.12-mum, 1.5-V digital CMOS technology. A threefold 1/f noise reduction (5 dB) is achieved at 10 Hz compared with a reference circuit. The impact of the principle on the circuit performance is investigated