Parallel Turing Machine,a Proposal

We have witnessed the tremendous momentum of the second spring of parallel computing in recent years. But, we should remember the low points of the field more than 20 years ago and review the lesson that has led to the question at that point whether “parallel computing will soon be relegated to the trash heap reserved for promising technologies that never quite make it” in an article entitled “the death of parallel computing” written by the late Ken Kennedy — a prominent leader of parallel computing in the world. Facing the new era of parallel computing, we should learn from the robust history of sequential computation in the past 60 years. We should study the foundation established by the model of Turing machine (1936) and its profound impact in this history. To this end, this paper examines the disappointing state of the work in parallel Turing machine models in the past 50 years of parallel computing research. Lacking a solid yet intuitive parallel Turing machine model will continue to be a serious challenge in the future parallel computing. Our paper presents an attempt to address this challenge by presenting a proposal of a parallel Turing machine model. We also discuss why we start our work in this paper from a parallel Turing machine model instead of other choices.     

Semantic Inference for Anaphora Resolution: Toward a Framework in Machine Translation

Anaphora is a discourse-level linguistic phenomenon.There is consensus that anaphora resolution shouldrely on prior sentences within the context of thediscourse. We propose to cast anaphora resolution asa semantic inference process in which a combination ofmultiple strategies, each exploiting different aspectsof linguistic knowledge, is employed to provide acoherent resolution of anaphora. A framework whichencompasses several salient linguistic parameters suchas grammatical role, proximity, repetition, sentencerecency and semantic cues is demonstrated. This workalso shows how an anaphora-resolution algorithm can beembedded within a framework which captures all theabove salient parameters, as well as remedies some ofthe inadequacies found in any monolithic resolutionsystem. A language-neutral semantic representationcharacterized by semantic cues is presented in orderto capture the distilled information after resolution.The effectiveness of the language-neutralrepresentation, both for machine translation andanaphora resolution, is demonstrated through a set ofsimulations and evaluations.     

New Methodologies for Parallel Architecture

Moore's law continues to grant computer architects ever more transistors in the foreseeable future, and parallelism is the key to continued performance scaling in modern microprocessors. In this paper, the achievements in our research project, which is supported by the National Basic Research 973 Program of China, on parallel architecture, are systematically presented. The innovative approaches and techniques to solve the significant problems in parallel architecture design are summarized, including architecture level optimization, compiler and language-supported technologies, reliability, power-performance efficient design, test and verification challenges, and platform building. Two prototype chips, a multi-heavy-core Godson-3 and a many-light-core Godson-T, are described to demonstrate the highly scalable and reconfigurable parallel architecture designs. We also present some of our achievements appearing in ISCA, MICRO, ISSCC, HPCA, PLDI, PACT, IJCAI, Hot Chips, DATE, IEEE Trans. VLSI, IEEE Micro, IEEE Trans. Computers, etc.     

A Real-Time Image Segmentation on a Massively Parallel Architecture

The method described in this paper enables the two end points of a straight line to be obtained by a Modified Double Hough Transform (MDHT). It consists respectively of line detection, followed by segment extraction. The significance of this work is that the hardware implementation is based on the Content Addressable Memory (CAM) concept. Hence, during the first HT, voting is achieved for the every scan line of image, not every edge pixel. Therefore, all the steps which form the first HT: voting, thresholding and local maximum are achieved in a low constant time. The two end points of the line are extracted through the second HT. Here, a local neighbor parallel search is also achieved at the end of each scan line of the image not at every edge pixel. Therefore, the execution time is low since the neighboring range does not exceed a few lines. Experimental results are given to show the accuracy of our approach for use in high performance pattern recognition systems.     

并行视频服务器体系结构研究

分析了目前流行的并行视频服务器体系结构：分布式结构、集群式结构、并行通用计算机结构和并行专用视频服务器结构。综合其优点,针对视频应用的特点,提出了可扩展并行视频服务器体系结构,并研制了基于该结构的并行服务系统。     

Parallel Implementation of a Machine Learning Algorithm on GPU

The capability for understanding data passes through the ability of producing an effective and fast classification of the information in a time frame that allows to keep and preserve the value of the information itself and its potential. Machine learning explores the study and construction of algorithms that can learn from and make predictions on data. A powerful tool is provided by self-organizing maps (SOM). The goal of learning in the self-organizing map is to cause different parts of the network to respond similarly to certain input patterns. Because of its time complexity, often using this method is a critical challenge. In this paper we propose a parallel implementation for the SOM algorithm, using parallel processor architecture, as modern graphics processing units by CUDA. Experimental results show improvements in terms of execution time, with a promising speed up, compared to the CPU version and the widely used package SOM_PAK.     

Cognitive Architecture,Holistic Inference and Bayesian Networks

Minds and Machines - Two long-standing arguments in cognitive science invoke the assumption that holistic inference is computationally infeasible. The first is Fodor’s skeptical argument...     

一个工作负载驱动并行结构模拟器的设计与实现

简单介绍了并行多处理机结构模拟现状,讨论了一个实际工作负载驱动模拟器的设计与实现。     

Functionally Parallel Architecture for Array Processors

Based on the natural division of mathematical problems, functional parallelism becomes the architectural key for improving speed/cost ratios for array processors.     

基于网络的分布并行虚拟计算机DPVM的总体设计

基于网络的分布式并行计算技术提供高性能、低成本的计算资源。该文介绍所构造的一个基于网络的分布并行虚拟计算机DPVM。它由虚拟机层、通信层和基本类层组成,以浏览器方式提供用户界面;允许计算机加入系统,提供空闲计算资源,或登录到系统上,获得计算资源;采用Java作为程序设计语言,支持平台无关的分布并行计算。     

多位并行MQ编码的VLSI结构研究

MQ编码算法的高复杂度,低吞吐率严重制约其应用.本文在分析连续码流编码更新规律的基础上,利用滑动窗口机制和概率统计规律预测区间变化,减少并行数据间的关联,设计出三种不同并行度的MQ编码VLSI结构.并在FPGA芯片上进行优化实现.实验结果表明,与单输入MQ编码器相比,三种结构能在不影响器件工作频率和编码效率的情况下,不同程度的提高系统的处理速率,为MQ编码的大规模应用提供了广泛的选择空问.     

高性能并行分组交换结构的研究

随着高速宽带通信网络的发展,网络设备的交换能力正成为制约现代网络发展的主要瓶颈之一。并行交换结构能够极大提升网络设备的交换能力,使网络设备拥有更高的交换容量和交换速率,以支持更多的网络业务。本文从交换结构模型的角度较深入的研究了高速路由器调度算法,并在基于参考交换结构和库存论原理对并行分组交换(PPS)结构稳定工作进行定义的基础上,分别分析了无输入缓存PPS和带输入缓存PPS稳定工作的充要条件。     

高性能并行分组交换结构的研究

随着高速宽带通信网络的发展,网络设备的交换能力正成为制约现代网络发展的主要瓶颈之一.并行交换结构能够极大提升网络设备的交换能力,使网络设备拥有更高的交换容量和交换速率,以支持更多的网络业务.本文从交换结构模型的角度较深入的研究了高速路由器调度算法,并在基于参考交换结构和库存论原理对并行分组交换(PPS)结构稳定工作进行定义的基础上,分别分析了无输入缓存PPS和带输入缓存PPS稳定工作的充要条件.     

Architecture Selection and Singularity Analysis of a Three-Degree-of-Freedom Planar Parallel Manipulator

A three degree-of-freedom planar parallel manipulator, intended for high-speed, high-precision wire-bonding and electronic-component placement tasks, has been developed in our laboratory. In this paper, the work related to the kinematic manipulator-architecture selection is presented. The reachable workspace and effective base area metrics of the parallel manipulator were utilized for selecting the best possible architecture amongst six potential configurations. Constant platform-orientation regions, within the reachable workspace of the selected manipulator, were identified based on the manipulator task requirements. Simulation results for the workspace analyses (reachable workspace, effective base areas, and constant-orientation regions) are presented in this paper. Once the optimal-workspace architecture was selected, both workspace-boundary and internal singularities were further investigated in order to have a clear view of the set of uncontrollable poses of the manipulator. Singularity analyses examples are also included herein.