同步米里型序列检测电路的错误输出问题

用一般时序逻辑电路的设计方法设计米里型序列检测电路中存在一些问题,在没有检测到序列时就输出了检测到信号,系统工作出现不正常。分析了存在错误输出的原因之后,提出了一种通过调整输入序列使其与时钟同步,改进状态装换表的设计,以确保系统正常工作的米里型序列检测的设计方法,这种方法有效克服了米里型序列检测的问题,并对米里型时序逻辑电路的设计有通用性。     

米里电路设计中的状态化简问题

本文讨论了米里电路设计中的状态化简问题，指出状态化简后的电路有可能不能正常工作，给出了状态化简的适用条件和使用注意事项。     

单片机的总线与口线

<正> 总线的由来 在模拟电路中,无论电路多么复杂,我们都可以把它化简为若干个等效电路,通过分析计算求出每个等效电路的输出信号和输入信号的关系,这种关系是一一对应的关系。中小规模集成电路诞生以后,每个芯片内集成了成百上千个晶体管,芯片的几个引脚作为输入输出信号的引脚,另外一些引脚作为控制信号的引脚,当然电源引脚及地也是必不可少的,这就大大简化了设计者的工作。这种芯片的输出和输入常常不再是一一对应的关系,而是针对不同的输入组合有不同的输出结果,集成电路的真值表就是表达了这种对应关系,这一阶段的电路设计还只是硬件电路的设计。自从出现微控制器以后,电路设计的思想产生了质的飞跃,任何一个模拟量,不管它是电压、电     

判奇电路实现方法探讨

以三输入判奇电路设计为例,通过对其输出函数表达式的形式变换,分别采用多种门电路及译码器、数据选择器等74系列器件进行电路设计,给出了7种电路实现形式,并分析了各种电路实现的优缺点。此例说明了组合逻辑电路设计的灵活性及电路实现的多样性。所采用的设计方法对其他组合逻辑电路设计具有一定的启发与指导意义。     

时序逻辑电路设计的经典案例教学探究

围绕时序逻辑电路设计中串行数据检测器这一教学案例进行探讨,分析了传统和两种改进型电路的设计缺陷及其逻辑抽象本质,通过将传统设计方法和实用的电路设计相结合,能够把时序逻辑电路设计中涉及的逻辑抽象、状态等价、状态化简等概念实例化,教学内容的理论体系更完整、教学过程的逻辑性更强,有助于激发同学们夯实理论知识体系、解决实际问题的创新性思维能力。     

具有硬件互斥的控制电路设计方法

文章从计算机操作系统互斥理论出发,将其软件互斥类推形成硬件电路的互斥理论,并论述了具有硬件互斥特性的系统的设计方法。并用主电源/备用电源自动交替方案说明输出互斥的设计方法,用加/减法复用电路设计说明输入互斥电路的设计方法。简要说明了多个输入或输出信号共享多个共有硬件资源的交叉互斥。     

基于输入分解输出匹配的多态自检电路进化设计

针对进化方法在多态自检电路设计方面存在的扩展性问题,该文提出了一种基于输入分解输出匹配的多态自检电路进化设计方法。该方法将原始电路分解为可进化生成部分和固定部分,由此减少待进化设计电路的输入个数以及适应度评价时真值表输入输出组合数量,从而降低电路进化复杂度;在适应度评价阶段,当电路输出位与理想输出匹配度小于1/2时,通过添加非门的形式提高候选电路适应度和种群多样性,防止最优结构的丢失。进化设计实验将多态门和普通门相结合,进行了两种多态自检加法器的设计。结果表明,与传统多态自检电路进化设计方法相比所提方法进化代数分别减少了47.9%和89.1%,单个测试参量下故障覆盖率分别提高了75.7%和79.7%,具有收敛速度快、扩展性好、故障覆盖率高的优点。     

一种0.13 μm CMOS K波段LNA

基于0.13 μm CMOS工艺,设计了一种工作于K波段的低噪声放大器。输入匹配采用一种改良π型匹配网络,输出匹配采用L+π型匹配网络,避免了电容击穿的风险和源端大电感的引入。电路使用级间L型匹配的方式,利用第一级电路的输出寄生电容和第二级电路的输入寄生电容,有效地提高了电路的增益,降低了噪声。仿真结果表明,该低噪声放大电路为单电源1.5 V供电,在27 GHz频率处的增益为27 dB,噪声系数为3.75 dB,输入回波损耗和输出回波损耗分别为－11.1 dB和－20.5 dB。     

用于电机驱动芯片的高压电荷泵电路设计

基于开关电容系统理论,提出了一种用于步进电机芯片中H桥驱动电路的电荷泵电路。电路设计了零温度系数的高压压差检测电路、线形调制的反馈控制电路和泵电容充电电流控制电路。基于HHNEC 0.35μm BCD工艺平台进行电路设计,并完成流片。测试结果显示,电荷泵电路输出电压跟随输入电压线性变化,输出电压范围为13 V~41 V,纹波电压大小约为560 mV。所获结果与设计目标保持一致,证明了设计思想的正确性。     

自适应开启时间Buck变换器定时器电路设计

设计了一种用于自适应开启时间(adaptive on-time,AOT)Buck型DC-DC变换器的定时器电路,采用了输入电压前馈补偿和输出反馈技术,使开关频率不随输入、输出电压变化,实现了固定频率的伪脉冲宽度调制。基于0.18μm BCD工艺进行电路设计,并使用Hspice仿真验证。仿真结果表明当输入电压从5~18 V,相同输出电压下开关频率变化不超过10 k Hz,不同的输出电压下系统开关频率变化不超过20 k Hz。同时,由于定时器中采用输入电压前馈技术,提高了输入线性瞬态响应速度。     

Output-extended sequential machines

A new class of sequential machine, called output-extended, is defined. In contradistinction to Moore and Mealy machines, the output state here is a function of the previous output as well as the present state and input. A particular form of output-extended machine is studied, in which the function in question is the Boolean intersection of the present output in the Mealy sense and the previous output. It is shown that this structure offers possibilities of state reduction not present in the orginal Mealy machine.     

基于可编程计数器的时序逻辑电路设计

介绍了基于MSI可编程计数器74LS161的时序逻辑电路设计技术,目的是探索MSI可编程计数器实现一般时序逻辑电路的扩展应用方法,即以计数器Q3,Q2,Q1,Q0端的代码组合表示时序逻辑电路的各个状态,由输入变量控制计数器的EP,ET及LD端,综合利用计数、置数、保持功能,使计数器的状态变化满足所要求的时序,用计数功能实现＂次态=现态＋1＂的二进制时序关系,用置数功能实现＂次态=预置数＂的非二进制时序关系,用保持功能实现＂次态=现态＂的自循环时序关系。所述方法的创新点是提出了MSI可编程计数器改变应用方向的逻辑修改方法。     

基于概率转移矩阵的时序电路可靠度估计方法

传统的概率转移矩阵(Probabilistic Transfer Matrix,PTM)方法是一种能够比较精确地估计软差错对门级电路可靠度影响的方法,但现有的方法只适用于组合逻辑电路的可靠度估计.本文提出基于PTM的时序电路可靠度估计方法(reliability estimation of Sequential circuits based on PTM,S-PTM),先把待评估时序电路划分为输出逻辑模块和次态逻辑模块,然后用本文提出的时序电路PIM计算模型得到电路的PIM,最后根据输入信号的概率分布计算出时序电路的可靠度.用ISCAS 89基准电路为对象进行实验和验证,实验表明所提方法是准确和合理的.     

Minimization of mealy finite state machines via internal state merging

The problem of minimizing Mealy finite state machines (FSMs) arises when digital devices based on programmable logic integrated circuits are synthesized. A distinctive feature of the approach proposed is that merging of two states is used and an FSM is represented as a transition list. The conditions used to merge states, the functioning identity and the FSM’s behavior determinacy, are presented. Situations leading to wait state formation caused by state merging are discussed. The algorithms for minimizing the internal states, transition paths, and input variable of FSMs are described. The features of application of the method proposed are discussed.     

Ultra-low power FinFET-based domino circuits

Aggressive scaling of single-gate CMOS device face greater challenge in nanometre technology as sub-threshold and gate-oxide leakage currents increase exponentially with reduction of channel length. This paper discusses a double-gate FinFET (DGFET) technology which mitigates leakage current and higher ON state current when scaling is done beyond 32 nm. Here 8 and 16 input OR gate domino logic circuits are simulated on 32 nm FinFET Predictive technology model (PTM) on HSPICE. Simulation results of different 8 input OR gate domino logic circuits like Current-mirror footed domino (CMFD), High-speed clock-delayed (HSCD), Modified-HSCD (M-HSCD), Conditional evaluation domino logic (CEDL) and Conditional stacked keeper domino logic (CSK-DL), all operated in Short Gate (SG) and Low Power (LP) mode, shows tremendous reduction in average power consumption and delay. In this paper, domino logic-based circuit Ultra-Low Power Stack Dual-Phase Clock (ULPS-DPC) is proposed for both CMOS and FinFET (SG and LP modes). Proposed circuit shows maximum reduction in average power consumption of 84.04% when compared with CSK-DL circuit and maximum reduction in delay of 75.4% when compared with M-HSCD circuit at 10 MHz frequency when these circuits are simulated in SG mode.     

基于数据选择器和D触发器的多输入时序电路设计

为了探索多输入时序逻辑电路的简便实现方法,介绍了基于数据选择器和D触发器的多输入时序逻辑电路设计技术。即将D触发器和数据选择器进行组合,用触发器的现态作为数据选择器选择输入变量、数据选择器的输出函数作为触发器的D输入信号,构成既有存储功能又有数据选择功能的多输入端时序网络。由触发器的现态选择输入变量、所选择的输入变量决定触发器的次态转换方向。该方法适合实现互斥多变量时序逻辑电路,且在设计过程中不需要进行函数化简。     

Precomputation-based sequential logic optimization for low power

We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. We present two different precomputation architectures which exploit this observation. The primary optimization step is the synthesis of the precomputation logic, which computes the output values for a subset of input conditions. If the output values can be precomputed, the original logic circuit can be “turned off” in the next clock cycle and will have substantially reduced switching activity. The size of the precomputation logic determines the power dissipation reduction, area increase and delay increase relative to the original circuit. Given a logic-level sequential circuit, we present an automatic method of synthesizing precomputation logic so as to achieve maximal reductions in power dissipation. We present experimental results on various sequential circuits. Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay     

Sequential circuit test generation using dynamic justification equivalence

Automatic test pattern generation (ATPG) for sequential circuits involves making decisions in the search decision spaces bounded by a sequential circuit. The flip-flops in the sequential circuit determine the circuit state search decision space. The inputs of the circuit define the combinational search decision space. Much work on sequential circuit ATPG acceleration focused on how to make ATPG search decisions. We propose a new technique to improve sequential circuit ATPG efficiency by focusing on not repeating previous searches. This new method is orthogonal to existing deterministic sequential circuit ATPG algorithms.A common search operation in sequential circuit ATPG is justification, which is to find an input assignment to justify a desired output assignment of a component. We have observed that implications in a circuit resulting from prior justification decisions form an unique justification decomposition. Since the connectivity of a circuit does not change during ATPG, test generation for different target faults may share identical justification decision sequences represented by identical decision spaces. Because justification decomposition represents the collective effects of prior justification decisions, it is used to identify previously-explored justification decisions. Preliminary results on the ISCAS 1989 circuits show that our test generator (SEST) using justification decompositions, on average, runs 2.4 and 4.5 times faster than Gentest and Hitec, respectively. We describe the details of justification equivalence and its application in ATPG accompanied with step-by-step examples.