一种优化Girth分布的准循环LDPC码设计方法研究

在准循环LDPC码的构造中,校验矩阵拥有尽可能好的girth分布对于改善码的性能有着重要的意义。该文提出了构造准循环LDPC码的GirthOpt-DE算法,优化设计以获得具有好girth分布的移位参数矩阵为目标。仿真结果表明,该文方法得到的准循环LDPC码在BER性能和最小距离上均要优于固定生成函数的准循环LDPC码,Arrary码和Tanner码,并且使用上更为灵活,可以指定码长,码率及尽可能好的girth分布。     

一种基于QCE-PEG的LDPC码构造方法

为提高LDPC码的实用性,该文提出了一种QCE-PEG校验矩阵构造方法,给出了实现具体步骤和设计实例。该算法将构造过程分解,结合准循环扩展技术和渐进边增长构造方法的优点,既能满足度分布对的需要,又保证了平均围长尽可能大的要求,提高了LDPC编码的速度和性能。仿真结果表明：用该方法设计的中短长度非正则LDPC码,其性能优于渐进边增长方法构造的PEG码,且设计简单,编码快速,便于工程实现,具有良好的应用前景。     

一种具有较大围长的正则LDPC码构造方法

提出一种新的具有较大围长的正则LDPC码构造方法。首先介绍以矩阵分裂技术为基础的高围长正则LDPC码的构造方法,并在此基础上分析了设计围长时参数的选取方法。仿真表明,用这种方法构造的正则LDPC码围长可以达到12,并且在AWGN信道下的性能不差于相同参数、随机构造的LDPC码,在高信噪比时甚至优于相同参数的随机码。     

一种基于 MDS-卷积码的LDPC码构造方法

近年来,结构化低密度奇偶校验(LDPC)码的构造方法受到了广泛地关注.本文提出了一种利用最大距离分割(MDS)编码构造结构化LDPC码的思路.该思路将基于两个信息符号的RS码构造LDPC码的方法扩展至适用于所有的MDS码.本文以具有MDS特性的卷积码为例详细描述该构造方法的细节,并构造了码长从255比特到4095比特的高码率LDPC码.由于卷积码的MDS定义不同于线性分组码,因此本文给出了一种对卷积码截短的方法及其必要的证明.仿真结果表明,本文构造MDS-Conv-LDPC码的性能优于随机构造的LDPC码.     

一种非规则广义LDPC码的构造方法

广义低密度奇偶校验(Generalized Low睤ensity Parity睠heck,GLDPC)码把低密度奇偶校验(Low睤ensity Parity睠heck,LDPC)码中的单奇偶校验(Single Parity睠heck,SPC)节点替换为校验能力更强的广义约束(Generalized Constraint,GC)节点,使其在中短码和低码率的条件下具有更低的误码率。传统GLDPC码要求基矩阵的行重等于分量码的码长,这限制了GLDPC码构造的灵活性。另外,相比于传统GLDPC码中GC节点位置的随机选取,GC节点的位置选择在GLDPC码的误码率性能上有一定的优化空间。针对以上两点,提出了一种基于渐进边增长(Progressive Edge-rowth,PEG)算法的非规则GLDPC码构造方法和一种基于Tanner图边数的GC节点位置选择算法。使用PEG算法生成的非规则LDPC码作为本地码,根据本地码的校验节点度使用多种分量码,结合GC节点位置选择算法构造非规则GLDPC码。仿真结果表明,与传统方法构造的GLDPC码相比,基于Tanner图边数的GC节点位置选择算法构造的非规则PEG-LDPC码在误码率和译码复杂度上均得到明显改善。     

适于分层译码算法的LDPC码构造方法

The layered decoding algorithm has been widely used in the implementation of Low Density Parity Check (LDPC) decoders, due to its high convergence speed. However, the pipeline operation of the layered decoder may introduce memory access conflicts, which heavily deteriorates the decoder throughput. To essentially deal with the issue of memory access conflicts, we propose a construction algorithm of LDPC codes, to which a constraint condition is added in the Progressive Edge-Growth (PEG) algorithm. The constraint condition can guarantee that for our constructed LDPC codes, the sets of all the variable nodes connected to the consecutive layers do not share any common variable node, which can avoid the memory access conflicts. Simulation results show that the performance of our constructed LDPC codes is close to the several other LDPC codes adopted in wireless standards. Moreover, compared with the decoder for IEEE 802. 16e LDPC codes, the throughput of our LDPC decoder has large improvement, while the chip resource consumption is unchanged. Thus, our constructed LD-PC codes can be adopted in the high-speed transmission.     

一种基于伪循环MDS码的准循环LDPC码构造方法

该文提出了一种利用两个信息符号的伪循环最大距离可分(MDS)码,构造围长为6的准循环低密度奇偶校验(LDPC)码的方法。在GF(q)中,它通过直接计算长为q+1的伪循环MDS码生成多项式,构造准循环LDPC码的校验矩阵。其主要利用了含两个信息符号的伪循环MDS码字特殊的循环性,及任意两个码字间距离不小于q的特点,使所构造的准循环LDPC码保证无4环。仿真结果表明,基于伪循环MDS码的准循环LDPC码在高斯信道下,能获得较好的误码性能。     

光通信中基于SCG(4,k)码的一类改进LDPC码构造方法

针对SCG(4,k)码构造方法的分析与研究,提出一种适用于光通信系统中改进的新颖低密度奇偶校验(LDPC)码构造方法.该方法在保留SCG(4,k)构造方法的基础上,采用类似于准循环的构造形式,使生成的码字不受短环干扰,并具有良好的围长特性;并且与改进前的SCG(4,k)码相比,该构造方法具有硬件实现方面节省存储空间和降低计算复杂度等优点.采用该方法构造了码率为93.7％的LDPC(3969,3720)码.仿真结果表明:这种码的净编码增益(NCG)比广泛用于光通信系统中的经典RS(255,239)码提高了1.99 dB.     

On the Construction of Quasi-Systematic Block-Circulant LDPC Codes

A class of quasi-systematic block-circulant LDPC (QSBC-LDPC) Codes is proposed. The parity-check matrix of a QSBC-LDPC code is a sparse block-circulant matrix with a quasi-systematic structure. Due to the special structure of the parity-check matrix, only limited memories, XOR computations and cyclic-shifting operations are needed in the recursive encoding process of the QSBC-LDPC codes. Simulations show that the QSBC-LDPC codes provide remarkable performance improvement with low encoding complexity.     

LDPC码的树图法构造

LDPC码译码采用的是BP算法,但由于回路的存在,使译码重复迭代,特别是短长度的回路使LDPC码的性能下降.为此,用树图法分析了LDPC码的回路及其特性,给出了求解回路长度和所经过节点的方法,非常适合于计算机进行求解.同时也用树图的方法来构造LDPC码,可以在树生成的过程中了解其中的回路数目及长度.     

基于DTMB中LDPC码与BCH码的乘积码构造

中国地面数字电视传输(DTMB)标准中的级联码能够有效降低低密度奇偶校验(Low-Density Parity-Check,LDPC)码的误码平层以获得极低的误比特率。基于DTMB标准中LDPC码与BCH码提出了一种性能优越的乘积码构造方案。构造的乘积码不仅性能优于级联码而且编译码复杂度与级联码相当,代价是较大的译码延时与较大的存储量。仿真结果表明,在码率相同且误比特率为1×10-7时,与级联码相比,构造的码长最长的乘积码可获得约0.12 dB的编码增益。     

基于素域构造的准循环低密度校验码

该文提出一种基于素域构造准循环低密度校验码的方法。该方法是Lan等所提出基于有限域构造准循环低密度校验码的方法在素域上的推广,给出了一类更广泛的基于素域构造的准循环低密度校验码。通过仿真结果证实：所构造的这一类准循环低密度校验码在高斯白噪声信道上采用迭代译码时具有优良的纠错性能。     

一种低误码平层的LDPC码的构造与实现

提出了一种分层的伪随机低密度奇偶校验码(LDPC)的构造方法,有效地改善了译码性能,尤其是降低了误码平层.然后针对这种码字,介绍了相应译码器的硬件实现结构.     

Construction of Irregular LDPC Codes by Quasi-Cyclic Extension

In this correspondence, we propose an approach to construct irregular low-density parity-check (LDPC) codes based on quasi-cyclic extension. When decoded iteratively, the constructed irregular LDPC codes exhibit a relatively low error floor in the high signal-to-noise ratio (SNR) region and are subject to relatively few undetected errors. The LDPC codes constructed based on the proposed scheme remain efficiently encodable     

High Rate APPS and Bi-APPS LDPC Codes Design with Low Error Floor and Large Girth

In this paper, two new methods to construct low-density parity-check (LDPC) codes with low error floor and large girth are proposed. The first one is APPS-LDPC codes based on Arithmetic Progression theory and cycle classification, whose girth is at least eight. Based on the designed APPS-LDPC codes, we further construct Bi-diagonal APPS-LDPC codes with column degree 4, whose circulant permutation matrix is combined by two shifted identity matrix. The designed APPS-LDPC code has 0.25 and 0.2 dB coding gain compared to partition-and-shift (PS)-LDPC code and progressive-edge-growth (PEG)-LDPC code. And the Bi-APPS-LDPC code has similar performance to T2 LDPC code in CCSDS standard, but its effective structure is more suitable for high throughput decoder implementation on FPGA. Both codes have less construction complexity than PS-LDPC code and PEG-LDPC code.     

一种线性编码半随机构造LDPC码及其仿真

文章首先给出了一种消除4环的完全随机的低密度奇偶校验(LDPC)码构造法,然后通过分析快速编码计算复杂度影响因素对其进行了改进,得到一种消除4环且可线性编码的半随机构造法.仿真表明,半随机构造法相对于完全随机构造法,其性能相接近,但却可以线性时间编码,因此更适合实际应用.     

Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes

This paper presents an architecture for high-throughput decoding of high-rate Low-Density Parity-Check (LDPC) codes. The proposed architecture is a modification of the sliced message passing (SMP) decoding architecture which overlaps the check-node and variable-node update stages, achieving a good tradeoff between area and throughput, and also, high hardware utilization efficiency (HUE). The proposed modification does not affect the performance of the SMP algorithm and yields an area reduction of 33%. As an example, SMP architecture and the proposed modification was synthesized in a 90 nm CMOS process for the 2048-bit LDPC code of the IEEE802.3an standard with 16 iterations achieving a throughput of 5.9 Gbps with 15.3 mm² and 6.2 Gbps with 10.2 mm², respectively.     

Algebraic Construction of Quasi-Cyclic LDPC Codes for the AWGN and Erasure Channels

This paper is concerned with construction of quasi-cyclic (QC) low-density parity-check (LDPC) codes for three different types of channels: the additive white Gaussian noise, the binary random erasure, and the binary burst erasure channels. Two algebraic methods for systematic construction of QC-LDPC codes are presented. Codes constructed perform well over all three types of channels.     

一种新的码率兼容LDPC码打孔方案

该文研究码率兼容LDPC码的打孔问题。Ha等人研究LDPC码打孔时提出的Grouping和Sorting方案使低k-SR节点的数目最大化,它相对于随机打孔有了很大增益,但此方案只保证有一个存活校验节点。该文研究多个存活校验节点的作用,提出MSCN打孔方案最大化打孔节点的存活校验节点数。AWGN信道上的仿真结果显示,低码率时MSCN方案具有比Grouping和Sorting方案更为优越的性能。理论推导及实验结果均表明,码率兼容LDPC码打孔时,多个存活校验节点有益于译码性能的提升。