A comprehensive approach to fixed-step simulation of switchedcircuits

Because of its reduced calculation effort and deterministic execution time, fixed-step simulation is a prerequisite for real-time performance. However, when simulating switched circuits, it introduces errors in the form of switching delays and inconsistent initial conditions. In order to eliminate these errors, the present paper describes a physically sound method for accurate and efficient fixed-step/real-time simulation of switched circuits. Assuming that switching is instantaneous and respecting the conservation of energy principle, the simulation method provides simple and straightforward procedures for eliminating switching delays and for calculating consistent initial conditions, even though the switching time may not coincide with a calculation time-step and the circuit may pass through a series of simultaneous switchings. Furthermore, the simulation method proposes a simple decoupling technique to isolate parts of the circuit where the switching occurs, in order to reduce the effort required for the calculation of initial conditions. Implementation of the proposed simulation method in the nodal approach and in the state space approach is shown. A 12 pulse thyristor rectifier and a PWM inverter are used to highlight simulation accuracy. Simulation results, with and without the simulation method, are compared to variable-step simulation and to other documented methods. Finally, the simulation of a full HVDC system serves to demonstrate real-time simulation performance     

换路定律的延拓

传统的换路定律要求电容端电压和电感中电流为有限值。本文基于电路发生换路前后瞬间电荷与磁通守恒原理,导出了与传统不同的方法来确定换路后电路的初始条件。该方法的主要点在于对电路中出现冲激变量的有效处理能力,在有限电荷和磁通的假设下,将原电路分解成不同的子电路并分别计算,从而得到最后的解。此方法同时适用于线性与非线性电路。     

All‐Metallic Vertical Transistors Based on Stacked Dirac Materials

It is an ongoing pursuit to use metal as a channel material in a field effect transistor. All metallic transistor can be fabricated from pristine semimetallic Dirac materials (such as graphene, silicene, and germanene), but the on/off current ratio is very low. In a vertical heterostructure composed by two Dirac materials, the Dirac cones of the two materials survive the weak interlayer van der Waals interaction based on density functional theory method, and electron transport from the Dirac cone of one material to the one of the other material is therefore forbidden without assistance of phonon because of momentum mismatch. First‐principles quantum transport simulations of the all‐metallic vertical Dirac material heterostructure devices confirm the existence of a transport gap of over 0.4 eV, accompanied by a switching ratio of over 10⁴. Such a striking behavior is robust against the relative rotation between the two Dirac materials and can be extended to twisted bilayer graphene. Therefore, all‐metallic junction can be a semiconductor and novel avenue is opened up for Dirac material vertical structures in high‐performance devices without opening their band gaps.     

Symbolic Steady-State Analysis for Strongly Nonlinear Circuits and Systems

A symbolic method for steady-state analysis of nonlinear circuits and systems is presented. This method is based on the principle of the Equivalent Small Parameter method (the ESP method), which is an improved perturbation technique combined with the harmonic balance method. Using this method, a set of high-order nonlinear differential equations can be solved and the symbolic expressions of the steady-state periodic solutions for the required variables can be obtained. Two examples are given and show that the method is general and can be used for both weakly and strongly nonlinear circuits, and time-variant nonlinear circuits such as switching mode circuits.     

The novel resonant DC link three-level soft-switching inverter

ABSTRACT

In the paper, the novel topology of the resonant DC link three-level soft-switching inverter is proposed to reduce switching losses and improve the efficiency of three-level inverter at high switching frequency. Symmetrical auxiliary resonant circuits are set in the DC link of three-level hard-switching inverter. Moreover, the terminal voltage of the resonant capacitors between the DC buses periodically drops to zero via the resonance of auxiliary circuits. Furthermore, under such condition, the main switches of the three-level inverter would be operated, in order to achieve zero-voltage switching. Based on the equivalent circuits in different operating modes, the paper analyses the working process of the soft-switching inverter in detail. In addition, a 3 kW laboratory prototype of resonant DC link three-phase three-level soft-switching inverter is built. The experimental results show that the main switches and auxiliary switches of the inverter are operated under soft-switching conditions, and the efficiency is significantly improved compared with the three-level hard-switching inverter. Therefore, the proposed topology can effectively reduce switching losses and prove to be more practical in engineering.     

Analysis of the conditions for the worst case switching activity in integrated circuits

Relentless advances in IC technologies have fueled steady increases on fabricated component density and working frequencies. As feature sizes decrease to nanometer scales, an increase in switching activity per unit of area and time is observed. When extreme switching activity occurs in a small region of an integrated circuit, malfunctions may be triggered that compromise behavior. This can be either a consequence of a decrease in bias levels in the power grid caused by IR-Drop, or due to unexpected glitching on gates’ outputs caused by ground bounce. For proper circuit verification, both conditions have to be accurately estimated and accounted for. Achieving this in an accurate manner for a large circuit is a very challenging problem. In this paper we propose and compare methods for the identification of the conditions leading to extreme situations of switching activity in integrated circuits. Our approach is based on both spatial and time partitioning which are used to address the accuracy and computational requirements. We propose a method for determining the exact conditions for worst case switching activity in a small circuit area during a short time interval. We then show how this method can be combined with partitioning to allow for accurate full circuit verification.     

Subnanosecond-transient detector using emitter-coupled logic gates

It is shown that tunnel-diode circuits can be made directly compatible with emitter-coupled logic gates. This enables the design of subnanosecond threshold switching circuits with standard logic-gate output levels to be simply achieved. The switching speed of the tunnel diode under these circuit conditions can be calculated, and suitable graphs are given.     

Low-power digital systems based on adiabatic-switching principles

Adiabatic switching is an approach to low-power digital circuits that differs fundamentally from other practical low-power techniques. When adiabatic switching is used, the signal energies stored on circuit capacitances may be recycled instead of dissipated as heat. We describe the fundamental adiabatic amplifier circuit and analyze its performance. The dissipation of the adiabatic amplifier is compared to that of conventional switching circuits, both for the case of a fixed voltage swing and the case when the voltage swing can be scaled to reduce power dissipation. We show how combinational and sequential adiabatic-switching logic circuits may be constructed and describe the timing restrictions required for adiabatic operation. Small chip-building experiments have been performed to validate the techniques and to analyse the associated circuit overhead     

Method of improving switching speed

The saturation characteristic of a switching transistor can be improved by using gold doping, buried layers, or clamp circuits. However, some important factors such as switching speed, loading capability, cost, and reliability may have to be sacrificed. The author describes a new technique to significantly improve not only the saturation characteristic, but also the switching speed by utilizing a two-collector-terminal transistor. The TCT structure and theory are presented. Results of experiments using the TCT and the conventional transistor are compared.     

Impact of Switching-Induced Electromagnetic Interference on Low-Voltage Cables in Substations

The electromagnetic environment within a substation is very complex. Substations represent an intricate interconnected collection of devices that serve as electromagnetic wave emitters and receptors. Transient electromagnetic emissions—electromagnetic interference (EMI)—are generated during the switching of disconnector and circuit breakers (CBs) that may cause malfunction or damage to electronic equipment positioned nearby if appropriate immunity measures are not taken. The interference may couple significant energy through common-mode currents to cable protection. Electromagnetic compatibility is mostly achieved by addressing the EMI victim through techniques in the secondary environment, such as shielding and filtering. This paper presents the finite-element method analysis of three methods: metallic channel, braided cable, and additional cable, used for EMI mitigation on low-voltage cables of 20 kV side in a 63-kV/20-kV substation due to switching effects of disconnector and CBs. In each method, overvoltage is considered and the results are compared with each other. A simple circuit analysis was also carried out on the causes of switching based on EMI to provide some insight into the interference mechanism during switching process, using common-mode and differential-mode equivalent circuits. The overvoltage reductions are attained through differential-mode current and shielding methods.      

Control of chaos in the boost converter

A method for controlling chaos which is particularly suitable for switching circuits is presented. The method has been successfully applied to the current-mode controlled boost converter which is a piecewise linear system with switching nonlinearity     

Precomputation-based sequential logic optimization for low power

We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. We present two different precomputation architectures which exploit this observation. The primary optimization step is the synthesis of the precomputation logic, which computes the output values for a subset of input conditions. If the output values can be precomputed, the original logic circuit can be “turned off” in the next clock cycle and will have substantially reduced switching activity. The size of the precomputation logic determines the power dissipation reduction, area increase and delay increase relative to the original circuit. Given a logic-level sequential circuit, we present an automatic method of synthesizing precomputation logic so as to achieve maximal reductions in power dissipation. We present experimental results on various sequential circuits. Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay     

Gateless synchronous counters with D flip-flops

A new approach to the state assignment problem for the synthesis of sequential switching circuits is applied to solve completely the synthesis problem of gateless counters. The necessary and sufficient condition that assures that the counter may be synthesised without gates is found. A method is developed to determine a priori if a given state table corresponds to a circuit that may be synthesised without gates.     

Testing switching networks for short-circuit faults

A significant class of faults in switching networks is due to short circuits between signal terminals. A method is proposed which tests networks for such faults, making use of algorithms developed for detecting or diagnosing stuck-at-level faults.     

Determining Multiple Steady-State ZCS Operating Points of a Switch-Mode Contactless Power Transfer System

This paper presents a new method for accurately determining all possible steady-state operating points of a switch-mode contactless power transfer (CPT) system. The method is based on a stroboscopic mapping model and accurate calculation of its fixed points corresponding to circuit zero current switching (ZCS) conditions. Four steady-state operating points are identified for, e.g., inductor–capacitor–inductor ( LCL)-type CPT system. Voltage and current waveforms and switching periods are determined. Parameter influences on ZCS periods are studied by bifurcation diagrams. Both PSpice simulation and experimental results have verified the proposed method. The results provide new opportunities for a practical CPT system to operate at different soft switching frequencies. The method is very useful for analyzing switch-mode resonant circuits and designing new power flow controllers.      

Statistical estimation of delay-dependent switching activities inembedded CMOS combinational circuits

This paper describes a new procedure to estimate the delay-dependent switching activities in CMOS combinational circuits. The procedure is based on analytic and statistical approaches to take advantage of their time-efficiency over conventional event-driven simulation tools. For this study, combinational circuits driven by discrete-time logic signals are considered. By focusing on a specific class of combinational circuits, the transitional effects can be analyzed more accurately by considering some of the delay effects neglected in previous studies, Also, to model the delay-dependent effects, statistical properties such as the pattern probability, the propagation probability, and the distribution of the propagation delay of switching activities are defined and evaluated. The simulation results on benchmark circuits indicate that the proposed procedure significantly speeds up the estimation process in comparison to the conventional event-driven simulators. The reliability issues in the aspect of switching activities are briefly discussed     

基于静态逻辑蕴涵的电路功耗优化

介绍一种针对经过工艺映射的组合逻辑电路进行功耗优化的方法.首先根据电路节点的翻转频率对节点进行分类,每次考虑一个节点,找出它在电路中的直接和间接蕴涵;然后利用这些蕴涵在电路添加一些逻辑门和连接,来增加电路的冗余;最后去除这些冗余来化简电路,去除那些高功耗的节点,从而减少整个电路的翻转活动,降低功耗.这个过程是重复的,每次重复从一个新的节点开始,最后得到一个跳变减少的电路.     

A photonic wavelength-division switching system using tunable laserdiode filters

A photonic wavelength-division switching system using semiconductor tunable wavelength filters is proposed. A switching system using wavelength switches and multistage switching networks is discussed. A crucial point in developing this switching system is to achieve a large number of wavelength-division channels. The potential of 100 wavelength-division channels in such switching systems is estimated, based on InP optical integrated circuits. A wavelength network synchronization which permits the network to utilize such a large number of wavelength-division channels without wavelength misalignment and drift is proposed. An eight-channel wavelength-division switching experiment, using phase-shift-controlled distributed feedback laser diodes as tunable wavelength filters, is reported     

基于单片机通用IO口的SPI接口模拟

IIC接口是一种同步串行通讯接口。为了扩展系统接口,有时必须要模拟出IIC串口。提出了基于TI的MSP430系列单片机利用通用I/O口软件模拟出了IIC串口的方法,提高了IIC的接口效率,简化了其使用方法,并且给出连接IIC接口的24C01型EEPROM的实例。     

Transient power supply current monitoring—A new test method for CMOS VLSI circuits

We present a new method for testing digital CMOS integrated circuits. The new method is based on the following premise: monitor the switching behavior of a circuit as opposed to the output logic state. We use the transient power supply current as a window of observability into the circuit switching behavior. A method for isolating normal switching transients from those which result from defects is introduced. The feasibility of this new testing approach is investigated by conducting several experiments involving the design of integrated circuits with built-in defects, fabrication, and physical testing. The results of these experiments show this new test method to be a promising one for detecting defects that can escape stuck-at testing andI _DDQ testing.