112-GHz collector-up Ge/GaAs heterojunction bipolar transistorswith low turn-on voltage

This paper reports small-sized collector-up Ge/Ga/As heterojunction bipolar transistors (HBT's) operating at low power and high frequency. A heavily B-doped Ge base-layer and a newly-developed self-aligned process reduce the base resistance and the parasitic elements. Intrinsic base resistance is 50 Ω/□; this is the lowest value reported for bipolar transistors. With limiting the active emitter area through B ion implantation, these collector-up HBT's with a collector size of 2×5 μm² exhibit a current gain of 60. They exhibit a maximum oscillation frequency f_max of 112 GHz with an associated current gain cutoff frequency f_T of 25 GHz. The large value of f_max, exceeding 100 GHz, is attributed to the extremely low base resistance caused by the heavily B-doped base-layer and the self-aligned process and to the low base-collector capacitance expected from the collector-up structure. The turn-on voltage of these HBT's is approximately 0.7 V smaller than that of AlGaAs/GaAs HBT's. These results show that these HBT's have excellent potential for low-power dissipation circuits     

A high-speed bipolar technology featuring self-aligned single-polybase and submicrometer emitter contacts

An experimental bipolar transistor structure with self-aligned base-emitter contacts formed using one polysilicon layer is presented with geometries and frequency performance comparable to those of double-polysilicon structures. This structure, called STRIPE (self-aligned trench-isolated polysilicon electrodes), provides a 0.2-μm emitter-base polysilicon contact separation. A 0.4-μm emitter width is achieved with conventional 0.8-μm optical lithography. Scaling of the emitter width of 0.3 μm has been performed with minimal degradation of device performance, and scaling of the emitter width pattern to 0.2 μm has been demonstrated. These dimensions are the smallest achieved in single-polysilicon structures with polysilicon base contacts and are comparable to those achieved in double-polysilicon structures. The STRIPE structure has been used to fabricate transistors with f_t as high as 33.8 GHz     

GaInP/GaAs double heterojunction bipolar transistor with highfT, fmax, and breakdown voltage

We report on the dc and microwave performance of an MOCVD-grown carbon-doped GaInP/GaAs double heterojunction bipolar transistor (DHBT) with a thin highly doped n-type GaInP layer in the collector. The DHBT showed improved current-voltage characteristics at low collector-emitter bias compared with those of a DHBT without the heavily doped GaInP layer, while maintaining a high breakdown voltage (BV_CEO~20 V). Small area, self-aligned emitter transistors with two 2×5 μm² emitter fingers were fabricated and exhibited f_T and f_max of 53 GHz and 75 GHz, respectively. These results indicate the promise of carbon-doped base GaInP/GaAs DHBT's for high-power microwave applications     

A vertically isolated self-aligned transistor—VIST

A vertically isolated self-aligned transistor (VIST) has been developed to make possible high-speed low-power dissipation bipolar devices suitable for LSI. This VIST consists of a bird's beak free oxide isolated structure and a high impurity density inactive base self-aligned to the polysilicon emitter. A flat emitter transistor with a self-aligned base is developed by forming an inactive high impurity density base region with an ion-implantation method using a polysilicon emitter as a mask. The transistors exhibit uniform current gain even to current levels as low as 10^-8A. The ftvalue of this transistor is 6 GHz. The ring oscillators and counter are fabricated using the 13 × 6 µm²transistor cell. The power and delay product is 0.12 pJ.     

Self-aligned complementary bipolar transistors fabricated with a selective-oxidation mask

This paper deals with a self-aligned complementary transistor (vertical n-p-n and vertical p-n-p) structure that is ideal for high-speed and high-accuracy analog bipolar LSI circuits. The device structure consists of a 2-µm epitaxial layer, a non-LOCOS trench isolation buried with polysilicon, and complementary transistors, which are characterized by self-aligned active base and emitter. The key feature lies in the fabrication process, which forms an active base and emitter by ion implantations through a silicon nitride film by the use of an oxidation film that covers an extrinsic base as a mask [1]. The leakage current at the emitter-base junction can be minimized, because the ion-implantation-induced residual defects are confined in the emitter and the extrinsic base regions. The current gains of both transistors (n-p-n and p-n-p) remain constant down to a collector current of Ic= 10^-9A. The typical distribution of the base-emitter offsets (ΔVBE) of transistor pairs was 0.2 mV as expressed in the standard deviation = 3σ. The maximum values of fTfor n-p-n and p-n-p transistors are 6 and 1.5 GHz, respectively.     

High frequency performance of SiC heterojunction bipolartransistors

A compact heterojunction bipolar transistor (HBT) model was employed to simulate the high frequency and high power performances of SiC-based bipolar transistors. Potential 6H-SiC/3C-SiC heterojunction bipolar transistors (6H/3C-HBT's) at case temperatures of 27°C (300 K) through 600°C (873 K) were investigated. The high frequency and high power performance was compared to AlGaAs/GaAs HBT's. As expected, the ohmic contact resistance limits the high frequency performance of the SiC HBT. At the present time, it is only possible to reliably produce 1×10^-4 Ω-cm² contact resistances on SiC, so an f_T of 4.4 GHz and an f_max of 3.2 GHz are the highest realistic values. However, assuming an incredibly low 1×10^-6 Ω-cm² contact resistance for the emitter, base, and collector terminals, an f_T of 31.1 GHz and an f_max of 12.7 GHz can be obtained for a 6H/3C-SiC HBT     

High-speed, low-noise InGaP/GaAs heterojunction bipolar transistors

We have demonstrated self-aligned InGaP/GaAs heterojunction bipolar transistors (HBT's) with excellent dc, microwave, and noise performance. A 3×10 μm² emitter finger device achieved a cutoff frequency of f_T=66 GHz and a maximum frequency of oscillation of f_max=109 GHz. A minimum noise figure of 1.12 dB and an associated gain of 11 dB were measured at 4 GHz. These results are the highest combined f_T+f_max and the lowest noise figure reported for an InGaP/GaAs HBT and are attributed to material quality and the use of self-aligned base contacts. These data clearly demonstrate the viability of InGaP/GaAs HBT's for high-speed, low-noise circuit applications     

A 277-GHz fmax transferred-substrate heterojunctionbipolar transistor

We report a AlInAs-GaInAs transferred-substrate heterojunction bipolar transistor (HBT). The transferred-substrate process permits fabrication of narrow and aligned collector-base and emitter-base junctions, reducing the collector-base capacitance and increasing the device f_max. A device with aligned 0.7-μm emitter and 1.6-μm collector stripes has extrapolated 277 GHz f_max and 127 GHz f_τ, respectively     

Visualizing the doping profile of a silicon germanium HBT with polysilicon emitter using electron holography

Modern bipolar transistors use polysilicon emitters and an epitaxial grown silicon germanium (SiGe) base. For device optimization, both the SiGe base and the region of the diffused emitter is of special interest. In this paper, electron holography is applied to visualize and directly measure the two-dimensional distribution of the local potential in a high-performance SiGe heterojunction bipolar transistor. Special emphasis is put on investigating the region of the emitter diffused into the epitaxially grown base layer. In addition, we investigate the self-aligned base-link construction. We compare electron holographic measurements of the whole transistor to secondary ion mass spectrometric (SIMS) data and discuss the results.     

High-speed InGaP/GaAs HBTs with a strained InxGa1-xAs base

A self-aligned InGaP/GaAs heterojunction bipolar transistor with a compositionally graded In_xGa_1-xAs base has been demonstrated with f_T=83 GHz and f_max=197 GHz. To our knowledge, these results are the highest reported for both parameters in InGaP/GaAs HBT's. The graded base, which improves electron transport through the base, results in a DC current gain and a cutoff frequency which are 100% and 20% higher, respectively, than that achieved by an identical device with a nongraded base. The high f_max results from a heavily doped base, self-aligned base contacts, and a self-aligned collector etch. These results demonstrate the applicability of InGaP/GaAs HBT's in high-speed microwave applications     

Measurement of collector and emitter resistances in bipolartransistors

New DC methods to measure the collector resistance R_C and emitter resistance R_E are presented. These methods are based on monitoring the substrate current of the parasitic vertical p-n-p transistor linked with the n-p-n intrinsic transistor. The p-n-p transistor is operated with either the bottom substrate-collector or the top base-collector p-n junction forward-biased. This allows for a separation of the various components of R_C. R_E is obtained from the measured lateral portion of R_C and the collector-emitter saturation voltage. Examples of measurements on advanced self-aligned transistors with polysilicon contacts are shown. The results show a very strong dependence of R_C on the base-emitter and base-collector voltages of the n-p-n transistor. The bias dependence of R_C is due to the conductivity modulation of the epitaxial collector. From the measured emitter resistance R_E a value for the specific contact resistance for the polysilicon emitter contact of ρ_c≅50 Ω-μm² is obtained     

Process and device performance of a high-speed double poly-Sibipolar technology using borosenic-poly process with coupling-baseimplant

Use of boron and arsenic diffusions through an emitter polysilicon film (borosenic-poly emitter-base process) produces a transistor base width of less than 100nm with an emitter junction depth of 50 nm and an emitter-to-base reverse leakage current of approximately 70 pA. The borosenic-poly process resolves both the channeling and shadowing effects of a sidewall-oxided spacer during the base boron implantation. The process also minimizes crystal defects generated during the emitter and base implantations. The coupling-base boron implant significantly improves a wide variation in the emitter-to-collector periphery punchthrough voltage without degrading the emitter-to-base breakdown voltage current gain, cutoff frequency, or ECL gate delay time. A deep trench isolation with 4-μm depth and 1.2-μm width reduces the collector-to-substrate capacitance to 9 fF, while maintaining a transistor-to-transistor isolation voltage of greater than 25 V. The application of self-aligned titanium silicide technology to form polysilicon resistors without holes and to reduce the sheet resistance of the emitter and collector polysilicon electrodes to 1 Ω/square is discussed     

A selective-epitaxial-growth SiGe-base HBT with SMI electrodesfeaturing 9.3-ps ECL-gate delay

An ultra-high-speed selective-epitaxial-growth SiGe-base heterojunction bipolar transistor (HBT) with self-aligned stacked metal/in-situ doped poly-Si (IDP) (referred to as SMI) electrodes is developed. A 0.5-μm-wide SiGe base self-aligned to the 0.1-μm-wide emitter was selectively grown by using a UHV/CVD system. This self-aligned structure effectively reduces collector capacitance. In SMI technology, a tungsten film is selectively stacked on all poly-Si electrodes (base, emitter, and collector) in a self-aligned manner by using selective deposition without any heat treatment. So this technology does not cause unwanted diffusion of the base dopants and keeps a shallow intrinsic base profile. SMI technology can therefore provide low parasitic resistances and is well-suited to an SiGe-base HBT. A 2-μm-wide BPSG/SiO₂ refilled trench was introduced in order to reduce the substrate capacitance. The low dielectric constant of BPSG/SiO₂ and the wide trench are very effective in reducing the sidewall element of substrate capacitance. This technology makes it possible to obtain ultra-high-speed operation with a 9.3-ps-gate-delay emitter-coupled-logic (ECL) circuit     

Selective epitaxy base transistor (SEBT)

A bipolar transistor using selective epitaxy for base formation in a double-poly self-aligned structure is presented. The intrinsic base was formed by a selective-epitaxial deposition in place of ion implantation. Such epitaxial base processes are capable of achieving a narrow intrinsic base sheet resistance R_bi and base-emitter diffusion capacitance c_be compared to advanced ion-implanted processes. A selective epitaxial base can be simply introduced in advanced double-poly self-aligned processes compared to a nonselective epitaxial layer     

A 60-GHz fT super self-aligned selectively grownSiGe-base (SSSB) bipolar transistor with trench isolation fabricated onSOI substrate and its application to 20-Gb/s optical transmitterICs

A 60-GHz cutoff frequency (f_T) super self-aligned selectively grown SiGe-base (SSSB) bipolar technology is developed. It is applied to 20-Gb/s optical fiber transmitter ICs. Self-aligned bipolar transistors mutually isolated by using a BPSG-filled trench were fabricated on a bond-and-etchback silicon-on-insulator (SOI) substrate to reduce the collector-substrate capacitance C_CS. The SiGe base was prepared by selective epitaxial growth (SEG) technology. A 0.4-μm wide emitter was used to reduce the junction capacitances. The maximum cutoff frequency f_T and the maximum frequency of oscillation f_max were 60 and 51 GHz, respectively. By using this technology, Si-ICs for an optical transmitter system were made, such as a selector (a multiplexer without input and output retiming D-type flip-flops (D-F/Fs)), a multiplier, and a D-F/F. An internal high-speed clock buffer circuit achieves stable operation under a single clock input condition in the selector and the multiplier ICs. Their stable operation was confirmed up to 20 Gb/s. The selector IC for data multiplexing operates at over 30 Gb/s     

An advanced bipolar transistor with self-aligned ion-planted baseand W/poly emitter

The fabrication, device profile, and electrical characteristics of an advanced bipolar transistor with an LDD-like self-aligned lateral profile are discussed. An ion-implanted extrinsic base with a low sheet resistance of 55 Ω/square and a junction depth of 0.35 μm is obtained using rapid thermal annealing. The extrinsic base and emitter are separated by a temporary submicrometer sidewall spacer, which is subsequently removed to maintain a planar surface during the emitter-active-base formation process. The emitter is contacted by a W-TiN-n⁺ polysilicon stack with a sheet resistance of 1 Ω/square. As a result of the planarity of the surface during the profile formation for the active region and the decoupling of the structural process from the thin base process, an active base width of 105 nm is obtained     

High-speed performance of Si/Si1-xGexheterojunction bipolar transistors

A theoretical investigation of Si/Si_1-xGe_x heterojunction bipolar transistors (HBTs) undertaken in an attempt to determine their speed potential is discussed. The analysis is based on a compact transistor model, and devices with self-aligned geometry, including both extrinsic and intrinsic parameters, are considered. For an emitter area of 1×5 μm², an f_t of over 75 GHz and f_max of over 35 GHz were computed at a collector current density of 1×10 ⁵ A/cm² and V_CB of 5 V     

Process investigations for a 30-GHz fT submicrometerdouble poly-Si bipolar technology

Major process issues are investigated to establish a manufacturable process for a 30-GHz f_T deep-trench isolated submicrometer double polysilicon bipolar technology. A thinner deep-trench surface oxide minimizes crystal defects generated by thermal stresses during the subsequent processes, and significantly improves collector-to-emitter leakage currents in npn transistors. The effects of reactive-ion-etch (RIE) process used for the base surface oxide etch are evaluated in terms of current gain, emitter resistance, and cutoff frequency of the npn transistors. Silicon surface roughness created by an RIE process produces a nonuniform interface oxide film between the emitter polysilicon and the silicon surface, which results in a lower current gain due to a retardation of arsenic diffusion from the emitter polysilicon through the unbroken thicker portion of the interface oxide film. Lateral pnp transistors and Schottky diodes using a vanadium silicide are characterized as a function of epitaxial layer thickness. Schottky diodes are integrated with high performance npn transistors without using extra photo-masking process steps. The reverse leakage currents of Schottky diodes fabricated by using an RIE process are acceptable for practical use in circuits. A planarization process is investigated by employing an RTA reflow of BPSG films deposited in an LPCVD furnace. The maximum RTA reflow temperature is limited to 1000°C in order to maintain an acceptable integrity of TiSi₂ layer formed on top of the n+ polysilicon layer. The planarity achieved by an RTA reflow at a temperature between 975°C and 1000°C is acceptable for double polysilicon bipolar integrated circuits using metal interconnects produced by an electroplated gold process     

Submicron scaling of HBTs

The variation of heterojunction bipolar transistor (HBT) bandwidth with scaling is reviewed. High bandwidths are obtained by thinning the base and collector layers, increasing emitter current density, decreasing emitter contact resistivity, and reducing the emitter and collector junction widths. In mesa HBTs, minimum dimensions required for the base contact impose a minimum width for the collector junction, frustrating device scaling. Narrow collector junctions can be obtained by using substrate transfer or collector-undercut processes or, if contact resistivity is greatly reduced, by reducing the width of the base ohmic contacts in a mesa structure. HBTs with submicron collector junctions exhibit extremely high f_max and high gains in mm-wave ICs. Transferred-substrate HBTs have obtained 21 dB unilateral power gain at 100 GHz. If extrapolated at -20 dB/decade, the power gain cutoff frequency f_max is 1.1 THz. f_max will be less than 1 THz if unmodeled electron transport physics produce a >20 dB/decade variation in power gain at frequencies above 110 GHz. Transferred-substrate HBTs have obtained 295 GHz f_T. The substrate transfer process provides microstrip interconnects on a low-ϵ_r polymer dielectric with a electroplated gold ground plane. Important wiring parasitics, including wiring capacitance, and ground via inductance are substantially reduced. Demonstrated ICs include lumped and distributed amplifiers with bandwidths to 85 GHz and per-stage gain-bandwidth products over 400 GHz, and master-slave latches operating at 75 GHz     

SiGe drift base bipolar transistor with self-aligned selectiveCVD-tungsten electrodes

A new device and process technology is developed for high-speed SiGe epitaxial base transistors. A 60-nm SiGe epitaxial base and the selectively ion-implanted collector (SIC) structure enhance the cutoff frequency to about 40 GHz. Base resistance is minimized to 165 Ω (emitter area: 0.2×3 μm²), and an f_MAX of 37.1 GHz is achieved by employing 0.2-μm EB lithography for the emitter window, selective CVD tungsten for the base electrode and a self-aligned oxide side wall for the emitter-to-base separation. Circuit simulations predict that this device could reduce the ECL gate delay to below 20 ps