A high-performance polysilicon thin-film transistor using XeClexcimer laser crystallization of pre-patterned amorphous Si films

A high-performance polysilicon thin-film transistor (TFT) fabricated using XeCl excimer laser crystallization of pre-patterned amorphous Si films is presented. The enhanced TFT performance over previous reported results is attributed to pre-patterning before laser crystallization leading to enhanced lateral grain growth. Device performance has been systematically investigated as a function of the laser energy density, the repetition rate, and the number of laser shots. Under the optimal laser energy density, poly-Si TFT's fabricated using a simple low- temperature (⩽600°C) process have field-effect mobilities of 91 cm²/V·s (electrons) and 55 cm²/V·s (holes), and ON/OFF current ratios over 10 ⁷ at V_Ds=10 V. The excellent overall TFT performance is achieved without substrate heating during laser crystallization and without hydrogenation. The results also show that poly-Si TFT performance is not sensitive to the laser repetition rate and the number of laser shots above 10     

High field effect mobility deuterated amorphous silicon thin-filmtransistors based on the substitution of hydrogen with deuterium

The characteristics of amorphous silicon hydrogen and deuterium thin-film transistors (a-Si:H/a-Si:D TFT) were studied. The deuterated and hydrogenated amorphous silicon channels were prepared by first annealing the as-deposited a-Si:H layer at 550°C in N₂ environment to expel all the hydrogen atoms out of the films, then the D ₂ or H₂ plasma were applied to treat the amorphous silicon layers. The field effect mobility of the conventional hydrogen TFT is usually smaller than 1 cm²/V-s. It was found that substitution of hydrogen with deuterium improved the field effect mobility of the TFT. The maximum field effect mobility of a-Si:D TFT obtained from the saturation region was 1.77 cm²/V-s     

The Characteristics of New n-Type Polycrystalline Silicon Thin-Film Transistors Employing Alternating Magnetic-Field-Enhanced Rapid Thermal Annealing

We fabricated a new top-gate n-type depletion-mode polycrystalline silicon (poly-Si) thin-film transistor (TFT) employing alternating magnetic-field-enhanced rapid thermal annealing. An n⁺ amorphous silicon (n⁺ a-Si) layer was deposited to improve the contact resistance between the active Si and source/drain (S/D) metal. The proposed process was almost compatible with the widely used hydrogenated amorphous silicon (a-Si:H) TFT fabrication process. This new process offers better uniformity when compared to the conventional laser-crystallized poly-Si TFT process, because it involves nonlaser crystallization. The poly-Si TFT exhibited a threshold voltage (V_TH) of -7.99 V at a drain bias of 0.1 V, a field-effect mobility of 7.14 cm²/V ldr s, a subthreshold swing (S) of 0.68 V/dec, and an ON/OFF current ratio of 107. The diffused phosphorous ions (P⁺ ions) in the channel reduced the V_TH and increased the S value.     

Fabrication of thin film transistors by chemical mechanicalpolished polycrystalline silicon films

A top-gate p-channel polycrystalline thin film transistor (TFT) has been fabricated using the polycrystalline silicon (poly-Si) film as-deposited by ultrahigh vacuum chemical vapor deposition (UHV/CVD) and polished by chemical mechanical polishing (CMP). In this process, long-term recrystallization in channel films is not needed. A maximum field effect mobility of 58 cm²/V-s, ON/OFF current ratio of 1.1 10⁷, and threshold voltage of -0.54 V were obtained. The characteristics are not poor. In this work, therefore, we have demonstrated a new method to fabricate poly-Si TFT's     

Hydrogen dilution effect on the properties of coplanar amorphoussilicon thin-film transistors fabricated by inductively-coupled plasmaCVD

The electrical and optical properties of the hydrogenated amorphous silicon (a-Si:H) films deposited by inductively-coupled plasma (ICP) chemical vapor deposition (CVD) with a variation of H₂ flow rate have been studied. The photosensitivity of a-Si:H is ~10⁷ when the H₂/SiH₄ ratio is between 3 and 8. With increasing H₂/SiH₄, the SiH₂ mode infrared absorption has a minimum at a H₂/SiH₄ ratio of 8. Coplanar a-Si:H thin-film transistors (TFT's) were fabricated using a triple layer of thin a-Si:H, silicon-nitride, and a-Si:H deposited by ICP-CVD using ion doping and low resistivity Ni silicide. After patterning the thin a-Si:H/silicon-nitride layers on the channel region, the gate and source/drain regions were ion-doped and then heated at 230°C to form Ni silicide layers. The low resistive Ni silicide formed on the a-Si:H reduces the offset length between gate and source/drain, leads to a coplanar a-Si:H TFT. The TFT exhibited a field effect mobility of 0.6 cm²/Vs and a threshold voltage of 2.3 V at the H₂/SiH₄ ratio of 8. The effect of H₂ dilution in SiH₄ on the coplanar a-Si:H TFT performance has been investigated. We found that the performance of the TFT is the best when the SiH₂ mode density in a-Si:H is the minimum. The coplanar TFT is very suitable for large-area, high density TFT displays because of its low parasitic capacitance between gate and source/drain contacts     

Effects of NH3 plasma passivation on N-channelpolycrystalline silicon thin-film transistors

The NH₃-plasma passivation has been performed on polycrystalline silicon (poly-Si) thin-film transistors (TFT's), It is found that the TFT's after the NH₃-plasma passivation achieve better device performance, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 10⁸, and also better hot-carrier reliability than the H₂-plasma devices. Based on optical emission spectroscopy (OES) and secondary ion mass spectroscopy (SIMS) analysis, these improvements were attributed to not only the hydrogen passivation of the defect states, but also the nitrogen pile-up at SiO₂/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films. Furthermore, the gate-oxide leakage current significantly decreases and the oxide breakdown voltage slightly increases after applying NH₃-plasma treatment. This novel process is of potential use for the fabrication of TFT/LCD's and TFT/SRAM's     

Development of high-performance polycrystalline silicon thin-filmtransistors (TFTs) using defect control process technologies

High-performance polycrystalline Si (poly-Si) thin-film transistors (TFTs) were successfully fabricated on a glass substrate below 425°C by introducing defect control process technologies. The defects in the laser crystallized poly-Si films were terminated by an oxygen plasma treatment to the film and the defects at the SiO₂ /Si interface were controlled by a gate SiO₂ film formation using electron cyclotron resonance (ECR) plasma enhanced chemical vapor deposition (PECVD). As a result, high n-channel mobility of 309 cm²V^-1s^-1, low threshold voltage of 1.12 V and low subthreshold swing of 250 mV/decade were obtained. In addition, it was demonstrated that the defect control process is quite effective to minimize the variation of TFT characteristics     

Fully self-aligned tri-layer a-Si:H thin-film transistors withdeposited doped contact layer

We demonstrate a new self-aligned TFT process for hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs). Two backside exposure photolithography steps are used to fabricate fully self-aligned tri-layer TFTs with deposited n⁺ contacts. Since no critical data alignment is required, this simple process is well suited to fabrication of short channel TFTs. We have fabricated fully self-aligned tri-layer a-Si:H TFTs with excellent device performance, and contact overlaps <1 μm. For a 20-μm channel length TFT with an a-Si:H thickness of 13 nm, the linear region (V_DS=0.1 V) and saturation region (V_DS=25 V) extrinsic mobility values are both 1.2 cm²/V-s, the off currents are <1 pA, and the on/off current ratio is >10⁷     

Dependence of thin film transistor characteristics on thedeposition conditions of silicon nitride and amorphous silicon

The systematic relation between thin film transistors' (TFT's) characteristics and the deposition conditions of amorphous silicon nitride (a-SiN) films and hydrogenated amorphous silicon (a-Si:H) films is investigated. It is observed that field effect mobility μ_FE and threshold voltage V_th of the TFT's strongly depend on the deposition conditions of these films. The maximum μ_FE of 0.88 cm²/V·s is obtained for the TFT of which a-SiN film is deposited at a pressure of 85 Pa. This phenomenon is due to the variation of the interface states density between a-Si:H film and a-SiN film     

High-Performance Self-Aligned Bottom-Gate Low-Temperature Poly-Silicon Thin-Film Transistors With Excimer Laser Crystallization

In this letter, high-performance bottom-gate (BG) low-temperature poly-silicon thin-film transistors (TFT) with excimer laser crystallization have been demonstrated using self-aligned (SA) backside photolithography exposure. The grains with lateral grain size of about 0.75 mum could be artificially grown in the channel region via the super-lateral-growth phenomenon fabricated by excimer laser irradiation. Consequently, SA-BG TFT with the channel length of 1 mum exhibited field-effect mobility reaching 193 cm²/V ldr s without hydrogenation, while the mobility of the conventional non-SA-BG TFT and conventional SA top-gate one were about 17.8 and 103 cm²/V ldr s, respectively. Moreover, SA-BG TFT showed higher device uniformity and wider process window owing to the homogenous lateral grains crystallized from the channel steps near the BG edges.     

Low-temperature polysilicon TFT with two-layer gate insulator usingphoto-CVD and APCVD SiO2

The performance of polysilicon thin-film transistors (TFTs) formed by a 600°C process was improved using a two-layer gate insulator of photochemical-assisted vapor deposition (photo-CVD) SiO₂ and atmospheric-pressure chemical vapor deposition (APCVD) SiO₂. The photo-CVD SiO₂, 100 Å thick, was deposited on polysilicon and followed by APCVD SiO₂ of 1000 Å thickness. The TFT had a threshold voltage of 8.3 V and a field-effect mobility of 35 cm²/V-s, which were higher than those of the conventional TFT with a single-layer gate SiO₂ of APCVD. Hydrogenation by hydrogen plasma was more effective for the new TFT than for the conventional device     

Low-temperature polycrystalline-silicon TFT on 7059 glass

A polycrystalline-silicon (poly-Si) thin-film transistor (TFT) deposited at low temperature on Corning 7059 glass is reported. It has practical applications for low-cost thin-film display and imaging electronics manufacturing. All the process steps used to fabricate the poly-Si device take place at temperatures of 550°C or less. The poly-Si films exhibit crystallite grain sizes on the order of 5000 Å, and the fabricated devices show field-effect mobilities of 10-20 cm²/V-s and threshold voltages around zero. A plasma process to form the source and drain contacts has also been developed     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

A Novel Low-Temperature Polysilicon Thin-Film Transistors With a Self-Aligned Gate and Raised Source/Drain Formed by the Damascene Process

In this letter, a novel structure of the polycrystalline silicon thin-film transistors (TFTs) with a self-aligned gate and raised source/drain (RSD) formed by the damascene process has been developed and investigated. Comparing with the conventional coplanar TFT, the proposed RSD TFT has a remarkable lower off-state current (177 to 6.29 nA), and the on/off current ratio is only slightly decreased from 1.71 times 10⁷ to 1.39 times 10⁷. Only four photomasking steps are required. This novel structure is an excellent candidate for further high-performance large-area device applications.     

Defect Passivation by Selenium-Ion Implantation for Poly-Si Thin Film Transistors

Low-dose (10¹³ cm^-2) selenium-ion implantation prior to pulsed-excimer-laser crystallization is investigated as a low-thermal-budget defect-passivation technique for polycrystalline silicon TFTs. Selenium defect passivation is found to be effective for improving TFT performance and for providing superior TFT reliability as compared with hydrogenation. Ion implantation, passivation, polycrystalline silicon (poly-Si), selenium (Se), thin-film transistor (TFT).     

KrF excimer laser annealed TFT with very high field-effect mobilityof 329 cm2/V-s

A thin-film transistor (TFT) with a maximum field-effect mobility of 320 cm²/V-s, an on/off current ratio of 7.6×10⁷ , a threshold voltage of 6.7 V and a subthreshold slope of 0.37 V/decade was fabricated by using pulse laser annealing processes. Amorphous silicon films (a-Si:H) with a very low impurity concentration of 4×10¹⁸ cm^-3 for oxygen, 1.5×10¹⁸ cm^-3 for carbon, and 2×10¹⁷ cm^-3 for nitrogen were deposited by a plasma chemical vapor deposition (CVD) method and annealed by KrF excimer laser (wavelength of 248 nm). The Raman spectroscopy technique was a useful tool for optimizing laser annealing conditions. Experimental results show that two factors are very important for fabricating very-high mobility TFTs: (1) utilizing high-purity as-deposited a-Si:H film; and (2) performing whole laser annealing processes sequentially in a vacuum container and optimizing illumination conditions     

A new process of fabricating inverted-staggered tri-layer thin-filmtransistors

A new method of fabricating a-Si:H TFT with etching-stop structure has been proposed. Only one plasma-enhanced chemical vapor deposition is required in this new method and a PH₃/H₂ plasma treatment during the deposition has been used to form the TFT contact and thus saved another plasma deposition. With this method, a TFT of 500 Å active layer has been fabricated successfully. The drain current and saturation mobility of this device is 2.4×10^-7 A and 0.1 cm²/V sec, respectively, which is comparable to the conventional fabricating method. The plasma treatment will also form an additional leakage path on the TFT top surface and increase the TFT subthreshold slope. However, a current of less than 1 pA at V_G=-2.4 V can still be obtained. The possible mechanism of the contact formation by the plasma treatment is also discussed     

The impact of oxidation of channel polysilicon on the trap-densityof submicron bottom-gate TFT's

Oxidation of channel polysilicon improves characteristics of narrow channel TFT's, especially in leakage current. Small leakage current of less than -20 fA/μm and high on/off ratio of about 7 orders of magnitude at a drain voltage of -3.3 V have been achieved by this method. By the analysis of trap densities, leakage current reduction in the oxidized TFT is attributed to the oxidation encroachment under the channel polysilicon which results in a decrease of interface-state density from 5×10¹¹/cm² to about 10¹⁰/cm² at both gate side and back side of the channel polysilicon. It is pointed out that interface state is in some cases more responsible for device degradation than bulk traps and that the reduction of interface states is indispensable to improving device characteristics. This method is directly applicable to TFT load SRAM's in which TFT width is less than 0.5 μm     

Copper gate hydrogenated amorphous silicon TFT with thin bufferlayers

We demonstrated a Cu gate hydrogenated amorphous silicon thin-film transistor (TFT) with buffer layers. We introduced an AlN/Cu/Al₂ O₃ multilayer for a gate of an a-Si:H TFT. The Al₂ O₃ improves the adhesion to glass substrate and AlN protect the Cu diffusion to the TFT and plasma damage to Cu during plasma enhanced chemical vapor deposition of silicon-nitride. An a-Si:H TFT with a Cu gate exhibited a field effect mobility of 1.18 cm² V/s, a gate voltage swing of 0.87 V/dec., and a threshold voltage of 3.5 V     

Short-channel amorphous-silicon thin-film transistors

Amorphous-silicon thin film transistors (TFTs) with submicrometer-long bottom-gate have been fabricated and their characteristics were evaluated. By the desirable effects of highly conductive source and drain of excimer-laser crystallized Si film, the mobility was hardly decreased from about 1.0 cm²/Vs for the 15-μm long TFT to about 0.9 cm²/Vs for the 0.5-μm long TFT. Detailed effects of the gate electrode thickness and length have been discussed on the TFT characteristics