共查询到20条相似文献,搜索用时 31 毫秒
1.
A technique to extract the off-state floating-body (FB) voltage of silicon-on-insulator (SOI) CMOS devices is presented. The bias dependent S-parameter measurements of a single standard FB SOI device and its equivalent circuit, along with the capacitance-voltage (C-V) measurements between the drain and source of the same device, are used to determine the FB voltage. No special test structure design is needed. The technique proposes a method for the extraction of the parasitic source, drain, and gate resistances. Using the technique, FB voltage in excess of 0.4 V is measured in a partially depicted (PD) NMOS device at drain voltage of 2.5 V and zero gate voltage 相似文献
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Somerville M.H. Blanchard R. del Alamo J.A. Duh G. Chao P.C. 《Electron Device Letters, IEEE》1998,19(11):405-407
We present a new simple three-terminal technique for measuring the on-state breakdown voltage in HEMTs. The gate current extraction technique involves grounding the source, and extracting a constant current from the gate. The drain current is then ramped from the off-state to the on-state, and the locus of drain voltage is measured. This locus of drain current versus drain voltage provides a simple, unambiguous definition of the on-state breakdown voltage which is consistent with the accepted definition of off-state breakdown. The technique is relatively safe and repeatable so that temperature dependent measurements of on-state breakdown can be carried out. This helps illuminate the physics of both off-state and on-state breakdown 相似文献
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基于绝缘体上硅技术,提出并研制动态阈值nMOSFETs结构.阐述了动态阈值nMOSFETs的工作原理.动态阈值nMOSFETs的阈值电压从VBS=0 V时的580 mV动态变化到VBS=0.6 V时的220 mV,但是这种优势并没有以增加漏电流为代价.因此动态阈值nMOSFETs的驱动能力较之浮体nMOSFETs在低压情况下,更具有优势.工作电压为0.6 V时,动态阈值nMOSFETs的驱动能力是浮体的25.5倍,0.7 V时为12倍.而且浮体nMOSFETs中的浮体效应,诸如Kink效应,反常亚阈值斜率和击穿电压降低等,均被动态阈值nMOSFETs结构有效抑制. 相似文献
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《Electron Devices, IEEE Transactions on》1986,33(12):1953-1955
The j-MOS transistor reported earlier has now been fabricated in silicon-on-insulator (SOI) prepared by oxygen ion implantation. Significant improvements in the drain breakdown voltage and off-state leakage current are attributed to a contoured gate oxide and to the quality of the SOI structure, respectively. The electron mobility in the channel silicon is 910 cm2/V . s and the minority-carrier lifetime is 3 µs. We conclude that the j-MOS transistor in SOI shows promise for controlling moderate power loads, particularly in dielectrically isolated power integrated circuit applications. 相似文献
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The gate-induced-drain-leakage (GIDL) currents in thin-film SOI/NMOSFET's have been studied before and after front-channel hot-carrier stress. Both the normal-mode stress (with the front gate biased beyond the threshold voltage and the drain biased at a high positive voltage, while the source is grounded with the back gate) and the reverse-mode stress (with the source and drain interchanged) have been investigated. The following significant changes have been observed: i) an increase of the off-state drain GIDL current after the normal-mode stress, especially in the low gate field region, and ii) a decrease of the off-state GIDL current after the reverse-mode stress, especially in the high gate field region. These changes can be attributed to the hot-carrier induced interface traps and their effects on the parasitic bipolar transistor gain in the thin-film SOI/NMOSFET 相似文献
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Off-state modulation of the floating-body potential in partially depleted silicon-on-insulator (PDSOI) transistors from the 90-nm technology generation is observed using pulsed current-voltage (I-V) measurements. Varying the off-value of the gate voltage is shown to either decrease the transient on-current (I/sub on,trans/) of PDSOI devices through gate-to-body leakage or increase I/sub on,trans/ due to gate-induced drain leakage. Dependence of I/sub on,trans/ on off-state gate bias is not observed in bulk devices, PDSOI devices with body contacts, or fully depleted SOI devices, confirming the role of floating-body in the observed effects. Thus, off-state conditions should be accounted for when considering floating-body effects and when using pulsed I-V measurements to study self-heating. 相似文献
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Chen J. Solomon R. Chan T.-Y. Ko P.K. Hu C. 《Electron Devices, IEEE Transactions on》1992,39(10):2346-2353
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A sub-micron poly-Si TFT device, operating at a drain bias of 1.5 V, has been studied with respect to channel layer thickness. A thinner channel layer may lead to better good gate control over the entire channel region, thus resulting in a lower threshold voltage. Similarly, under negative gate bias, a thinner channel layer would sustain larger vertical electric field. However, a thinned channel layer can reduce the source/drain bulk punch-through, thus causing a smaller channel region with relatively high electric field for carrier field emission. With using a low drain bias of 1.5 V, for the poly-Si TFT device with a thinner channel layer, the leakage current would be more effectively suppressed by the resultantly smaller channel region with relatively high electric field for carrier field emission. As a result, even for a gate length of 0.5 μm, the poly-Si TFT device with 20-nm channel layer can cause an off-state leakage of about 0.1 pA/μm at a drain bias of 1.5 V, and an on/off current ratio higher than 8 orders can be achieved. 相似文献
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The measurement of anomalous hot-carrier damage in thin-film n-channel SOI MOSFETs is reported. Due to the presence of a parasitic bipolar transistor between the source and drain, the minimum drain voltage for breakdown in these devices occurs when the device is biased in subthreshold. Using charge-pumping measurements, it is shown that if the device is biased in this regime, where single-transistor latch occurs, hot holes are injected into the gate oxide near the drain. Consequently, the maximum allowable drain voltage for these devices is governed by the parasitic bipolar properties of the SOI MOSFET 相似文献
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This work examines different components of leakage current in scaled n-MOSFET's with ultrathin gate oxides (1.4-2.0 nm). Both gate direct tunneling and drain leakage currents are studied by theoretical modeling and experiments, and their effects on the drain current are investigated and compared. It concludes that the source and drain extension to the gate overlap regions have strong effects on device performance in terms of gate tunneling and off-state drain currents 相似文献
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A technique is developed to measure silicon-on-insulator (SOI) silicon device film thickness using a MOSFET. The method is based on CV measurements between gate and source/drain at two different back-gate voltages. The SOI devices used in this study were n+ polysilicon gate n-channel MOSFETs fabricated with modified submicrometer CMOS technology on SIMOX (separation by implanted oxygen) wafers. The SIMOX wafers were implanted with a high dose of oxygen ions (1018 cm-2) at 200 keV and subsequently annealed at 1230°C. The NMOS threshold boron implant dose is 2×1012 cm-2. This method is simple, nondestructive, and no special test structure is needed. Using this technique, SOI film thickness mapping was made on a finished wafer and a thickness variation of ±150 Å was found 相似文献
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Shing-Hwa Renn Rauly E. Pelloie J.-L. Balestra F. 《Electron Devices, IEEE Transactions on》1998,45(5):1140-1146
Hot-carrier effects (HCE) induced by the parasitic bipolar transistor (PBT) action are thoroughly investigated in deep submicron N-channel SOI MOSFETs for a wide range of temperature and gate length. A multistage device degradation is highlighted for all the experimental conditions. Original Vt variations are also obtained for short-channel devices, a reduction of the threshold voltage being observed for intermediate values of stress time in the case of high stress drain biases. At low temperature (LT), an improvement of the device aging can be obtained in the low Vd range because of the significant reduction of the leakage current in the PBT regime. However, in the case of high Vd, since the strong leakage current cannot be suppressed at LT, the device aging is larger than that obtained at room temperature. On the other hand, the device lifetime in off-state operation is carefully predicted as a function of gate length with various methods. Numerical simulations are also used in order to propose optimized silicon-on-insulator (SOI) architectures for alleviating the PBT action and improving the device performance and reliability 相似文献
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Jong-Ho Lee Hyung-Cheol Shin Jong-June Kim Choon-Bae Park Young-June Park 《Electron Device Letters, IEEE》1997,18(5):184-186
A new SOI NMOSFET with a “LOCOS-like” shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, we developed a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3 μm SOI devices with Vz of 0.773 V and Tox=7.6 nm is 360 μA/μm at VGS=3.5 V and V DS=2.5 V. Improved breakdown characteristics were obtained and the BVDSS (the drain voltage for 1 nA/μm of ID at TGS=0 V) of the device with Leff=0.3 μm under the floating body condition was as high as 3.7 V 相似文献
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《Microelectronics Reliability》2015,55(2):347-351
The leakage current suppression mechanism in AlGaN/GaN High Electron Mobility Transistors (HEMTs) is investigated. It is known that leakage current can cause severe reliability problems for HEMT devices and conventional AlGaN/GaN HEMT devices suffer from detrimental off-state drain leakage current issues, especially under high off-state drain bias. Therefore, a leakage current suppression technique featuring hybrid-Schottky/ohmic-drain contact is discussed. Through the 2-zones leakage current suppression mechanism by the hybrid-Schottky/drain metal including the shielding effect of the rough ohmic-drain metal morphology and the drain side electric field modulation, AlGaN/GaN HEMT featuring this novel technique can significantly enhance the leakage current suppression capability and improve the breakdown voltage. An analytical method using loop-voltage-scanning is proposed to illustrate the optimization procedure of the hybrid-Schottky/ohmic drain metallization on leakage current suppression. Through the comparison of the loop leakage current hysteresis of conventional ohmic drain HEMT and hybrid-Schottky/ohmic drain, the leakage current suppression mechanism is verified through the leakage current considering surface acceptor-like trap charging/discharging model. Device featuring the hybrid-Schottky/ohmic drain technique shows an improvement in breakdown voltage from 450 V (with no Schottky drain metal) to 855 V with a total drift region length of 9 μm, indicating enhanced off-state reliability characteristics for the AlGaN/GaN HEMT devices. 相似文献
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Ali A. Orouji 《Microelectronic Engineering》2006,83(3):409-414
In this paper, we present the unique features exhibited by a novel double gate MOSFET in which the front gate consists of two side gates as an extension of the source/drain. The asymmetrical side gates are used to induce extremely shallow source/drain regions on either side of the main gate. Using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing and the hot carrier effect. Based on our simulation results, we demonstrate that the proposed symmetrical double gate SOI MOSFET with asymmetrical side gates for the induced source/drain is far superior in terms of controlling the short-channel effects when compared to the conventional symmetrical double gate SOI MOSFET. We show that when the side gate length is equal to the main gate length, the device can be operated in an optimal condition in terms of threshold voltage roll-off and hot carrier effect. We further show that in the proposed structure the threshold voltage of the device is nearly independent of the side gate bias variation. 相似文献
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Off-state breakdown in power pHEMTs: the impact of the source 总被引:1,自引:0,他引:1
Somerville M.H. Del Alamo J.A. Saunier P. 《Electron Devices, IEEE Transactions on》1998,45(9):1883-1889
Conventional wisdom suggests that in pseudomorphic high electron mobility transistors (pHEMTs), the field between the drain and the gate determines off-state breakdown, and that the drain to gate voltage therefore sets the breakdown voltage of the device. Thus, the two terminal breakdown voltage is a widely used figure of merit, and most models for breakdown focus on the depletion region in the gate-drain gap, while altogether ignoring the source. We present extensive new measurements and simulations that demonstrate that for power pHEMTs, the electrostatic interaction of the source seriously degrades the device's gate-drain breakdown. We identify the key aspect ratio that controls the effect, LG:xD where LG is the gate length and xD is the depletion region length on the drain. This work establishes that the design of the source must be taken into consideration in the engineering of high-power pHEMT's 相似文献
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Kyung Wook Kim Kyu Sik Cho Jin Jang 《Electron Device Letters, IEEE》1999,20(11):560-562
We have developed a novel, low off-state leakage current polycrystalline silicon (poly-Si) thin-film transistor (TFT) by introducing a very thin hydrogenated amorphous silicon (a-Si:H) buffer on the poly-Si active layer. The a-Si:H buffer is formed on the whole poly-Si and thus no additional mask step is needed. With an a-Si:H buffer on poly-Si, the off-state leakage current of a coplanar TFT is remarkably reduced, while the reduction of the on-state current is relatively small. The poly-Si TFT with an a-Si:H buffer exhibited a field effect mobility of 12 cm2/Vs and an off-state leakage current of 3 fA/μm at the drain voltage of 1 V and the gate voltage of -5 V 相似文献