3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay

We show empirical results that demonstrate the effect of high performance SiGe HBT design parameters on the minimum gate delay of an ECL ring oscillator. SiGe HBT devices with a high f/sub MAX/ (338 GHz) and a low f/sub T/ (180 GHz) achieve a minimum delay of 3.9 ps, which to our knowledge is the lowest reported delay for a silicon based logic gate. Compared to the extracted (extrapolated) f/sub T/ and f/sub MAX/, a simple figure of merit proportional to /spl radic/f/sub T//R/sub B/C/sub CB/ with R/sub B/ and C/sub CB/ extracted from S-parameter measurement is best correlated to the minimum gate delay.     

Injection transistor logic (ITL): new bipolar low-power inverter

Investigates the characteristics of a new injection transistor logic (ITL) fabricated by vapour-phase epitaxy and ion implantation. The maximum current gain of the Si-ITL-inverter is about 150. The propagation delay t/sub pd/ was determined by the ring oscillator and maximum frequency method. At a power of 100 mu W per gate for this inverter, t/sub pd/ is about 500 ps and 850 ps for 60 mu W. In the high-speed ITL structure t/sub pd/ is about 300 ps for 120 mu W.<>     

High-speed frequency dividers using self-aligned AlGaAs/GaAs heterojunction bipolar transistors

A divide-by-four frequency divider and ring oscillators have been fabricated employing self-aligned AlGaAs/GaAs heterojunction bipolar transistors (HBT's). Maximum toggle frequency of 13.7 GHz and propagation delay time of 17.2 ps are achieved in ECL gate circuitry. These values are the highest and the lowest in ECL circuits and in bipolar circuits, respectively, ever reported.     

A 209 K-transistor ECL gate array with RAM

A 12 K-gate ECL gate array with 36 kbit of dedicated RAM has been developed. An ECL logic cell structure with an extra transistor buried under a V/sub cc/ power bus is proposed to implement both the logic function and a memory cell. The logic part has the capability of implementing configurable RAM with up to 5.8 kbit. By employing 0.6- mu m double-polysilicon self-aligned technology, the intrinsic gate delay is 110 ps at a power consumption of 1.8 mW/gate. The address access times of dedicated RAM and configurable RAM are 3.0 and 1.8 ns, respectively. The gate array is applied to 9 K-gate logic circuitry with 35-kbit table look-aside buffer (TLB) memory using dedicated RAM and a 16-word*18-bit register file using configurable RAM.<>     

A bipolar 18K-gate variable size cell masterslice

An emitter-coupled logic (ECL) 100K compatible 18K-gate masterslice has been developed. A variable-size-cell (VSC) approach is proposed to reduce nonutilized elements in the ECL gate array. The concept of the VSC is to implement logic circuitry not by the usual macrocells but by newly developed cellular units. The unit is constructed using three transistors and four polysilicon resistors. By utilizing 1.2-/spl mu/m salicide base contact technology, the intrinsic gate delay is 150 ps at a power consumption of 2.4 mW. A 32-bit multiplier has been implemented as an application. Compared with conventional cell structures, a 20% higher effective gate density is achieved.     

Diode-HBT-logic circuits monolithically integrable with ECl/CMLcircuits

A novel logic approach, diode-HBT logic (DHL), that is implemented with GaAlAs/GaAs HBTs and Schottky diodes to provide high-density and low-power digital circuit operation is described. This logic family was realized with the same technology used to produce emitter-coupled-logic/current-mode-logic (ECL/CML) circuits. The logic operation was demonstrated with a 19-stage ring oscillator and a frequency divider. A gate delay of 160 ps was measured with 1.1 mW of power per gate. The divider worked properly up to 6 GHz. Layouts of a DHL flip-flop and divider showed that circuit area and transistor count can be reduced by about a factor of 3, relative to ECL/CML circuits. The new logic approach allows monolithic integration of high-speed ECL/CML circuits with high-density DHL circuits with high-density DHL circuits     

Self-aligned InP DHBT with f/sub /spl tau// and f/sub max/ over 300 GHz in a new manufacturable technology

We report self-aligned indium-phosphide double-heterojunction bipolar transistor devices in a new manufacturable technology with both cutoff frequency (f/sub /spl tau//) and maximum oscillation frequency (f/sub max/) over 300 GHz and open-base breakdown voltage (BV/sub ceo/) over 4 V. Logic circuits fabricated using these devices in a production integrated-circuit process achieved a current-mode logic ring-oscillator gate delay of 1.95 ps and an emitter-coupled logic static-divider frequency of 152 GHz, both of which closely matched model-based circuit simulations.     

High-speed scaled-down self-aligned SEG SiGe HBTs

A scaled-down self-aligned selective-epitaxial-growth (SEG) SiGe HBT, structurally optimized for an emitter scaled down toward 100 nm, was developed. This SiGe HBT features a funnel-shaped emitter electrode and a narrow separation between the emitter and base electrodes. The first feature is effective for suppressing the increase of the emitter resistance, while the second one reduces the base resistance of the scaled-down emitter. The good current-voltage performance - a current gain of 500 for the SiGe HBT with an emitter area of 0.11 /spl times/ 0.34 /spl mu/m and V/sub BE/ standard deviation of less than 0.8 mV for emitter width down to about 0.13 /spl mu/m - demonstrates the applicability of this SiGe HBT with a narrow emitter. This SiGe HBT demonstrated high-speed operation: an emitter-coupled logic (ECL) gate delay of 4.8 ps and a maximum operating frequency of 81 GHz for a static frequency divider.     

Trade-offs and challenges of short channel design on millimetre-wave power performance of GaN HFETs

For the application of undoped AlGaN/GaN HFETs to Ka-band millimetre(mm)-wave high frequency power performance, the maximum frequency of oscillation, f/sub max/, was found to be seriously limited by gate resistance and output conductance with the gate length down to 0.1 /spl mu/m. This makes it difficult for devices to achieve both high f/sub T/ and f/sub max/ at the same time. However, the technology of field-plate gate, to increase device breakdown voltage, will add extra gate capacitance. It makes the optimum gate structure design more important. The influence of gate metal thickness and gate length on f/sub max/ based on the lumped small signal circuit model analysis and the possibility to obtain high f/sub T/ and f/sub max/ simultaneously for the GaN material structure is discussed for application to the Ka-band mm-wave operating system.     

Fabrication and characterization of 100-nm In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As double-gate HEMTs with two separate gate controls

In this letter, we demonstrate successful operation of 100-nm T-gates double-gate high electron mobility transistors with two separate gate controls (V/sub g1s/ /spl ne/ V/sub g2s/). These devices are fabricated by means of adhesive bonding technique using enzocyclocbutene polymer. The additional gate enables the variation of the threshold voltage V/sub th/ in a wide range from -0.68 to -0.12V while keeping high cutoff frequency f/sub t/ of about 170 GHz and high maximum oscillation frequency f/sub max/ of about 200 GHz. These devices are considered as being very effective for millimeter-wave mixing applications and are promising devices for the fabrication of velocity modulation transistor (VMT) (Sakaki et al., 1982).     

Scaling of characteristic frequencies in RF CMOS

Device simulation of the 180-, 90-, and 65-nm CMOS generations shows that in NMOSTs, the cut-off frequency f/sub T/ and the maximum oscillation frequency f/sub max/ are roughly inversely proportional to the gate length. The voltage-gain bandwidth f/sub A/ depends only weakly on the gate length. At 40-nm gate length, f/sub T/ values of 300 GHz are predicted. For small values of the drain and source contact resistance (<10/sup -8/ /spl Omega//spl middot/cm/sup 2/), f/sub T/ can only be improved by a further reduction of the gate length. The f/sub max/ values (for zero gate resistance higher than f/sub T/) degrade strongly with increasing gate resistance. Simple approximate formulas for the dependence of f/sub T/ and f/sub A/ on the contact resistances are presented.     

An analytical model for the determination of the transient responseof CML and ECL gates

In the analysis, the full-range transient response of the gate is calculated using closed-form analytical expressions. This is achieved by generalizing and improving the method used by J.M.C. Stork (IEDM Tech. Dig., p.550, 1988) for the determination of the propagation delay. The proposed model is applicable at low-level injection, unity fan-in, and unity fan-out. The delays related to the transit time, the load, and the junction capacitances are considered. For ECL gates, the emitter follower delay is also included. Various delays (risetime, propagation delay, etc.) calculated using the proposed model agree perfectly with the results of SPICE computer simulations and with the reported experimental values     

An ultra-high-speed ECL-BiCMOS technology with silicon filletself-aligned contacts

We have developed a half-micron super self-aligned BiCMOS technology for high speed application. A new SIlicon Fillet self-aligned conTact (SIFT) process is integrated in this BiCMOS technology enabling high speed performances for both CMOS and ECL bipolar circuits. In this paper, we describe the process design, device characteristics and circuit performance of this BiCMOS technology. The minimum CMOS gate delay is 38 ps on 0.5 μm gate and 50 ps on 0.6 μm gate ring oscillators at 5 V. Bipolar ECL gate delay is 24 ps on 0.6 μm emitter ring oscillators with collector current density of 40 kA/cm². A single phase decision circuit operating error free over 8 Gb/s and a static frequency divider operating at 13.5 GHz is demonstrated in our BiCMOS technology     

Characterization of CMOS Devices for VLSI

CMOS bulk and SOS technologies are discussed for VLSI with emphasis on static and dynamic characteristics of two-input NAND gates. Olpthnum performance (minimum figure of merit FM= f/sub pd/P/sub d/) is obtained for a CMOS/SOS two-input NAND gate (FO = 2, C/sub L/ = 22 fF) with an electrical channel length L = 0.75 /spl mu/m, channel width W= 5.0 /spl mu/m, and oxide thickness X/sub O/ = 450 /spl Aring/with V/sub DD/ = 3.0 V, to yield t/sub pd/ = 400 ps and P/sub d/ = 250 /spl mu/W (t/sub pd/P/sub d/ = 100 fJ) at room temperature. Bulk technology performs within a factor of 2 of SOS for t/sub pd/ and P/sub d/. CMOS technologies offer subnanosecond propagation delays, similar to ECL bipolar, at the low submilliwatt power levels of CMOS. An analytical expression for t/sub pd/ describes the performance of two-input NAND gates in terms of device modeling and fabrication parameters. Such an expression provides a hierarchal modeling approach to characterize mini-cells for VLSI.     

Bipolar high-speed low-power gates with double implanted transistors

Speed power relations oxide isolated double implanted subnanosecond gate circuits (ECL and E/SUP 2/CL) were investigated in comparison to double diffused circuits. Under optimizing aspects with respect to propagation delay, data of double implanted integrated bipolar transistors and circuit performance are given dependent on implantation parameters.     

Equivalent circuit and ECL ring oscillators of graded-bandgap base GaAs/AlGaAs HBTs

Equivalent circuit parameters of graded-bandgap base GaAs/AlGaAs heterojunction bipolar transistors are derived by analysing static and microwave characteristics. Here, the estimated base transit time of 1.4 ps indicates that the average electron velocity is enhanced under the built-in field of the graded base. Additionally, ECL ring oscillators are simulated using the obtained parameters. The simulated propagation delay time of ECL gates agrees well with an experimental result of as short as 65 ps/gate.     

Dependence of current-gain cutoff frequency on gate length in submicron GaInAs/AlInAs MODFETs

Investigates the gate length (L/sub g/) dependence of the current-gain cutoff frequency f/sub T/ in lattice-matched GaInAs/AlInAs MODFETs. The transconductance is found to be relatively insensitive to gate length in this submicron regime, while the f/sub T/ increases with decreasing gate length due to reduced capacitance as dictated by the charge control model. An effective saturation velocity of 1.3*10/sup 7/ cm/s is deduced from the f/sub T/-L/sub g/ dependence. A maximum f/sub T/ of 112 GHz is measured on an L/sub g/=0.15 mu m device, limited mainly by parasitic charge in the AlInAs.<>     

Direct-coupled transistor-transistor logic: a new high-performance LSI gate family

The direct-coupled transistor-transistor logic (DCT/SUP 2/L) family consists of a multiple-emitter AND gate and a NOR gate similar to direct-coupled transistor logic (DCTL). High speed for low power is obtained by limiting the voltage swing and using a low voltage power supply of about 2 V. Using a conservative, standard Schottky process, the DCT/SUP 2/L NOR gate has a delay of about 1 ns for 4-mW gate power. A computer-aided analysis shows that this is faster than the basic gates of emitter function logic (EFL), emitter-coupled logic (ECL), or Schottky transistor-transistor logic (T/SUP 2/L) with the same process and gate power. A comparison of actual arithmetic logic units shows that Schottky DCT/SUP 2/L is smaller and faster than ECL and Schottky T/SUP 2/L. The higher speed and density of DCT/SUP 2/L makes it a better large-scale integration (LSI) concept than the other logic families.     

547-GHz f/sub t/ In/sub 0.7/Ga/sub 0.3/As-In/sub 0.52/Al/sub 0.48/As HEMTs with reduced source and drain resistance

We fabricated 30-nm gate pseudomorphic channel In/sub 0.7/Ga/sub 0.3/As-In/sub 0.52/Al/sub 0.48/As high electron mobility transistors (HEMTs) with reduced source and drain parasitic resistances. A multilayer cap structure consisting of Si highly doped n/sup +/-InGaAs and n/sup +/-InP layers was used to reduce these resistances while enabling reproducible 30-nm gate process. The HEMTs also had a laterally scaled gate-recess that effectively enhanced electron velocity, and an adequately long gate-channel distance of 12nm to suppress gate leakage current. The transconductance (g/sub m/) reached 1.5 S/mm, and the off-state breakdown voltage (BV/sub gd/) defined at a gate current of -1 mA/mm was -3.0 V. An extremely high current gain cutoff frequency (f/sub t/) of 547 GHz and a simultaneous maximum oscillation frequency (f/sub max/) of 400 GHz were achieved: the best performance yet reported for any transistor.