分裂法与FET技术相结合的电路动态分析

提出了分裂法与FFT技术相结合的动态电路分析法。把复杂动态电路分割成若干个线性子电路和一组联络支路(线性和非线性)。在任意长时间间隔内,用多端动态电源等效替代线性子电路。在互联电路的计算中,应用了FFT技术,该方法可降低分析复杂电路的难度,提高计算效率。     

基本电子电路

TN7()1 01040601分裂法与F FT技术相结合的电路动态分析/任洪林,陈学允侯文斌(哈尔滨工业大学)办电子与信息学报一2 00123(2)一187一191提出厂分裂法与FFT技术相结合的动态电路分析法把复杂动态电路分割成若干个线性子电路和一组联络支路(线性和非线性).在任意长时间间隔内。用多端动态电源等效替代线性子电路.在互联电路的计算中,应用了F FT技术,该方法可降低分析复杂电路的难度提高计算效率.图4参2(李)可达矩阵的新求法/杨文秀严尚安,张洁曾顺鹏(后勤1-程学院)11电子科技大学学报一2以川。29(6)666-668将模糊数学求传递闭包的思想应…     

基于ARMA谐波分解和相干检测的非线性电路故障诊断

针对非线性模拟动态电路故障诊断,提出一种基于谐波分解的故障诊断方法.通过激励设计使电路响应的Volterra谱具有可分离性,通过ARMA谐波分解方法提取Voherra线性子电路响应;然后利用相干检测提取动态电路相位切片上的静态参数;最后,根据线性电路的频响叠加性原理建立故障诊断方程.仿真实例说明,该方法具有软故障、多故障诊断能力.     

关于线性电容之静态电容和动态电容作用的研究

在对由两个初始电压不为零的电容及一个电阻串联构成的一阶电路分析时,发现研究动态电路的过渡过程时要区分静态电容和动态电容,否则有可能会导致分析计算的错误。计算线性电容储存能量公式中的电容是电容元件的静态电容,初始电荷不等的两个电容元件串联时,其等效静态电容无法确定。一阶RC电路的时间常数中的电容是电容元件的动态电容或电容元件串联、并联的等效动态电容。在分析一阶电路的动态过程时要特别注意这些问题,希望引起从事电路教学工作的同行注意。     

深度饱和三极管等效电路模型分析

运用现代电子仿真实验平台和传统实际实验方法，尝试通过对共发射极放大器电路静态和动态工作参数的测量，分析深度饱和的三极管的动态等效模型。并运用三极管的动态等效模型分析，当放大器输入和输出耦合电容改变时，对输入与输出信号之间相位位移的影响，通过仿真平台和传统方法实验结果分析两者结果一致，从而进一步阐明深度饱和三极管的等效模型。     

悬浮栅结构ISFET动态特性的HSPICE仿真

通过对ISFET敏感机理的理论分析,根据表面基模型,建立了悬浮栅结构ISFET器件的HSPICE动态行为模型,对ISFET器件的动态特性进行仿真得到时间响应曲线,并探讨了薄膜等效电阻、薄膜等效电容、互连线寄生电容和寄生电阻等因素与动态特性中延迟时间和迟滞等不理想因素的关系,为ISFET/REFET差分结构集成传感器芯片设计提供理论指导。     

悬浮栅结构ISFET动态特性的HSPICE仿真

通过对ISFET敏感机理的理论分析，根据表面基模型，建立了悬浮栅结构ISFET器件的HSPICE动态行为模型，对ISFET器件的动态特性进行仿真得到时间响应曲线，并探讨了薄膜等效电阻、薄膜等效电容、互连线寄生电容和寄生电阻等因素与动态特性中延迟时间和迟滞等不理想因素的关系，为ISFET/REFET差分结构集成传感器芯片设计提供理论指导。     

悬浮栅结构ISFET动态特性的HSPICE仿真

通过对ISFET敏感机理的理论分析,根据表面基模型,建立了悬浮栅结构ISFET器件的HSPICE动态行为模型,对ISFET器件的动态特性进行仿真得到时间响应曲线,并探讨了薄膜等效电阻、薄膜等效电容、互连线寄生电容和寄生电阻等因素与动态特性中延迟时间和迟滞等不理想因素的关系,为ISFET/REFET差分结构集成传感器芯片设计提供理论指导.     

基于电压阀和电流阀模型的晶体管放大电路分析

依据已经提出的电压阀和电流阀两种非线性电路模型以及由电压阀和电流阀构造出的晶体管模型,进一步对各种晶体管放大电路进行了非线性模型等效,并在等效的模型电路基础上,研究晶体管放大电路的静态工作点计算方法、动态参数计算方法.该方法具有电路直观、概念清晰、分析计算准确等特点,而且能够判断出晶体管是否截止或饱和、动态工作范围大小等.     

一种高速低失调比较器电路设计

本文分析了两级动态比较器的瞬态特性,设计了一种高速低失调的两级动态比较器电路。相比于传统的两级动态比较器,本设计只需要单相时钟信号,通过增加第一级动态预放大电路的有效增益,既降低了比较器的延迟时间,也减小了等效输入失调电压。本设计采用90nm CMOS工艺实现,所有的分析结果都通过了仿真验证。     

Equivalent Circuit of the Bolometer Detector

A small-signal dynamic equivalent circuit is established for the output voltage of a dc-biased bolometer (barretter) detector. The circuit consists of a voltage generator /spl upsi//sub g/, whose output is an undistorted replica of the incident RF-power modulation envelope, followed by a series resistor R/sub 1/ of dynamic origin, a shunt capacitor C that represents heat storage in the bolometer wire, and a series resistor R/sub 0/ equal to the dc resistance, usually 200 ohms. The resistance R/sub 1/ is independent of signal level, and is typically about 220 ohms for an 8.75-mA bolometer and about 120 ohms for a 4.5-mA bolometer. At a modulation frequency f/sub m/ near 0 Hz, the equivalent audio source impedance of the bolometer is R/sub 1/ +R/sub 0/. The common belief that the source impedance is R/sub 0/ in the weak-signal case is, therefore, refuted. Formulas are derived giving v/sub g/ / /P/sub RF/ and R/sub 1/ as functions of basic, easily determined bolometer parameters. The time constant for open-circuit load is /spl tau//sub oc/= R/sub 1/C, where /spl tau//sub oc/ is determined best by measurement, since catalog values of /spl tau//sub oc/ often are seriously in error. The capacitance is C=/spl tau//sub oc/ / /R/sub 1/. With one type of bolometer /spl tau//sub oc/ measures about 110 /spl mu/s, while various catalogs state values of 250 to 350 /spl mu/s. The equivalent circuit is confirmed quantitatively by measurements of output voltage and source impedance versus modulation frequency.     

Direct parameter extraction of SiGe HBTs for the VBIC bipolar compact model

An improved direct parameter extraction method of SiGe heterojunction bipolar transistors (HBTs) for the vertical bipolar intercompany (VBIC)-type hybrid-/spl pi/ model is developed. All the equivalent circuit elements are extracted analytically from S-parameter data only and without any numerical optimization. The proposed technique of the parameter extraction, differing from the previous ones, focuses on correcting the pad de-embedding error for an accurate and invariant extraction of intrinsic base resistance (R/sub bi/), formulating a new parasitic substrate network, and improving the extraction procedure of transconductance (g/sub m/), dynamic base-emitter resistance (r/sub /spl pi//), and base-emitter capacitance (C/sub /spl pi//) using the accurately extracted R/sub bi/. The extracted parameters are frequency-independent and reliable due to elimination of any de-embedding errors. The agreements between the measured and model-calculated data are excellent in the frequency range of 0.2-10.2 GHz over a wide range of bias points. Therefore, we believe that the proposed extraction method is a simple and reliable routine applicable to the optimization of transistor design, process control, and the improvement of VBIC compact model, especially for SiGe HBTs.     

基于分数阶忆阻器的混沌电路分析与设计

提出了一种新型的分数阶忆阻混沌电路.首先,建立了分数阶忆阻器的数学模型,通过数值仿真验证了分数阶广义忆阻器满足忆阻器的基本特性.然后,将分数阶广义忆阻器与蔡氏振荡电路相结合,建立了一种基于分数阶广义忆阻器的混沌电路模型.通过稳定性理论,对分数阶系统的稳定性进行了分析.为了进一步研究电路参数对系统动态行为的影响,利用相位...     

Microwave Noise Characterization of GaAs MESFET's: Evaluation by On-Wafer Low-Frequency Output Noise Current Measurement

A simplified noise equivalent circuit is presented for submicron-gate-length MESFET's in the common-source configuration, consisting of five linear circuit elements: the gate-to source capacitance C/sub gs/, the total input resistance R/sub T/, the transconductance g/sub m/, the output resistance R/sub 0/, and a noise current source of spectral density S/sub io/ at the output port. All of these elements can be determined by on-wafer measurements, and the noise current can be measured at a low frequency. The minimum noise figure of the device calculated from this model, as well as the bias and frequency dependence of the noise figure, is shown to be in agreement with microwave noise figure measurements. Thus a technique has been established for determination of the minimum noise figure of a device solely by on-wafer measurements rather than by the usual microwave measurements. The proposed technique can be employed rapidly, conveniently, without the need for tuning, and at the wafer stage of device fabrication.     

基于Matlab/Simulink的SiC MOSFET建模与分析

针对现阶段SiC MOSFET建模研究无法应用在电机控制系统领域的现状,提出了一种基于Matlab/Simulink的SiC MOSFET仿真电路模型。对功率器件的动态特性和静态特性进行综合分析,采用非分段受控电流源模型模拟功率器件静态特性,具体分析SiC MOSFET的开关过程,同时采用曲线拟合的方法对影响器件开关过程的非线性电容进行表征,在Matlab/Simulink中建立SiC MOSFET等效电路模型。为了验证模型准确性,将仿真结果与数据手册中的数据进行比较分析,仿真结果表明所建模型可以较为准确地描述SiC MOSFET动、静态特性,开通时间和关断时间误差均小于7%,对比结果验证了模型的准确性和有效性。建立的模型为SiC MOSFET在电机控制策略仿真及应用领域提供了参考依据。     

Microwave analysis of AlGaAs/InGaAs HEMT using Monte Carlo simulation

The current gain of an intrinsic HEMT is determined as function of frequency using small-signal Monte Carlo simulations. The f/sub T/ obtained is in good agreement with the value derived from steady-state results by F/sub T/=g/sub m//2 pi C/sub G/. A set of Z parameters is also calculated and an equivalent circuit model is deduced.<>     

Improved noise model for MESFETs and HEMTs in lower gigahertz frequency range

A noise model based on an equivalent circuit is applied to an HEMT. Besides the frequency dependence of the most important noise parameters (F/sub min/, R/sub opt/, X/sub opt/, R/sub N/) two apparent experimental facts are explained: the limited R/sub opt/, X/sub opt/ and the increase of R/sub N/ with decreasing frequency.<>     

A better understanding of CMOS latch-up

Both lumped-element two-transistor circuit model and two-dimensional finite-element analyses are used to study the latch-up phenomena in CMOS structures. The equivalent circuit model offers a simple view on latch-up, while 2-D modeling provides more physics and quantitative understanding of latch-up. A generalized criterion for p-n-p-n latch-up is derived based on the equivalent circuit. 2-D modeling confirms the latch-up triggering condition described by the criterion. Furthermore, 2-D simulation models the entire latch-up process, including the dynamic triggering stage, and determines the intrinsic steady-state I - V characteristics of p-n-p-n devices.