An 8192-bit electrically alterable ROM employing a one-transistor cell with floating gate

Describes a fully decoded, TTL compatible, electrically alterable, 8-kbit MOS ROM using a two-level n-channel polysilicon gate process. The memory cell consists of a single transistor with stacked gate structure where the floating gate covers only one part of the channel and is extended to an erase overlap of the source diffusion region off the channel. Programming in typically 100 ms/word is achieved by injection of hot electrons from the short channel (3.5 /spl mu/m) into the floating gate. Electrical block erasure is performed by Fowler-Nordheim emission of electrons from the floating gate. To avoid excessive avalanche breakdown currents during erasure 40 nm-50 nm oxides at the erase overlap and a voltage ramp are used. The memory operates with standard voltages (/spl plusmn/5 V, +12 V), during read, program and erase operation, a single pulsed high voltage (+26 V) for programming, and an erase voltage ramp of +35 V maximum. Typical access time is 250 ns.     

Modelling of write/erase and charge retention characteristics of floating gate EEPROM devices

A theoretical model is developed to characterise the write, erase and charge retention mechanisms of floating gate EEPROM devices. The model depicts the effect of the properties of thin tunnel oxide, interpoly oxide, injector area, and programming voltage on the device performance. The effect of trapping of electrons in the thin oxide during repeated write/erase cycles is also described.     

A single transistor electrically alterable cell

A novel single transistor electrically alterable memory cell is presented. The cell is based on floating gate technology using a double diffused (DMOS) transistor. Writing into the cell is achieved through hot electron injection while erasing is performed via Fowler-Nordheim tunneling through a thin oxide (100-Å) region. The memory cell requires only one transistor because the write and erase voltages range between 15-20 and 25-30 V, respectively. The writeability of the cell is enhanced by the thin oxide region and dependent on the proximity of this region to the channel of the DMOS transistor.     

A 16K E/SUP 2/PROM employing new array architecture and designed-in reliability features

Reports on a new 200 ns highly reliable, 16384 bit (2K/spl times/8), thin oxide floating gate electrically erasable and programmable read-only memory-e/SUP 2/PROM. The part can be written and erased by tunneling of electrons to and from the floating gate within 10 ms by applying a DC signal of 21 V to V/SUB pp/ . Improved yield and performance through minimizing the thin oxide area is achieved by incorporating a single direct wafer stepper masking step to define a minimum (1.5 /spl mu/m diameter) thin oxide injecting area. A new array architecture has made it feasible to selectively erase or write a single byte. Improved reliability is achieved by incorporating an on-chip V/SUB pp/ pulse shape generator which minimizes thin oxide stress. Endurance related testing features designed into the part allow efficient endurance screening of potentially `weak' parts.     

Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure

Design theory and experimental results of the WRITE and ERASE properties of a rewritable and nonvolatile avalanche-injection-type memory are reported. The memory transistor has the stacked-gate structure of a floating gate and a control gate. The threshold-voltage shift of the transistor due to injected charge is controlled by applied potential on the control gate which reduces the avalanche breakdown voltage of the drain junction and accelerates electron injection into the floating gate. The writing time is about 20 µs for a single transistor and is less than 5 s for a fully decoded 2048-bit memory with appropriate duty cycles of programming pulses. Erasure of the memory is accomplished either by ultraviolet light irradiation onto the floating gate or by electric field emission of electrons from the floating gate to the control gate. Electrical erasing is theoretically analyzed and successfully compared with experimental results on the 2K bit memory. Memory retention is also investigated and a charge-escaping model is proposed.     

Low-level gate current injections in flash memories initiated byminority carrier collection action of floating terminals

An unintentional channel hot carrier injection phenomenon is reported for flash memory cells. The injection occurs near the source metallurgical junction during electrical erase and is caused by subthreshold leakage current between source and floating drains. This mechanism is initiated by a minority carrier population (electrons) which is generated by impact ionization around the source junction and later collected by the floating drains. Subsequently, when the floating gate potential approaches threshold voltage, these collected electrons drift from the drain toward the source. When they reach the source junction depletion region, they experience carrier multiplications and some hot carriers are injected onto the floating gate. The injected carriers can be either hot holes or hot electrons depending on the magnitude of the floating gate potential. This mechanism affects the final threshold voltage distribution of flash memories, especially when the electric field across the tunnel oxide is low     

Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell

The stacked-gate injection MOS transistor (SIMOS) uses a control gate stacked on the floating gate for selection of the cell during reading, programming, and erasure. Programming is achieved by the injection of hot electrons from the channel into the floating gate, resulting in a large upward shift in threshold voltage. In both states, operation is in the enhancement mode. Electrical erasure can be performed by injection of hot holes from an avalanche breakdown at the source-substrate junction and by Fowler-Nordheim electron injection from the floating gate to the source. Because the floating gate can be charged positively during the erasure, part of the channel is not covered by the floating gate, and in this way the enhancement mode of the SIMOS transistor after erasure is guaranteed. In a matrix array, the memory cell consists of the SIMOS transistor only. Decoders, read amplifiers, etc., can be integrated on the same substrate. Erasure can be performed as a block, or word-by-word. Different disturb effects on memory cells during programming and erasure are discussed. The cell area of the SIMOS memory is 850 µm². The photograph of a fully decoded 8192-bit SIMOS memory chip is presented.     

A source-side injection erasable programmable read-only-memory (SI-EPROM) device

A new erasable programmable read-only memory (EPROM) device with promise for low-voltage high-speed programming is described. This device is an asymmetrical n-channel stacked-gate MOSFET, with a short weak gate-control channel region introduced close to the source. At high gate bias, a strong channel electric field is created in this local region even at a relatively low drain voltage. Furthermore, the gate oxide field in this region also aids the injection of hot electrons into the floating gate. As a result, the source-side injection EPROM (SI-EPROM) has shown 10-µs programming speed at a drain voltage of 5 V.     

Atmos—An electrically reprogrammable read-only memory device

An adjustable threshold MOS (Atmos) transistor is described that can be used as an electrically reprogrammable read-only memory by changing the charge content of a floating polysilicon gate. This floating gate is charged negatively (write) by means of a nonavalanche mechanism and charged positively (erase) by the avalanche breakdown of source or drain junction and subsequent hole injection into the oxide. The write time is between 10 and 100 ms, the erase time on the order of 1 s. The charge retention of the floating gate is about 90 percent after storage for 1000 h at 125°C.     

Narrow distribution of threshold Voltage in 4-Mbit MONOS memory-cell array with F-N channel write and direct/F-N tunneling erase operation as a single transistor structure

This paper describes the narrow and nonspreading distribution of threshold voltage in metal-oxide-nitride-oxide semiconductor (MONOS) memory cell array with Fowler-Nordheim (F-N) channel write operation and direct/F-N tunneling erase operation as a single transistor structure. We fabricated a 4-Mbit MONOS memory test chip using 0.25-/spl mu/m technology. The gate length of the memory cell was shrunk to 0.18 /spl mu/m. The distribution of threshold voltage for many operations were evaluated. The range of threshold voltage distribution is small, within 0.5 V in 12-14 V for programming and -8.5 to -9 V for erasing. It was also narrow for program/erase cycles up to 10/sup 4/ and after exposure to temperatures of 300/spl deg/C for 17 h and 150/spl deg/C for 304 h. These characteristics of narrow Vth distribution represent advantages of the MONOS memory device both for nonverify operation in program/erase mode and for low supply voltage operation in read mode. Another advantage is that no anomalous leak cell or tail bit is evident in the data retention result, demonstrating high reliability. The MONOS memory device is a promising candidate for use in cheaper and more scalable gate length fabrication processes compared with floating gate for highly reliable embedded applications.     

FCAT—A low-voltage high-speed alterable n-channel nonvolatile memory device

The structure and principles of a new nonvolatile charge storage device are described. The Floating Si-gate Channel Corner Avalanche Transition (FCAT) memory device is an n-channel MOS transistor with a floating gate. The p⁺regions are placed outside the channel area by aligning them with the floating gate and are adjacent to the diffused n⁺source and/or drain regions. This device can operate in the write/erase modes under low-voltage (12 V) and high-speed (< 1 ms) conditions using only a pair of positive pulses. This is achieved with a novel avalanche transition at the channel corner through a relatively thin (4-6 nm thick) oxide under the open-drain condition.     

A high-density, high-performance EEPROM cell

The theory, design, and performance data of a new high density, high performanee EEPROM cell is described. The memory cell is fabricated using standard n-channel double-polysilicon processing together with thin-oxide technology, and has an area of 24 × 24 µm2using 4-µm design rules. The cell is of the floating gate type, and employs avalanche injection of electrons and holes from a common injector. The use of thin oxide (≃ 100 Å) between the n⁺-p⁺injector region of the substrate and the floating gate of the memory transistor makes operation possible using voltages of less than 20 V. Write and erase times are 10 ms with an endurance to write-erase cycling of 10⁵cycles. The power dissipation during writing and erasing is 10 mW.     

Observation of fast erase due to enhanced generation of holes caused by electron impact ionization

This letter describes an enhanced erase mechanism in flash memory cells due to impact ionization induced generation of holes. The increased population of holes is initiated by the impact ionization of electrons in the collector-base region of a parasitic bipolar transistor. Electrons injected from the emitter (drain) of a parasitic n-p-n bipolar transistor into the base (substrate) can drift to the collector (source) where the high electrical field in the collector-base space charge region causes impact ionization and carrier multiplication. The impact ionization generated holes that gain enough energy to overcome the oxide barrier can be injected into the floating gate, resulting a very fast erase.     

A novel P-channel nitride-trapping nonvolatile memory device with excellent reliability properties

A novel P-channel nitride trapping nonvolatile memory device is studied. The device uses a P/sup +/-poly gate to reduce gate injection during channel erase, and a relatively thick tunnel oxide (>5 nm) to prevent charge loss. The programming is carried out by low-power band-to-band tunneling induced hot-electron (BTBTHE) injection. For the erase, self-convergent channel erase is used to expel the electrons out of nitride. Experimental results show that this p-channel device is immune to read disturb due to the large potential barrier for hole tunneling. Excellent P/E cycling endurance and retention properties are demonstrated. This p-channel device shows potential for high-density NAND-type array application with high-programming throughput (>10 Mb/sec).     

A true single-transistor oxide-nitride-oxide EEPROM device

A novel single-transistor EEPROM device using single-polysilicon technology is described. This memory is programmed by channel hot-electron injection and the charges are stored in the oxide-nitride-oxide (ONO) gate dielectric. Erasing is accomplished in milliseconds by applying a positive voltage to the drain plus an optional negative voltage to the gate causing electron tunneling and/or hot-hole injection due to the deep-depletion-mode drain breakdown. Since the injection and storage of electrons and holes are confined to a short region near the drain, the part of the channel near the source maintains the original positive threshold voltage even after repeated erase operation. Therefore a select transistor, separate or integral, is not needed. Because oxide layers with a thickness larger than 60 Å are used, this device has much better data retention characteristics than conventional MNOS memory cells. This device has been successfully tested for WRITE/ERASE endurance to 10000 cycles.     

A 128 K flash EEPROM using double-polysilicon technology

An easily manufacturable 128 K flash EEPROM (electrically erasable programmable read-only memory) was developed based on a novel cell. Programming is achieved through hot-electron injection and erasing through electron tunneling from the floating gate to the drain. The cell is 20% larger than an EPROM cell and contains an integral series transistor which ensures selflimited erasing, reduces leakage, and increases the cell current. The flash EEPROM device can withstand thousands of program/erase cycles. Endurance failures are due to threshold window closing caused by electron trapping in the gate oxide. Typical erasure time is 1 s to clear the entire memory.     

Novel Single Polysilicon EEPROM Cell With Dual Work Function Floating Gate

A novel single polysilicon electrically erasable programmable read-only memory cell with dual work function floating-gate (DWFG) structure is presented in this letter. The floating gate of the proposed DWFG cell is doped with p+ on the source side and n+ on the drain side. For DWFG devices, the floating gate on the source side has a higher work function than that on the drain side. The work function difference and the intrinsic doped region at the middle of the floating-gate affect the channel potential distribution and generate a peak lateral electric field inside the channel, improving the channel's hot electron programming characteristics. The experimental results show that the proposed DWFG cell gives faster programming speeds and program operation at lower voltage than conventional cells     

Optimization of embedded compact nonvolatile memories for sub-100-nm CMOS generations

The performance of compact nonvolatile memory cells, meant for embedded applications in advanced CMOS processes, is studied and analyzed in detail by means of technology computer-aided design (TCAD), and new experimental results are presented. Improvement of the memory performance is achieved. The key element of this improvement is access gate oxide thickness reduction combined with suitable design of the channel/source/drain doping profiles. An increase of the memory readout current by a factor of two was achieved with an excellent low-leakage current level of the access gate transistor. The increase of the read current allows faster read access, while the excellent subthreshold behavior of the access gate transistor allows aggressive scaling of the access gate length down to 160 nm. A gate voltage as low as 1 V can be used for reading the cell, so there is no need for voltage boosting. The source-side injection programming speed is increased by one order of magnitude for devices with thin access gate oxide. The compact cell is suited for embedded applications in sub-100-nm CMOS generations.     

A high power MOSFET with a vertical drain electrode and a meshed gate structure

A MOSFET with a maximum power of 200 W in a 5/spl times/5 mm/SUP 2/ chip which exhibits 20-A current, 3000-millimho transconductance and 100-V breakdown voltage has been developed. The features of the device structure are a vertical drain electrode which makes it possible to use most of the surface area for the source electrode, and a meshed gate structure which realizes an increase in the channel width per unit area. The p-channel device with an offset gate structure was fabricated from an n on p/SUP +/ epitaxial wafer by using polysilicon gate and ion implantation processes. The device can be operated stably at ambient temperatures up to 180/spl deg/C. While the bipolar transistor is a suitable power device in the low voltage region, the MOSFET looks more promising in the high voltage region than the V-FET and the bipolar transistor.     

Technology of a new n-channel one-transistor EAROM cell called SIMOS

The structure and technology of a new nonvolatile charge-storage device are described. The stacked-gate injection MOS (SIMOS) device is an n-channel MOS transistor with a control gate stacked on the floating gate. In the programming mode, electrons are accelerated by the channel drift field to energies high enough to overcome the barrier height of the Si-SiO2interface and so injected into the floating gate. On account of the channel-injection mechanism performed in the programming mode, channel lengths of less than 4 µm are required. A combination of this condition with the stacked-gate concept is achieved by a self-aligned technique which defines both polysilicon gates by a single photolithographic procedure. By means of the self-aligned technique, both the one-transistor EPROM cell and the one-transistor EAROM cell can be realized. Basic structures of the two different type one-transistor memory cells are the SIMOS transistor and the SIMOS tetrode, respectively. The technology of these two different SIMOS devices is described in detail and experimental results concerning charge accumulation, charge removal, and charge retention are reported.