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1.
A novel approach to the construction of a flash-type Josephson A/D (analog/digital) converter is presented. Simulations show that one-junction SQUID (superconducting quantum interference device) comparators can have a greater than fivefold advantage in bandwidth over the two- or three-junction SQUIDs in an A/D circuit. Assuming a Nb junction technology, the simulations show that a 6-bit A/D converter using one-junction SQUID comparators could have a sampling rate of ~20 GHz with ~5 bits of resolution for a 5-GHz input signal. Detailed analysis and simulations of an A/D converter constructed with one-junction SQUIDs are presented. Further improvement can be made by using a coding algorithm which requires 2N-1 comparators, instead of N, for an N-bit A/D converter  相似文献   

2.
An analog-to-digital (A/D) converter is presented based on the repeated comparison at random intervals of the input voltage with the instantaneous value of a triangular waveform. This asynchronous sampling of a triangular waveform results in a converter, which features simplicity, both in conversion principle and circuit design, as the linearity merely depends on short-term stability of nonprecision components. The resolution increases with the number of samples and a tradeoff is possible between resolution and conversion time. In intelligent sensors the transducer, the signal conditioning circuits, and the A/D converter are integrated in a single chip. The required IC-process compatibility of all these subsystems narrows the range of the possibilities for implementing special processing steps to realize precision components, which favors the application of the stochastic A/D converter  相似文献   

3.
The authors discuss the causes of speed limitations in various A/D (analog/digital) converter designs. The upper limit on bandwidth is extracted with the help of Josephson SPICE simulations. In the Josephson A/D converter circuits discussed, the dynamic properties of the SQUIDs (superconducting quantum interference devices) determine the aperture time and dictate the bandwidth. Designs for 4-bit A/D converters that show potential for bandwidths on the order of 10 GHz are described. Particular attention is given to the bit-parallel A/D converter with self-gating AND comparator and bit-parallel A/D converters with CLAM (current latching analog microcomparator) and variable-pulse peak comparators  相似文献   

4.
An algorithmic stage for bipolar 1-b analog-to-digital (A/D) conversion using a unity-gain buffer is proposed. Cyclic and pipeline A/D converter architectures using this stage iteratively or in cascade are also described. Error analysis and SPICE simulations show that a conversion accuracy higher than 8-b and a conversion rate up to 10 Mb/s are attainable with presently available 3-μm CMOS technologies. Video frequency operation is also possible with finer linewidths. The component requirement is minimum, and thus it is best suited for an analog interface in application-specific integrated circuits (ASIC). A prototype cyclid A/D converter built using discrete components confirms the principles of operation  相似文献   

5.
An integration-type high-speed analog-to-digital converter   总被引:1,自引:0,他引:1  
An analog-to-digital (A/D) converter consisting of a switched-capacitor integrator, comparator, and control circuit is presented. The conversion process consists of voltage-to-frequency (V/F) conversion to determine the upper M bits of an N-bit representation of an analog input voltage and the subsequent voltage-to-time (V/T) conversion to determine the remaining lower N -M bits. The total clock cycle required for N-bit resolution is 2M+2N-M at most. The circuits for the V/F and V/T conversion share most of the components and thus the converter can be implemented with the minimum component count. Error analysis shows that a conversion accuracy higher than 12 bits can be expected from its CMOS monolithic realization. Prototype converters built using discrete components have confirmed the principles of operation  相似文献   

6.
The author proposes to use spectral averaging techniques to measure the harmonic distortion and noise floor of an analog/digital (A/D) digitizing subsystem. The noise floor of an ideal B-bit A/D converter is derived in closed form. It is shown that this noise floor is a function of the A/D resolution B, the record length N, and the equivalent noise bandwidth EB of the window function used in the discrete-Fourier-transform (DFT) computation. For an example, the noise floor is given for the case in which the magnitude square of the spectrum is averaged. Both experimental and simulation results are presented and it is shown that they are in good agreement with the theoretical results  相似文献   

7.
Analog-to-digital (A/D) converter performances are constantly improving, concerning both conversion speed and resolution. Consequently, characterization becomes harder as the limits of the testing instrumentation are reached. We tried to answer that problem by defining a test methodology based on “dual-tone” spectral analysis. In this paper we present both the basic principles of this method and also experimental results on A/D converters  相似文献   

8.
介绍了一种利用最新研发的电子元件和电流检测技术设计的DC 100A直流电流标准装置.该标准采用"ZERO-FLUK"技术解决了电流采样单元的零温漂、零功耗问题;采用高分辨力数模转换控制电路解决了系统控制精度和稳定性的问题.  相似文献   

9.
A resistance deviation-to-pulsewidth converter is presented for interfacing resistive sensors. It consists of a ramp integrator, two resistance-tunable Schmitt triggers, and two logic gates. A prototype circuit built using discrete components exhibits a resolution as high as 14 bits and a linearity error less than plusmn0.06% when the output pulse is counted by a 10-MHz clock signal. The proposed circuit is applied to measure the temperature difference with the platinum resistance temperature detectors. The measured conversion sensitivity of the temperature difference-to-pulsewidth converter is 5.74 mus/degC, and its linearity error is less than plusmn1% in the temperature difference range of 0degC to 100degC.  相似文献   

10.
《IEEE sensors journal》2008,8(10):1620-1627
A new low cost converter topology is proposed for sinusoidal position encoders. The converter enables determination of the angle from the sine and cosine signals of the encoder. When used with resolvers, the implementation of the present scheme takes advantage of the available excitation signal used to operate the device. This trigonometric reference signal is optimally used to generate an analogue signal equivalent to a digital look-up table (LUT). This enables determination of the mechanical angle without using LUT, A/D, and D/A converters. The scheme is optimized in order to achieve highest possible precision. Beside simplicity of its implementation, the proposed converter offers the advantage of robustness to amplitude fluctuation of the transducer excitation signal. The converter was implemented using ordinary low-cost analog components. The theory of operation, computer simulation, and experimental results are given.   相似文献   

11.
一种新型的大动态范围CCD相机视频信号处理电路   总被引:1,自引:1,他引:0  
由于目前的CCD尤其科学级CCD的动态范围高达105:1,甚至106:1,此时若要满足ADC的动态范围大于CCD相机的动态范围,则必须选择分辨力为18~20bit的ADC,而航天级或高等级的高分辨力ADC较少且价格昂贵。本文利用CCD相机系统的噪声谱密度跟信号大小有密切关系这一特点,对于强光信号和弱光信号采用不同的信号处理链,从系统通道增益的角度阐述了低分辨力ADC实现高分辨力模数转换的原理及硬件实现方案,最后通过实验室成像测试验证,实验结果表明,用低分辨力A/D转换器采用粗细量化相结合方式实现了高分辨力模数转换,并提高了CCD相机的动态范围。  相似文献   

12.
张杨 《计量学报》1994,15(2):121-125,158
本文介绍一种个人微机仪器(PCI)式数字示波器的硬件、软件原理。该仪器采用高速并行A/D变换器进行数据采集,其数字化率为20MS/s,分辨率为8bit。微机控制输入信号的放大和采集,并把采集到的信号实时地显示在微机的监视器上。该仪器不但具有一般双通道数字示波器的功能,而且在不增加硬件投人的情况下,只要编写相应的应用软件就可以对两路输人波形进行分析、运算。适用于电子学研究、生物学研究,以及电子、磁性材料测试和医疗监视等各个领域。  相似文献   

13.
A novel automatically synchronized ramp analog-to-digital (A/D) converter is described. The main feature of this system is that the same master oscillator is used for producing sawtooth waves and digitization waves. This system avoids the errors which appear in conventional systems because of nonsynchronization. Experimental testing of the concept was done using a 1-MHz frequency crystal  相似文献   

14.
A high-resolution, linear resistance-to-frequency converter   总被引:2,自引:0,他引:2  
A resistance-to-frequency converter consisting of a Wheatstone bridge followed by an integrator and a comparator is described. In concept the circuit represents a relaxation oscillator whose frequency changes linearly with a resistance change detected by the bridge. Analyses show that a resolution better than 0.05% is possible with the simple configuration, and an excellent linearity is maintained over the wide resistance change by using a simple compensation method. The converter is therefore suited as a signal conditioner of a resistive sensor. Experimental results are included to demonstrate its performance  相似文献   

15.
A Hopfield-type neural network approach which leads to an analog circuit for implementing the A/D conversion is presented. The solution of the original symmetric connection Hopfield A/D converter sometimes may reach a “spurious state” that does not correspond to the correct digital representation of the input signal. An A/D converter based on the model of nonsymmetrical neural networks is proposed to obtain the stable and correct encoding. Due to the infeasible conventional RC-active implementation, a cost-effective switched-capacitor implementation by means of Schmitt triggers is adopted. It is capable of achieving high performance as well as a high convergence rate. Finally, a simulation using a tool called SWITCAP is conducted to verify the validity and performance of the proposed implementation  相似文献   

16.
In this paper, we investigate the problem of the D/A converter with nonuniformly sampled input data. The input digital data were obtained by sampling the intended analog waveform at nonuniform time intervals, and we look into the question: “Given that the timing offset of each data sample is known, would it be beneficial, in terms of the output signal-to-noise ratio, to use this offset to adjust the playback timing of the D/A converter?” We examine two different timing strategies. The first approach simply plays out the signal at a uniform rate, while the second one uses the known timing offset to adjust the D/A converter playback timing accordingly. The closed-form expressions of the spectrum of the D/A converter output signals are derived. From these expressions, we find that the spectrum structure, for the case where the timing offsets are compensated, is the infinite sum of the weighted shift to the baseband spectrum. For the uniform playout approach, the spectrum structure is much more complicated where each shifted spectrum is modified by a different weighting function of the frequency. Although the spectrum structure may be conceptually simpler for the case where the timing offsets are compensated, it is by no means clear that either method is better than the other in terms of the output waveform quality. We then apply the results to analyze the direct digital synthesis output sine waves. The signal-to-noise ratio, SNR, for both cases is derived in simple closed form. It is found that for the case where the timing offsets are compensated, the SNR can be greatly enhanced by appropriate selection of operation parameters  相似文献   

17.
多数制式混沌A/D变换器研究   总被引:7,自引:2,他引:5  
从目前的工程观点来看,一个本身不稳定的A/D变换器是不可能用来进行精确的A/D变换的。本提出可用极不稳定的混沌电路实现精确稳定的A/D变换,并且可随意改变为2、3等进制的A/D变换。虽然其精度目前还未超过现有的A/D变换器,但这是一种全新意义上的A/D变换,值得进一步研究。  相似文献   

18.
This paper describes a novel digital-to-analog (D/A) conversion technique, which uses the analog quantity polarization as a D/A conversion medium. It can be implemented by CMOS capacitors or by ferroelectric capacitors, which exhibit strong nonlinearity in charge versus voltage behavior. Because a ferroelectric material inherently has spontaneous polarization and generally has a large dielectric constant, the effective capacitance of a ferroelectric capacitor is much larger than that of a CMOS capacitor of the same size. This ensures less influence of bottom-electrode parasitic capacitance on a ferroelectric capacitor. Furthermore, a data converter based on ferroelectric capacitors possesses the potential nonvolatile memory function owing to ferroelectric hysteresis. Along with the architecture proposed for polarization-switching digital-to-analog converter (PDAC), its circuit implementation is introduced. Described is implementation of two 9-bit bipolar PDACs: one is based on CMOS capacitors and the other on off-chip ferroelectric capacitors. Experimental results are presented for the performance of these two prototypes.  相似文献   

19.
Nonlinear analog-to-digital conversion in smart sensor applications is an important topic since signal digitization and linearization can be performed in a single step near the transducer. In this paper a double pulsewidth modulated (PWM) scheme for nonlinear analog-to-digital conversion is presented. Calibration or auto-calibration data stored in the smart sensor's memory define the nonlinear profile characteristic of the transducer and provide the required data to obtain the inverse function of the analog-to-digital converter (ADC) transfer curve. Basically, as a function of the transducer's nonlinearity degree, the input voltage range of the ADC is segmented in a continuous set of subintervals and, for each of these subintervals, a second-order correction term based on a PWM A/D conversion is used to obtain a linear characteristic for the smart sensor. Additional advantages of this method result from its easy implementation in low-cost microcontrollers that include generally comparator inputs and PWM outputs. A flexible and programmable A/D conversion solution can be dynamically adapted to variations of the transducer's nonlinearity profile, and an increased resolution can be achieved at the expense of a lower conversion rate. Some MATLAB simulations and experimental results obtained with a square-root airflow transducer will be presented in the final part of the paper  相似文献   

20.
鞠静  熊健 《光电工程》1997,24(2):30-33
介绍了在红外系统中,采用步进电机作为扫描机构驱动元件,以D/A数模转换器作细分方式的定频脉宽调制驱动方式,实现微机控制下的扫描机的构步距均匀稳定,满足红外系统分辨率的要求。  相似文献   

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