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Traditional and some recently reported low power,high speed and high resolution approaches for SAR A/D converters are discussed.Based on SMIC 65 nm CMOS technology,two typical low power methods reported in previous works are validated by circuit design and simulation.Design challenges and considerations for high speed SAR A/D converters are presented.Moreover,an R–C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process.The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively.With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively,and the power dissipation is measured to be just 3.17 mW. 相似文献
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本文在0.18μm CMOS工艺下,实现了一款10位50MS/s两级逐次逼近流水线混合型模数转换器(pipeline SAR ADC)。其由基于逐次逼近的增益模数单元和逐次逼近ADC组成,并采用1位冗余位放宽了子模数转换器的比较误差。通过采用逐次逼近结构,增益减半MDAC技术,动态比较器及动态逐次逼近控制逻辑,降低了模数转换器的功耗和面积。流片测试结果表明,在1.8V电源电压,50MS/s采样速率下,信噪失真比(SFDR)和功耗分别为56.04dB和5mV。 相似文献
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采用流水折叠结构设计了一种10位100-MSample/s A/D转换器。失调取消技术和电阻平均插值网络提高了转换器的线性度。级联结构放宽了折叠放大器的带宽要求,采用分布式级间跟踪保持放大器实现流水线技术来获得更高的转换精度。基于SMIC 0.18 μm CMOS工艺的测试结果如下:INL和DNL的峰值分别为0.48 LSB and 0.33 LSB。输入电压范围VP-P为1.0 V,芯片面积2.29 mm2。100 MHz采样,20 MHz输入信号下,ENOB为9.59位,SNDR为59.5 dB,SFDR为82.49 dB。1.8V电源电压下功耗仅为95 mW。 相似文献
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提出了一种10位200 MHz CMOS电流舵视频D/A转换器(DAC)实现电路。权衡线性度、功耗、面积以及弱化毛刺等因素,该DAC的高6位采用单位译码矩阵,低4位采用二进制加权阵列。采用新型开关策略,进一步提高单位译码矩阵的线性度;设计带平滑电路的电流源与差分开关电路,以提高动态性能。整个芯片采用新加坡特许半导体公司3.3 V工作电压、0.35μm2P2M CMOS工艺制造。DAC的面积为1.26 mm×0.78 mm,其积分非线性误差和微分非线性误差均小于±0.2 LSB。 相似文献
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A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shifters are utilized. Design chal-lenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlin-earity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238×214 μm~2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications. 相似文献
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Traditional and some recently reported low power, high speed and high resolution approaches for SAR A/D converters are discussed. Based on SMIC 65 nm CMOS technology, two typical low power methods reported in previous works are validated by circuit design and simulation. Design challenges and considerations for high speed SAR A/D converters are presented. Moreover, an R-C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process. The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively. With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively, and the power dissipation is measured to be just 3.17 mW. 相似文献
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采用“5MSBs (Most-Significant-Bits) + 5LSBs (Least-Significant-Bits)”C-R混合式D/A转换方式以及低失调伪差分比较技术,结合电容阵列对称布局以及电阻梯低失配版图设计方法,基于0.18µm 1P5M CMOS Logic工艺,设计实现了一种用于触摸屏SoC (System-on-Chip)的8通道10位200kS/s逐次逼近型A/D转换器IP核。在1.8V电源电压下,测得的微分非线性误差和积分非线性误差分别为0.32LSB和0.81LSB。在采样频率为200kS/s,输入频率为91kHz时,测得的无杂散动态范围(SFDR: Spurious-Free Dynamic Range)和有效位数(ENOB: Effective-Number-of-Bits)分别为63.2dB和9.15bits,功耗仅为136µW。整个A/D转换器IP核的面积约为0.08mm2。设计结果显示该转换器满足触摸屏SoC的应用要求。 相似文献
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Based on a 5 MSBs(most-significant-bits)-plus-5 LSBs(least-significant-bits) C-R hybrid D/A conversion and low-offset pseudo-differential comparison approach,with capacitor array axially symmetric layout topology and resistor string low gradient mismatch placement method,an 8-channel 10-bit 200-kS/s SAR ADC(successive-approximation -register analog-to-digital converter) IP core for a touch screen SoC(system-on-chip) is implemented in a 0.18μm 1P5M CMOS logic process.Design considerations for the touch sc... 相似文献
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Tal Vitaly Zlotnikov Ofir Degani Igor Brouk Yael Nemirovsky 《Microelectronics Journal》2011,42(10):1143-1150
We present analysis, optimization, design and characterization of an integrated passive analog phase shifter at 24 GHz in a commercially available 45 nm RF-CMOS process. The design is based on a well-known RC bridge topology, which was optimized for maximum phase shift and minimal amplitude response variation versus phase and frequency. Phase is controlled by varying DC voltage on a varactor, resulting in 60° maximum phase shift with 0.1 dB amplitude variation at 24 GHz. The size of the phase shifter circuit excluding pads and input/output buffers is 40×50 μm2. 相似文献
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一种CMOS折叠结构ADC中的失调抵消技术 总被引:4,自引:2,他引:2
CMOS折叠预放电路的失调是限制CMOS折叠结构A/ D转换器实现高分辨率应用的主要原因之一.文中提出差分对的动态匹配技术改善了折叠预放电路的失调,从而为研制CMOS工艺中的高分辨率折叠结构A/ D转换器提供了一种可行方案,并给出了MATL AB和电路仿真的实验结果. 相似文献
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This article is presented to describe an area-efficient CMOS folding and interpolating analog-to-digital converter (ADC) for
embedded application, which is fully compatible with standard digital CMOS technology. A modified MOS-transistor-only folding
block contributes to a small chip area. At the input stage, offset averaging reduces the input capacitance and the distributed
track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio (SNDR). An INL/DNL of 0.77 LSB/0.6 LSB was measured. An SNDR figure of 43.7 dB is achieved at 4 MHz input frequencies when operated at full speed of 200 MHz. The chip is realized in a standard digital 0.18 μm CMOS technology and consumes a total power of 181 mW from 3.3 V power supply. The active area is 0.25 mm2. 相似文献