A heuristic storage for minimizing access time of arbitrary datapatterns

The serialization of memory accesses is a major limiting factor in high performance SIMD computers. The data patterns or templates that are accessed by a program can be perceived by the compiler, and, therefore, the design of dynamic storage schemes that minimize conflicts may dramatically improve performance. The problem of finding storage schemes that minimize the access time of arbitrary sets of power-of-two data patterns is proved to be NP-complete. We propose linear address transformations that can be dynamically applied by each processing element for mapping array references onto memories. An efficient approach for combining the constraints of different access patterns into one single linear address transformation is presented. We prove that finding the transformation that minimizes the access time is reducible to N-coloring, where N is the number of parallel memories. Using coloring heuristics, storage schemes are investigated with respect to minimizing the implementation cost (perfect storage) and overall access conflicts (semiperfect storage). Results show that the perfect-storage may deviate on the average by 20% from the optimum access time in the case of 10 arbitrary data patterns and 16 memories. However, semiperfect schemes lead to dramatic reduction of the degree of conflict compared to perfect-schemes. The proposed heuristic storage largely outperforms interleaving and row-column-diagonals storages. The method can be implemented as compiler procedure for synthesizing storage schemes that promote parallel access to arbitrary sets of data patterns     

Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells

Emerging non-volatile memories (e.g. STT-MRAM, OxRRAM and CBRAM) based on resistive switching are under intense research and development investigation by both academics and industries. They provide high performance such as fast write/read speed, low power and good endurance (e.g. >10¹²), and could be used as both computing and storage memories beyond flash memories. However the conventional access architecture based on 1 transistor + 1 memory cell limits its storage density as the selection transistor should be large enough to ensure enough current for the switching operation. This paper presents the design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells with a particular focus on reliability and power performance investigation. This architecture allows fewer selection transistors, and minimum contacts between memory cells and CMOS control circuits. The complementary cell and parallel data sensing mitigate the impact of sneak currents in the crossbar architecture and provide fast data access for computing purpose. We perform transient and statistical simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the functionality of this design by using CMOS 40 nm design kit and memory compact models, which were developed based on relative physics and experimental parameters.     

Design and Analysis of High-Capacity Associative Memories Based on a Class of Discrete-Time Recurrent Neural Networks

This paper presents a design method for synthesizing associative memories based on discrete-time recurrent neural networks. The proposed procedure enables both hetero- and autoassociative memories to be synthesized with high storage capacity and assured global asymptotic stability. The stored patterns are retrieved by feeding probes via external inputs rather than initial conditions. As typical representatives, discrete-time cellular neural networks (CNNs) designed with space-invariant cloning templates are examined in detail. In particular, it is shown that procedure herein can determine the input matrix of any CNN based on a space-invariant cloning template which involves only a few design parameters. Two specific examples and many experimental results are included to demonstrate the characteristics and performance of the designed associative memories.      

Gray-scale morphological associative memories

Neural models of associative memories are usually concerned with the storage and the retrieval of binary or bipolar patterns. Thus far, the emphasis in research on morphological associative memory systems has been on binary models, although a number of notable features of autoassociative morphological memories (AMMs) such as optimal absolute storage capacity and one-step convergence have been shown to hold in the general, gray-scale setting. In this paper, we make extensive use of minimax algebra to analyze gray-scale autoassociative morphological memories. Specifically, we provide a complete characterization of the fixed points and basins of attractions which allows us to describe the storage and recall mechanisms of gray-scale AMMs. Computer simulations using gray-scale images illustrate our rigorous mathematical results on the storage capacity and the noise tolerance of gray-scale morphological associative memories (MAMs). Finally, we introduce a modified gray-scale AMM model that yields a fixed point which is closest to the input pattern with respect to the Chebyshev distance and show how gray-scale AMMs can be used as classifiers.     

用非线性存储方案设计SIMD计算机的一般方法

非线性存储方案能在处理单元数等于存储体数的情况下,使ＳＩＭＤ机实现多种访存模式无冲突,提高其整体性能,文中提出一种用线性存储方案设计ＳＩＭＤ 一般方法,在存储方案给定的前提下,针对有限的模板集设计出同时满足存储器访问无冲突和互联网的并行结构,首先,用布尔向量空间表示模板,并指出模板与ＬＣ置换的对应关系,在此基础上,提出设计局部地址生成逻辑和增强的间接二进制Ｎ方体网络的方法,由于板集中任意的访存方式     

井下三轴振动信号同步采集与大容量存储系统设计

随钻三轴振动信号同步采集和大容量数据实时存储一直是钻井工程中的难点。设计一种基于AD7980级联的三轴振动信号同步采集电路,以M25P64作为基本存储器,采用SPI总线硬件扩容与软件压缩相结合的方法实现了井下大容量数据存储。试验结果表明,该设计能够满足在井下200 h不间断情况下三轴振动信号同步采集和数据存储实际需要。     

Holographic data storage

Research into and the development of data storage devices is a race to keep up with the continuing demand for more capacity, more density, and faster readout rates. Improvements in conventional memory technologies-magnetic hard disk drives, optical disks, and semiconductor memories-have managed to keep pace with the demand for bigger, faster memories. However, there is strong evidence that these two-dimensional surface storage technologies are approaching fundamental limits. An alternative approach for next-generation memories is to store data in three dimensions. This article describes developments in holographic 3D memories, in which high density is achieved by superimposing many holograms within the same volume of recording material. Holographic storage is a promising candidate for next-generation storage. Research has demonstrated that holographic storage systems with desirable properties can be engineered. The next step is to build these systems at costs competitive with those of existing technologies and to optimize the storage media     

Implicative Fuzzy Associative Memories

Associative neural memories are models of biological phenomena that allow for the storage of pattern associations and the retrieval of the desired output pattern upon presentation of a possibly noisy or incomplete version of an input pattern. In this paper, we introduce implicative fuzzy associative memories (IFAMs), a class of associative neural memories based on fuzzy set theory. An IFAM consists of a network of completely interconnected Pedrycz logic neurons with threshold whose connection weights are determined by the minimum of implications of presynaptic and postsynaptic activations. We present a series of results for autoassociative models including one pass convergence, unlimited storage capacity and tolerance with respect to eroded patterns. Finally, we present some results on fixed points and discuss the relationship between implicative fuzzy associative memories and morphological associative memories     

Recurrent correlation associative memories

A model for a class of high-capacity associative memories is presented. Since they are based on two-layer recurrent neural networks and their operations depend on the correlation measure, these associative memories are called recurrent correlation associative memories (RCAMs). The RCAMs are shown to be asymptotically stable in both synchronous and asynchronous (sequential) update modes as long as their weighting functions are continuous and monotone nondecreasing. In particular, a high-capacity RCAM named the exponential correlation associative memory (ECAM) is proposed. The asymptotic storage capacity of the ECAM scales exponentially with the length of memory patterns, and it meets the ultimate upper bound for the capacity of associative memories. The asymptotic storage capacity of the ECAM with limited dynamic range in its exponentiation nodes is found to be proportional to that dynamic range. Design and fabrication of a 3-mm CMOS ECAM chip is reported. The prototype chip can store 32 24-bit memory patterns, and its speed is higher than one associative recall operation every 3 mus. An application of the ECAM chip to vector quantization is also described.     

Analysis and synthesis of a class of discrete-time neural networksdescribed on hypercubes

A qualitative analysis is presented for a class of synchronous discrete-time neural networks defined on hypercubes in the state space. Analysis results are utilized to establish a design procedure for associative memories to be implemented on the present class of neural networks. To demonstrate the storage ability and flexibility of the synthesis procedure, several specific examples are considered. The design procedure has essentially the same desirable features as the results of J. Li et al. (1988, 1989) for continuous-time neural networks. For a given system dimension, networks designed by the present method may have the ability to store more patterns (as asymptotically stable equilibria) than corresponding discrete-time networks designed by other techniques. The design method guarantees the storage of all the desired patterns as asymptotically stable equilibrium points. The present method provides guidelines for reducing the number of spurious states and for estimating the extent of the patterns' domains of attraction. The present results provide a means of implementing neural networks by serial processors and special digital hardware.     

DEMON-BASED ASSOCIATIVE MEMORIES

Associative memories are of two fundamental types, those that store representations of prototypical patterns (auto-associative memories)and those that store associations between pairs of arbitrary patterns (hetero-associative memories)Four network models of the latter type, each employing a single layer of linear threshold units are presented. Two of these models maintain fixed arrangements of their components. The other two are dynamically self-organizing. They employ feedback about performance to guide changes in the organization of their components. These models are evaluated in terms of storage capacity, error-tolerance, and storage space efficiency. One form of dynamic memory has the highest storage capacity of any known network model of associative memory. A discussion of models by Anderson and Hopfield and some implications of static and dynamic architectures conclude the paper.     

Application of associative memories in designing assemblers

A method for implementing the assembler of a system by hardware is described. The implementation is based on using the associative memories for storing various tables that are maintained by the assembler during different phases of assembling. The assembling is done in two passes. This hardware implementation results in less assembling time and main storage requirements than its software counterpart. Also the method offers a good amount of design flexibility to fit into different systems.     

Design of swing arm actuator for small and slim optical disc drives

Recent advancements in mobile devices have fueled a requirement for information storage systems with characteristics such as subminiature size, low cost, and minimum power consumption. Small optical disk drives could provide a good solution, because their storage media is cheaper than those of hard disk drives or flash memories. In this paper, we proposed the miniaturized swing arm type actuator that had a new focusing mechanism for small and slim optical disk drives (ODD). Initial model was designed by EM and structural analyses. Based on results of DOE, optimization procedures of EM circuits were performed with design variables using variable metric method (VMM). And, structural parts were designed to maintain the high sensitivity of the actuator. Finally, the swing arm type actuator for small and slim ODDs was suggested and its dynamic characteristics were checked.     

The Implications of Electronic Serial Memories*

Advances in such new memory technologies as charge-coupled devices, magnetic bubble memories, and beam access memories have opened avenues for innovative applications of these computer elements in future computing systems. These quasi-serial electronic technologies compete on one hand with the random access memories (bipolar, MOS, and core) and, on the other hand, with disk memories (fixed-head disk and moving-head disk). There are important functional properties common to all these technologies, and their applications as computer memories will depend upon how successfully the systems designers appreciate–and then apply–these characteristics to computer system design.     

Information Processing with an Associative Parallel Processor

Research into new computer structures, which would be better suited to non-numerical information processing tasks, has been in progress for some years.^1,2,3The problem has been to design a computing system with high hardware efficiency and low software complexity over a wide range of these applications. Recent research^4,5,6has indicated that these apparently conflicting requirements could possibly be achieved by a parallel processing system containing content-addressable storage. Hence there is a revival of interest in associative memories and associative processors.     

A hybrid flash translation layer design for SLC-MLC flash memory based multibank solid state disk

This paper presents the design of a NAND flash based solid state disk (SSD), which can support various storage access patterns commonly observed in a PC environment. It is based on a hybrid model of high-performance SLC (single-level cell) NAND and low cost MLC (multi-level cell) NAND flash memories. Typically, SLC NAND has a higher transfer rate and greater cell endurance than MLC NAND flash memory. MLC NAND, on the other hand, benefits from lower price and higher capacity. In order to achieve higher performance than traditional SSDs, an interleaving technique that places NAND flash chips in parallel is essential. However, using the traditional FTL (flash translation layer) on an SSD with only MLC NAND chips is inefficient because the size of a logical block becomes large as the mapping address unit grows. In this paper, we proposed a HFTL (hybrid flash translation layer) which makes use of chained-blocks, combining SLC NAND and MLC NAND flash memories in parallel. Experimental results show that for most of the traces studied, the HFTL in an SSD configuration composed of 80% MLC NAND and 20% SLC NAND memories can improve performance compared to other solid state disk configurations, composed of either SLC NAND or MLC NAND flash memory alone.     

Built-In Self-Testing RAM: A Practical Alternative

The article investigates the design of a built-in self-testing RAM as an economical way, in terms of silicon area overhead, to test memories?more economical than the use of external testers. The design of a BIST static RAM is given, along with design decisions, retrospectives on how design could have used the area even more efficiently, and results of implementation. The extra silicon area used by the BIST hardware for 64K static memories is only five percent; for larger memories, it is less. BIST RAM, then, is a practical alternative, especially since testing can be done even during burn-in without the aid of an expensive external tester.     

A high performance NAND array file system based on multiple NAND flash memories

The existing NAND flash memory file systems have not taken into account multiple NAND flash memories for large-capacity storage. In addition, since large-capacity NAND flash memory is much more expensive than the same capacity hard disk drive, it is cost wise infeasible to build large-capacity flash drives. To resolve these problems, this paper suggests a new file system called NAFS for large-capacity storage with multiple small-capacity and low-cost NAND flash memories. It adopts a new cache policy, mount scheme, and garbage collection scheme in order to improve read and write performance, to reduce the mount time, and to improve the wear-leveling effectiveness. Our performance results show that NAFS is more suitable for large-capacity storage than conventional NAND file systems such as YAFFS2 and JFFS2 and a disk-based file system for Linux such as HDD-RAID5-EXT3 in terms of the read and write transfer rate using a double cache policy and the mount time using metadata stored on a separate partition. We also demonstrate that the wear-leveling effectiveness of NAFS can be improved by our adaptive garbage collection scheme.     

An economical tonal display for interactive graphics and image analysis data

The use of tonal displays in image analysis and interactive graphics has always dictated the use of expensive refresh memories for the display output device. This has involved the use of high speed digital drums, multiple head discs, and analog storage tubes. Recently, the introduction of very long shift registers has allowed the designer to consider their use for refresh memories. A prototype display using 1024 bit MOS static shift registers has been developed. It has been shown that a reasonable cost versus performance tradeoff can be obtained. The first efforts has resulted in a 128 × 128 × 4 bit (64k) memory; it is now in the process of being expanded to 256 × 256 × 8 bits (512k). This memory is cost competitive with digital disc memories and both cost and performance competitive with storage tube scan converters.     

Sparsely Connected Autoassociative Lattice Memories with an Application for the Reconstruction of Color Images

Sparsely connected autoassociative lattice memories (SCALMs) are very general models defined on complete lattices, a mathematical structure which is obtained by imposing some ordering on a set. They are computationally cheaper and mathematically simpler than ??traditional?? models and other memories such as the original autoassociative morphological memories (AMMs) of Ritter and Sussner because they only compute maximums and minimums. This paper provides theoretical results on SCALMs defined on a general complete lattice as well as an application of these memories for the storage and recall of color images. Precisely, we characterize the recall phase of SCALMs in terms of their fixed points. Then, we show that any endomorphic lattice polynomial??a concept that generalizes the notion of lattice polynomial of Birkhoff??on the fundamental memory set represents a fixed point of the SCALMs. Also, we discuss the relationship between SCALMs and the original AMMs. Finally, we provide some experimental results on the performance of SCALMs, defined on different color lattices, for the reconstruction of color images corrupted by either Gaussian or impulsive noise.